321a322
> #if ISA_HAS_DELAY_SLOT
322a324
> #endif
505,507c507,510
< next_PC = next_NPC;
< next_NPC = next_NPC + instSize;
< inst->setPredTarg(next_PC, next_NPC);
---
> Addr cur_PC = next_PC;
> next_PC = cur_PC + instSize; //next_NPC;
> next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
> inst->setPredTarg(next_NPC);
510c513
< inst->setPredTarg(next_PC, next_PC + sizeof(TheISA::MachInst));
---
> inst->setPredTarg(next_PC);
512d514
< inst->setPredTaken(false);
522c524
< DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken.\n", tid);
---
> DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
524c526
< DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid);
---
> DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
527d528
< next_PC = next_NPC;
528a530
> next_PC = next_NPC;
529a532
>
535c538,548
< } else {
---
> } else { // !predict_taken
> if (inst->isCondDelaySlot()) {
> next_PC = pred_PC;
> // The delay slot is skipped here if there is on
> // prediction
> } else {
> next_PC = next_NPC;
> // No need to declare a delay slot here since
> // there is no for the pred. target to jump
> }
>
541,544d553
< DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n",
< tid, next_PC, next_NPC);
< inst->setPredTarg(next_PC, next_NPC);
< inst->setPredTaken(predict_taken);
665,666c674
< DefaultFetch<Impl>::doSquash(const Addr &new_PC,
< const Addr &new_NPC, unsigned tid)
---
> DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
668,669c676,677
< DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
< tid, new_PC, new_NPC);
---
> DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
> tid, new_PC);
672,673c680,681
< nextPC[tid] = new_NPC;
< nextNPC[tid] = new_NPC + instSize;
---
> nextPC[tid] = new_PC + instSize;
> nextNPC[tid] = new_PC + (2 * instSize);
699c707
< DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
---
> DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
705c713
< doSquash(new_PC, new_NPC, tid);
---
> doSquash(new_PC, tid);
751c759,760
< std::list<unsigned>::iterator threads = (*activeThreads).begin();
---
> std::list<unsigned>::iterator threads = activeThreads->begin();
> std::list<unsigned>::iterator end = activeThreads->end();
753,754c762
< while (threads != (*activeThreads).end()) {
<
---
> while (threads != end) {
788,789c796
< DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
< const InstSeqNum &seq_num,
---
> DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
794c801
< doSquash(new_PC, new_NPC, tid);
---
> doSquash(new_PC, tid);
815c822,823
< std::list<unsigned>::iterator threads = (*activeThreads).begin();
---
> std::list<unsigned>::iterator threads = activeThreads->begin();
> std::list<unsigned>::iterator end = activeThreads->end();
820c828
< while (threads != (*activeThreads).end()) {
---
> while (threads != end) {
924d931
< fromCommit->commitInfo[tid].nextNPC,
982d988
< fromDecode->decodeInfo[tid].nextNPC,
1039,1040d1044
< Addr &fetch_NPC = nextPC[tid];
<
1097,1098c1101
< Addr next_NPC = fetch_NPC;
<
---
> Addr next_NPC = next_PC + instSize;
1116a1120,1122
> // Need to keep track of whether or not a delay slot
> // instruction has been fetched
>
1120c1126
< !predicted_branch;
---
> (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1123,1127d1128
< // If we're branching after this instruction, quite fetching
< // from the same block then.
< predicted_branch =
< (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
<
1147,1149c1148,1149
< DynInstPtr instruction = new DynInst(ext_inst,
< fetch_PC, fetch_NPC,
< next_PC, next_NPC,
---
> DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
> next_PC,
1161,1162d1160
< DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
<
1171c1169,1170
< lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
---
> predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
> next_NPC);
1187d1185
< fetch_NPC = next_NPC;
1198a1197,1219
>
> #if ISA_HAS_DELAY_SLOT
> if (predicted_branch) {
> delaySlotInfo[tid].branchSeqNum = inst_seq;
>
> DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
> tid, inst_seq);
> continue;
> } else if (delaySlotInfo[tid].numInsts > 0) {
> --delaySlotInfo[tid].numInsts;
>
> // It's OK to set PC to target of branch
> if (delaySlotInfo[tid].numInsts == 0) {
> delaySlotInfo[tid].targetReady = true;
>
> // Break the looping condition
> predicted_branch = true;
> }
>
> DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
> " process.\n", tid, delaySlotInfo[tid].numInsts);
> }
> #endif
1207c1228
< } else if (predicted_branch) {
---
> } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1224,1226c1245,1247
< PC[tid] = next_PC;
< nextPC[tid] = next_NPC;
< nextNPC[tid] = next_NPC + instSize;
---
> PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
> nextPC[tid] = next_PC + instSize; //next_NPC
> nextNPC[tid] = next_PC + (2 * instSize);
1346c1367,1369
< int tid = *((*activeThreads).begin());
---
> std::list<unsigned>::iterator thread = activeThreads->begin();
> assert(thread != activeThreads->end());
> int tid = *thread;
1396c1419,1420
< std::list<unsigned>::iterator threads = (*activeThreads).begin();
---
> std::list<unsigned>::iterator threads = activeThreads->begin();
> std::list<unsigned>::iterator end = activeThreads->end();
1398c1422
< while (threads != (*activeThreads).end()) {
---
> while (threads != end) {
1425a1450,1451
> std::list<unsigned>::iterator threads = activeThreads->begin();
> std::list<unsigned>::iterator end = activeThreads->end();
1427,1429c1453
< std::list<unsigned>::iterator threads = (*activeThreads).begin();
<
< while (threads != (*activeThreads).end()) {
---
> while (threads != end) {
1455c1479,1482
< std::list<unsigned>::iterator threads = (*activeThreads).begin();
---
> std::list<unsigned>::iterator thread = activeThreads->begin();
> assert(thread != activeThreads->end());
> unsigned tid = *thread;
>
1457c1484
< return *threads;
---
> return 0 * tid;