1117,1119d1116
< // Need to keep track of whether or not a delay slot
< // instruction has been fetched
<
1123c1120
< (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
---
> !predicted_branch;
1125a1123,1127
> // If we're branching after this instruction, quite fetching
> // from the same block then.
> predicted_branch =
> (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
>
1169,1170c1171
< predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
< next_NPC);
---
> lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
1185a1187
> fetch_NPC = next_NPC;
1197,1219d1198
<
< #if ISA_HAS_DELAY_SLOT
< if (predicted_branch) {
< delaySlotInfo[tid].branchSeqNum = inst_seq;
<
< DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
< tid, inst_seq);
< continue;
< } else if (delaySlotInfo[tid].numInsts > 0) {
< --delaySlotInfo[tid].numInsts;
<
< // It's OK to set PC to target of branch
< if (delaySlotInfo[tid].numInsts == 0) {
< delaySlotInfo[tid].targetReady = true;
<
< // Break the looping condition
< predicted_branch = true;
< }
<
< DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
< " process.\n", tid, delaySlotInfo[tid].numInsts);
< }
< #endif
1228c1207
< } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
---
> } else if (predicted_branch) {