154,183d153
< // Size of cache block.
< cacheBlkSize = 64;
<
< // Create mask to get rid of offset bits.
< cacheBlkMask = (cacheBlkSize - 1);
<
< for (int tid=0; tid < numThreads; tid++) {
<
< fetchStatus[tid] = Running;
<
< priorityList.push_back(tid);
<
< memReq[tid] = NULL;
<
< // Create space to store a cache line.
< cacheData[tid] = new uint8_t[cacheBlkSize];
< cacheDataPC[tid] = 0;
< cacheDataValid[tid] = false;
<
< delaySlotInfo[tid].branchSeqNum = -1;
< delaySlotInfo[tid].numInsts = 0;
< delaySlotInfo[tid].targetAddr = 0;
< delaySlotInfo[tid].targetReady = false;
<
< stalls[tid].decode = false;
< stalls[tid].rename = false;
< stalls[tid].iew = false;
< stalls[tid].commit = false;
< }
<
355a326,355
>
> // Size of cache block.
> cacheBlkSize = icachePort->peerBlockSize();
>
> // Create mask to get rid of offset bits.
> cacheBlkMask = (cacheBlkSize - 1);
>
> for (int tid=0; tid < numThreads; tid++) {
>
> fetchStatus[tid] = Running;
>
> priorityList.push_back(tid);
>
> memReq[tid] = NULL;
>
> // Create space to store a cache line.
> cacheData[tid] = new uint8_t[cacheBlkSize];
> cacheDataPC[tid] = 0;
> cacheDataValid[tid] = false;
>
> delaySlotInfo[tid].branchSeqNum = -1;
> delaySlotInfo[tid].numInsts = 0;
> delaySlotInfo[tid].targetAddr = 0;
> delaySlotInfo[tid].targetReady = false;
>
> stalls[tid].decode = false;
> stalls[tid].rename = false;
> stalls[tid].iew = false;
> stalls[tid].commit = false;
> }