66,67c66
< DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
< "functional call.");
---
> warn("Default fetch doesn't update it's state from a functional call.");
84d82
< DPRINTF(Fetch, "Received timing\n");
101,102c99
< : mem(params->mem),
< branchPred(params),
---
> : branchPred(params),
1123c1120,1124
< ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid));
---
> #if THE_ISA == ALPHA_ISA
> ext_inst = TheISA::makeExtMI(inst, fetch_PC);
> #elif THE_ISA == SPARC_ISA
> ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
> #endif
1166,1167c1167,1168
< DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
< curTick);
---
> // warn("%lli: Quiesce instruction encountered, halting fetch!",
> // curTick);
1281,1283d1281
< #else // !FULL_SYSTEM
< fetchStatus[tid] = TrapPending;
< status_change = true;
1284a1283,1285
> // warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
> #else // !FULL_SYSTEM
> warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1286,1287d1286
< DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
< tid, fault->name(), PC[tid]);