2c2
< * Copyright (c) 2010-2013 ARM Limited
---
> * Copyright (c) 2010-2014 ARM Limited
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< stalls[tid].rename = false;
< stalls[tid].iew = false;
< stalls[tid].commit = false;
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< assert(!stalls[i].decode);
< assert(!stalls[i].rename);
< assert(!stalls[i].iew);
< assert(!stalls[i].commit);
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< if (!(numInst < fetchWidth)) {
---
> // Don't send an instruction to decode if it can't handle it.
> // Asynchronous nature of this function's calling means we have to
> // check 2 signals to see if decode is stalled.
> if (!(numInst < fetchWidth) || stalls[tid].decode ||
> fromDecode->decodeBlock[tid]) {
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< } else if (stalls[tid].rename) {
< DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
< ret_val = true;
< } else if (stalls[tid].iew) {
< DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
< ret_val = true;
< } else if (stalls[tid].commit) {
< DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
< ret_val = true;
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< if (fromRename->renameBlock[tid]) {
< stalls[tid].rename = true;
< }
<
< if (fromRename->renameUnblock[tid]) {
< assert(stalls[tid].rename);
< assert(!fromRename->renameBlock[tid]);
< stalls[tid].rename = false;
< }
<
< if (fromIEW->iewBlock[tid]) {
< stalls[tid].iew = true;
< }
<
< if (fromIEW->iewUnblock[tid]) {
< assert(stalls[tid].iew);
< assert(!fromIEW->iewBlock[tid]);
< stalls[tid].iew = false;
< }
<
< if (fromCommit->commitBlock[tid]) {
< stalls[tid].commit = true;
< }
<
< if (fromCommit->commitUnblock[tid]) {
< assert(stalls[tid].commit);
< assert(!fromCommit->commitBlock[tid]);
< stalls[tid].commit = false;
< }
<
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< // Check ROB squash signals from commit.
< if (fromCommit->commitInfo[tid].robSquashing) {
< DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
<
< // Continue to squash.
< fetchStatus[tid] = Squashing;
<
< return true;
< }
<