290#if USE_CHECKER
291 if (cpu->checker) {
292 cpu->checker->setIcachePort(icachePort);
293 }
294#endif
295
296 // Schedule fetch to get the correct PC from the CPU
297 // scheduleFetchStartupEvent(1);
298
299 // Fetch needs to start fetching instructions at the very beginning,
300 // so it must start up in active state.
301 switchToActive();
302}
303
304template<class Impl>
305void
306DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
307{
308 DPRINTF(Fetch, "Setting the time buffer pointer.\n");
309 timeBuffer = time_buffer;
310
311 // Create wires to get information from proper places in time buffer.
312 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
313 fromRename = timeBuffer->getWire(-renameToFetchDelay);
314 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
315 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
316}
317
318template<class Impl>
319void
320DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
321{
322 DPRINTF(Fetch, "Setting active threads list pointer.\n");
323 activeThreads = at_ptr;
324}
325
326template<class Impl>
327void
328DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
329{
330 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
331 fetchQueue = fq_ptr;
332
333 // Create wire to write information to proper place in fetch queue.
334 toDecode = fetchQueue->getWire(0);
335}
336
337template<class Impl>
338void
339DefaultFetch<Impl>::initStage()
340{
341 // Setup PC and nextPC with initial state.
342 for (int tid = 0; tid < numThreads; tid++) {
343 PC[tid] = cpu->readPC(tid);
344 nextPC[tid] = cpu->readNextPC(tid);
345#if ISA_HAS_DELAY_SLOT
346 nextNPC[tid] = cpu->readNextNPC(tid);
347#endif
348 }
349}
350
351template<class Impl>
352void
353DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
354{
355 unsigned tid = pkt->req->getThreadNum();
356
357 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
358
359 // Only change the status if it's still waiting on the icache access
360 // to return.
361 if (fetchStatus[tid] != IcacheWaitResponse ||
362 pkt->req != memReq[tid] ||
363 isSwitchedOut()) {
364 ++fetchIcacheSquashes;
365 delete pkt->req;
366 delete pkt;
367 return;
368 }
369
370 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
371 cacheDataValid[tid] = true;
372
373 if (!drainPending) {
374 // Wake up the CPU (if it went to sleep and was waiting on
375 // this completion event).
376 cpu->wakeCPU();
377
378 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
379 tid);
380
381 switchToActive();
382 }
383
384 // Only switch to IcacheAccessComplete if we're not stalled as well.
385 if (checkStall(tid)) {
386 fetchStatus[tid] = Blocked;
387 } else {
388 fetchStatus[tid] = IcacheAccessComplete;
389 }
390
391 // Reset the mem req to NULL.
392 delete pkt->req;
393 delete pkt;
394 memReq[tid] = NULL;
395}
396
397template <class Impl>
398bool
399DefaultFetch<Impl>::drain()
400{
401 // Fetch is ready to drain at any time.
402 cpu->signalDrained();
403 drainPending = true;
404 return true;
405}
406
407template <class Impl>
408void
409DefaultFetch<Impl>::resume()
410{
411 drainPending = false;
412}
413
414template <class Impl>
415void
416DefaultFetch<Impl>::switchOut()
417{
418 switchedOut = true;
419 // Branch predictor needs to have its state cleared.
420 branchPred.switchOut();
421}
422
423template <class Impl>
424void
425DefaultFetch<Impl>::takeOverFrom()
426{
427 // Reset all state
428 for (int i = 0; i < Impl::MaxThreads; ++i) {
429 stalls[i].decode = 0;
430 stalls[i].rename = 0;
431 stalls[i].iew = 0;
432 stalls[i].commit = 0;
433 PC[i] = cpu->readPC(i);
434 nextPC[i] = cpu->readNextPC(i);
435#if ISA_HAS_DELAY_SLOT
436 nextNPC[i] = cpu->readNextNPC(i);
437 delaySlotInfo[i].branchSeqNum = -1;
438 delaySlotInfo[i].numInsts = 0;
439 delaySlotInfo[i].targetAddr = 0;
440 delaySlotInfo[i].targetReady = false;
441#endif
442 fetchStatus[i] = Running;
443 }
444 numInst = 0;
445 wroteToTimeBuffer = false;
446 _status = Inactive;
447 switchedOut = false;
448 interruptPending = false;
449 branchPred.takeOverFrom();
450}
451
452template <class Impl>
453void
454DefaultFetch<Impl>::wakeFromQuiesce()
455{
456 DPRINTF(Fetch, "Waking up from quiesce\n");
457 // Hopefully this is safe
458 // @todo: Allow other threads to wake from quiesce.
459 fetchStatus[0] = Running;
460}
461
462template <class Impl>
463inline void
464DefaultFetch<Impl>::switchToActive()
465{
466 if (_status == Inactive) {
467 DPRINTF(Activity, "Activating stage.\n");
468
469 cpu->activateStage(O3CPU::FetchIdx);
470
471 _status = Active;
472 }
473}
474
475template <class Impl>
476inline void
477DefaultFetch<Impl>::switchToInactive()
478{
479 if (_status == Active) {
480 DPRINTF(Activity, "Deactivating stage.\n");
481
482 cpu->deactivateStage(O3CPU::FetchIdx);
483
484 _status = Inactive;
485 }
486}
487
488template <class Impl>
489bool
490DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
491 Addr &next_NPC)
492{
493 // Do branch prediction check here.
494 // A bit of a misnomer...next_PC is actually the current PC until
495 // this function updates it.
496 bool predict_taken;
497
498 if (!inst->isControl()) {
499#if ISA_HAS_DELAY_SLOT
500 Addr cur_PC = next_PC;
501 next_PC = cur_PC + instSize; //next_NPC;
502 next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
503 inst->setPredTarg(next_NPC);
504#else
505 next_PC = next_PC + instSize;
506 inst->setPredTarg(next_PC);
507#endif
508 return false;
509 }
510
511 int tid = inst->threadNumber;
512#if ISA_HAS_DELAY_SLOT
513 Addr pred_PC = next_PC;
514 predict_taken = branchPred.predict(inst, pred_PC, tid);
515
516 if (predict_taken) {
517 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
518 } else {
519 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
520 }
521
522 if (predict_taken) {
523 next_PC = next_NPC;
524 next_NPC = pred_PC;
525
526 // Update delay slot info
527 ++delaySlotInfo[tid].numInsts;
528 delaySlotInfo[tid].targetAddr = pred_PC;
529 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
530 delaySlotInfo[tid].numInsts);
531 } else { // !predict_taken
532 if (inst->isCondDelaySlot()) {
533 next_PC = pred_PC;
534 // The delay slot is skipped here if there is on
535 // prediction
536 } else {
537 next_PC = next_NPC;
538 // No need to declare a delay slot here since
539 // there is no for the pred. target to jump
540 }
541
542 next_NPC = next_NPC + instSize;
543 }
544#else
545 predict_taken = branchPred.predict(inst, next_PC, tid);
546#endif
547
548 ++fetchedBranches;
549
550 if (predict_taken) {
551 ++predictedBranches;
552 }
553
554 return predict_taken;
555}
556
557template <class Impl>
558bool
559DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
560{
561 Fault fault = NoFault;
562
563 //AlphaDep
564 if (cacheBlocked) {
565 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
566 tid);
567 return false;
568 } else if (isSwitchedOut()) {
569 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
570 tid);
571 return false;
572 } else if (interruptPending && !(fetch_PC & 0x3)) {
573 // Hold off fetch from getting new instructions when:
574 // Cache is blocked, or
575 // while an interrupt is pending and we're not in PAL mode, or
576 // fetch is switched out.
577 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
578 tid);
579 return false;
580 }
581
582 // Align the fetch PC so it's at the start of a cache block.
583 Addr block_PC = icacheBlockAlignPC(fetch_PC);
584
585 // If we've already got the block, no need to try to fetch it again.
586 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
587 return true;
588 }
589
590 // Setup the memReq to do a read of the first instruction's address.
591 // Set the appropriate read size and flags as well.
592 // Build request here.
593 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
594 fetch_PC, cpu->readCpuId(), tid);
595
596 memReq[tid] = mem_req;
597
598 // Translate the instruction request.
599 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
600
601 // In the case of faults, the fetch stage may need to stall and wait
602 // for the ITB miss to be handled.
603
604 // If translation was successful, attempt to read the first
605 // instruction.
606 if (fault == NoFault) {
607#if 0
608 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
609 memReq[tid]->isUncacheable()) {
610 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
611 "misspeculating path)!",
612 memReq[tid]->paddr);
613 ret_fault = TheISA::genMachineCheckFault();
614 return false;
615 }
616#endif
617
618 // Build packet here.
619 PacketPtr data_pkt = new Packet(mem_req,
620 Packet::ReadReq, Packet::Broadcast);
621 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
622
623 cacheDataPC[tid] = block_PC;
624 cacheDataValid[tid] = false;
625
626 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
627
628 fetchedCacheLines++;
629
630 // Now do the timing access to see whether or not the instruction
631 // exists within the cache.
632 if (!icachePort->sendTiming(data_pkt)) {
633 if (data_pkt->result == Packet::BadAddress) {
634 fault = TheISA::genMachineCheckFault();
635 delete mem_req;
636 memReq[tid] = NULL;
637 }
638 assert(retryPkt == NULL);
639 assert(retryTid == -1);
640 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
641 fetchStatus[tid] = IcacheWaitRetry;
642 retryPkt = data_pkt;
643 retryTid = tid;
644 cacheBlocked = true;
645 return false;
646 }
647
648 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
649
650 lastIcacheStall[tid] = curTick;
651
652 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
653 "response.\n", tid);
654
655 fetchStatus[tid] = IcacheWaitResponse;
656 } else {
657 delete mem_req;
658 memReq[tid] = NULL;
659 }
660
661 ret_fault = fault;
662 return true;
663}
664
665template <class Impl>
666inline void
667DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
668{
669 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
670 tid, new_PC);
671
672 PC[tid] = new_PC;
673 nextPC[tid] = new_PC + instSize;
674 nextNPC[tid] = new_PC + (2 * instSize);
675
676 // Clear the icache miss if it's outstanding.
677 if (fetchStatus[tid] == IcacheWaitResponse) {
678 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
679 tid);
680 memReq[tid] = NULL;
681 }
682
683 // Get rid of the retrying packet if it was from this thread.
684 if (retryTid == tid) {
685 assert(cacheBlocked);
686 cacheBlocked = false;
687 retryTid = -1;
688 delete retryPkt->req;
689 delete retryPkt;
690 retryPkt = NULL;
691 }
692
693 fetchStatus[tid] = Squashing;
694
695 ++fetchSquashCycles;
696}
697
698template<class Impl>
699void
700DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
701 const InstSeqNum &seq_num,
702 unsigned tid)
703{
704 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
705
706 doSquash(new_PC, tid);
707
708#if ISA_HAS_DELAY_SLOT
709 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
710 delaySlotInfo[tid].numInsts = 0;
711 delaySlotInfo[tid].targetAddr = 0;
712 delaySlotInfo[tid].targetReady = false;
713 }
714#endif
715
716 // Tell the CPU to remove any instructions that are in flight between
717 // fetch and decode.
718 cpu->removeInstsUntil(seq_num, tid);
719}
720
721template<class Impl>
722bool
723DefaultFetch<Impl>::checkStall(unsigned tid) const
724{
725 bool ret_val = false;
726
727 if (cpu->contextSwitch) {
728 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
729 ret_val = true;
730 } else if (stalls[tid].decode) {
731 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
732 ret_val = true;
733 } else if (stalls[tid].rename) {
734 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
735 ret_val = true;
736 } else if (stalls[tid].iew) {
737 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
738 ret_val = true;
739 } else if (stalls[tid].commit) {
740 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
741 ret_val = true;
742 }
743
744 return ret_val;
745}
746
747template<class Impl>
748typename DefaultFetch<Impl>::FetchStatus
749DefaultFetch<Impl>::updateFetchStatus()
750{
751 //Check Running
752 std::list<unsigned>::iterator threads = (*activeThreads).begin();
753
754 while (threads != (*activeThreads).end()) {
755
756 unsigned tid = *threads++;
757
758 if (fetchStatus[tid] == Running ||
759 fetchStatus[tid] == Squashing ||
760 fetchStatus[tid] == IcacheAccessComplete) {
761
762 if (_status == Inactive) {
763 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
764
765 if (fetchStatus[tid] == IcacheAccessComplete) {
766 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
767 "completion\n",tid);
768 }
769
770 cpu->activateStage(O3CPU::FetchIdx);
771 }
772
773 return Active;
774 }
775 }
776
777 // Stage is switching from active to inactive, notify CPU of it.
778 if (_status == Active) {
779 DPRINTF(Activity, "Deactivating stage.\n");
780
781 cpu->deactivateStage(O3CPU::FetchIdx);
782 }
783
784 return Inactive;
785}
786
787template <class Impl>
788void
789DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
790 bool squash_delay_slot, unsigned tid)
791{
792 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
793
794 doSquash(new_PC, tid);
795
796#if ISA_HAS_DELAY_SLOT
797 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
798 delaySlotInfo[tid].numInsts = 0;
799 delaySlotInfo[tid].targetAddr = 0;
800 delaySlotInfo[tid].targetReady = false;
801 }
802
803 // Tell the CPU to remove any instructions that are not in the ROB.
804 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
805#else
806 // Tell the CPU to remove any instructions that are not in the ROB.
807 cpu->removeInstsNotInROB(tid, true, 0);
808#endif
809}
810
811template <class Impl>
812void
813DefaultFetch<Impl>::tick()
814{
815 std::list<unsigned>::iterator threads = (*activeThreads).begin();
816 bool status_change = false;
817
818 wroteToTimeBuffer = false;
819
820 while (threads != (*activeThreads).end()) {
821 unsigned tid = *threads++;
822
823 // Check the signals for each thread to determine the proper status
824 // for each thread.
825 bool updated_status = checkSignalsAndUpdate(tid);
826 status_change = status_change || updated_status;
827 }
828
829 DPRINTF(Fetch, "Running stage.\n");
830
831 // Reset the number of the instruction we're fetching.
832 numInst = 0;
833
834#if FULL_SYSTEM
835 if (fromCommit->commitInfo[0].interruptPending) {
836 interruptPending = true;
837 }
838
839 if (fromCommit->commitInfo[0].clearInterrupt) {
840 interruptPending = false;
841 }
842#endif
843
844 for (threadFetched = 0; threadFetched < numFetchingThreads;
845 threadFetched++) {
846 // Fetch each of the actively fetching threads.
847 fetch(status_change);
848 }
849
850 // Record number of instructions fetched this cycle for distribution.
851 fetchNisnDist.sample(numInst);
852
853 if (status_change) {
854 // Change the fetch stage status if there was a status change.
855 _status = updateFetchStatus();
856 }
857
858 // If there was activity this cycle, inform the CPU of it.
859 if (wroteToTimeBuffer || cpu->contextSwitch) {
860 DPRINTF(Activity, "Activity this cycle.\n");
861
862 cpu->activityThisCycle();
863 }
864}
865
866template <class Impl>
867bool
868DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
869{
870 // Update the per thread stall statuses.
871 if (fromDecode->decodeBlock[tid]) {
872 stalls[tid].decode = true;
873 }
874
875 if (fromDecode->decodeUnblock[tid]) {
876 assert(stalls[tid].decode);
877 assert(!fromDecode->decodeBlock[tid]);
878 stalls[tid].decode = false;
879 }
880
881 if (fromRename->renameBlock[tid]) {
882 stalls[tid].rename = true;
883 }
884
885 if (fromRename->renameUnblock[tid]) {
886 assert(stalls[tid].rename);
887 assert(!fromRename->renameBlock[tid]);
888 stalls[tid].rename = false;
889 }
890
891 if (fromIEW->iewBlock[tid]) {
892 stalls[tid].iew = true;
893 }
894
895 if (fromIEW->iewUnblock[tid]) {
896 assert(stalls[tid].iew);
897 assert(!fromIEW->iewBlock[tid]);
898 stalls[tid].iew = false;
899 }
900
901 if (fromCommit->commitBlock[tid]) {
902 stalls[tid].commit = true;
903 }
904
905 if (fromCommit->commitUnblock[tid]) {
906 assert(stalls[tid].commit);
907 assert(!fromCommit->commitBlock[tid]);
908 stalls[tid].commit = false;
909 }
910
911 // Check squash signals from commit.
912 if (fromCommit->commitInfo[tid].squash) {
913
914 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
915 "from commit.\n",tid);
916
917#if ISA_HAS_DELAY_SLOT
918 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
919#else
920 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
921#endif
922 // In any case, squash.
923 squash(fromCommit->commitInfo[tid].nextPC,
924 doneSeqNum,
925 fromCommit->commitInfo[tid].squashDelaySlot,
926 tid);
927
928 // Also check if there's a mispredict that happened.
929 if (fromCommit->commitInfo[tid].branchMispredict) {
930 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
931 fromCommit->commitInfo[tid].nextPC,
932 fromCommit->commitInfo[tid].branchTaken,
933 tid);
934 } else {
935 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
936 tid);
937 }
938
939 return true;
940 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
941 // Update the branch predictor if it wasn't a squashed instruction
942 // that was broadcasted.
943 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
944 }
945
946 // Check ROB squash signals from commit.
947 if (fromCommit->commitInfo[tid].robSquashing) {
948 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
949
950 // Continue to squash.
951 fetchStatus[tid] = Squashing;
952
953 return true;
954 }
955
956 // Check squash signals from decode.
957 if (fromDecode->decodeInfo[tid].squash) {
958 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
959 "from decode.\n",tid);
960
961 // Update the branch predictor.
962 if (fromDecode->decodeInfo[tid].branchMispredict) {
963 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
964 fromDecode->decodeInfo[tid].nextPC,
965 fromDecode->decodeInfo[tid].branchTaken,
966 tid);
967 } else {
968 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
969 tid);
970 }
971
972 if (fetchStatus[tid] != Squashing) {
973
974#if ISA_HAS_DELAY_SLOT
975 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
976#else
977 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
978#endif
979 // Squash unless we're already squashing
980 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
981 doneSeqNum,
982 tid);
983
984 return true;
985 }
986 }
987
988 if (checkStall(tid) &&
989 fetchStatus[tid] != IcacheWaitResponse &&
990 fetchStatus[tid] != IcacheWaitRetry) {
991 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
992
993 fetchStatus[tid] = Blocked;
994
995 return true;
996 }
997
998 if (fetchStatus[tid] == Blocked ||
999 fetchStatus[tid] == Squashing) {
1000 // Switch status to running if fetch isn't being told to block or
1001 // squash this cycle.
1002 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1003 tid);
1004
1005 fetchStatus[tid] = Running;
1006
1007 return true;
1008 }
1009
1010 // If we've reached this point, we have not gotten any signals that
1011 // cause fetch to change its status. Fetch remains the same as before.
1012 return false;
1013}
1014
1015template<class Impl>
1016void
1017DefaultFetch<Impl>::fetch(bool &status_change)
1018{
1019 //////////////////////////////////////////
1020 // Start actual fetch
1021 //////////////////////////////////////////
1022 int tid = getFetchingThread(fetchPolicy);
1023
1024 if (tid == -1 || drainPending) {
1025 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1026
1027 // Breaks looping condition in tick()
1028 threadFetched = numFetchingThreads;
1029 return;
1030 }
1031
1032 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1033
1034 // The current PC.
1035 Addr &fetch_PC = PC[tid];
1036
1037 // Fault code for memory access.
1038 Fault fault = NoFault;
1039
1040 // If returning from the delay of a cache miss, then update the status
1041 // to running, otherwise do the cache access. Possibly move this up
1042 // to tick() function.
1043 if (fetchStatus[tid] == IcacheAccessComplete) {
1044 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1045 tid);
1046
1047 fetchStatus[tid] = Running;
1048 status_change = true;
1049 } else if (fetchStatus[tid] == Running) {
1050 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1051 "instruction, starting at PC %08p.\n",
1052 tid, fetch_PC);
1053
1054 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1055 if (!fetch_success) {
1056 if (cacheBlocked) {
1057 ++icacheStallCycles;
1058 } else {
1059 ++fetchMiscStallCycles;
1060 }
1061 return;
1062 }
1063 } else {
1064 if (fetchStatus[tid] == Idle) {
1065 ++fetchIdleCycles;
1066 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1067 } else if (fetchStatus[tid] == Blocked) {
1068 ++fetchBlockedCycles;
1069 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1070 } else if (fetchStatus[tid] == Squashing) {
1071 ++fetchSquashCycles;
1072 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1073 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1074 ++icacheStallCycles;
1075 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1076 }
1077
1078 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1079 // fetch should do nothing.
1080 return;
1081 }
1082
1083 ++fetchCycles;
1084
1085 // If we had a stall due to an icache miss, then return.
1086 if (fetchStatus[tid] == IcacheWaitResponse) {
1087 ++icacheStallCycles;
1088 status_change = true;
1089 return;
1090 }
1091
1092 Addr next_PC = fetch_PC;
1093 Addr next_NPC = next_PC + instSize;
1094 InstSeqNum inst_seq;
1095 MachInst inst;
1096 ExtMachInst ext_inst;
1097 // @todo: Fix this hack.
1098 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1099
1100 if (fault == NoFault) {
1101 // If the read of the first instruction was successful, then grab the
1102 // instructions from the rest of the cache line and put them into the
1103 // queue heading to decode.
1104
1105 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1106 "decode.\n",tid);
1107
1108 // Need to keep track of whether or not a predicted branch
1109 // ended this fetch block.
1110 bool predicted_branch = false;
1111
1112 // Need to keep track of whether or not a delay slot
1113 // instruction has been fetched
1114
1115 for (;
1116 offset < cacheBlkSize &&
1117 numInst < fetchWidth &&
1118 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1119 ++numInst) {
1120
1121 // Get a sequence number.
1122 inst_seq = cpu->getAndIncrementInstSeq();
1123
1124 // Make sure this is a valid index.
1125 assert(offset <= cacheBlkSize - instSize);
1126
1127 // Get the instruction from the array of the cache line.
1128 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1129 (&cacheData[tid][offset]));
1130
1131#if THE_ISA == ALPHA_ISA
1132 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1133#elif THE_ISA == SPARC_ISA
1134 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1135#endif
1136
1137 // Create a new DynInst from the instruction fetched.
1138 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1139 next_PC,
1140 inst_seq, cpu);
1141 instruction->setTid(tid);
1142
1143 instruction->setASID(tid);
1144
1145 instruction->setThreadState(cpu->thread[tid]);
1146
1147 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1148 "[sn:%lli]\n",
1149 tid, instruction->readPC(), inst_seq);
1150
1151 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1152 tid, instruction->staticInst->disassemble(fetch_PC));
1153
1154 instruction->traceData =
1155 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1156 instruction->staticInst,
1157 instruction->readPC());
1158
1159 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1160 next_NPC);
1161
1162 // Add instruction to the CPU's list of instructions.
1163 instruction->setInstListIt(cpu->addInst(instruction));
1164
1165 // Write the instruction to the first slot in the queue
1166 // that heads to decode.
1167 toDecode->insts[numInst] = instruction;
1168
1169 toDecode->size++;
1170
1171 // Increment stat of fetched instructions.
1172 ++fetchedInsts;
1173
1174 // Move to the next instruction, unless we have a branch.
1175 fetch_PC = next_PC;
1176
1177 if (instruction->isQuiesce()) {
1178 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1179 curTick);
1180 fetchStatus[tid] = QuiescePending;
1181 ++numInst;
1182 status_change = true;
1183 break;
1184 }
1185
1186 offset += instSize;
1187
1188#if ISA_HAS_DELAY_SLOT
1189 if (predicted_branch) {
1190 delaySlotInfo[tid].branchSeqNum = inst_seq;
1191
1192 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1193 tid, inst_seq);
1194 continue;
1195 } else if (delaySlotInfo[tid].numInsts > 0) {
1196 --delaySlotInfo[tid].numInsts;
1197
1198 // It's OK to set PC to target of branch
1199 if (delaySlotInfo[tid].numInsts == 0) {
1200 delaySlotInfo[tid].targetReady = true;
1201
1202 // Break the looping condition
1203 predicted_branch = true;
1204 }
1205
1206 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1207 " process.\n", tid, delaySlotInfo[tid].numInsts);
1208 }
1209#endif
1210 }
1211
1212 if (offset >= cacheBlkSize) {
1213 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1214 "block.\n", tid);
1215 } else if (numInst >= fetchWidth) {
1216 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1217 "for this cycle.\n", tid);
1218 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1219 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1220 "instruction encountered.\n", tid);
1221 }
1222 }
1223
1224 if (numInst > 0) {
1225 wroteToTimeBuffer = true;
1226 }
1227
1228 // Now that fetching is completed, update the PC to signify what the next
1229 // cycle will be.
1230 if (fault == NoFault) {
1231#if ISA_HAS_DELAY_SLOT
1232 if (delaySlotInfo[tid].targetReady &&
1233 delaySlotInfo[tid].numInsts == 0) {
1234 // Set PC to target
1235 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1236 nextPC[tid] = next_PC + instSize; //next_NPC
1237 nextNPC[tid] = next_PC + (2 * instSize);
1238
1239 delaySlotInfo[tid].targetReady = false;
1240 } else {
1241 PC[tid] = next_PC;
1242 nextPC[tid] = next_NPC;
1243 nextNPC[tid] = next_NPC + instSize;
1244 }
1245
1246 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1247#else
1248 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1249 PC[tid] = next_PC;
1250 nextPC[tid] = next_PC + instSize;
1251#endif
1252 } else {
1253 // We shouldn't be in an icache miss and also have a fault (an ITB
1254 // miss)
1255 if (fetchStatus[tid] == IcacheWaitResponse) {
1256 panic("Fetch should have exited prior to this!");
1257 }
1258
1259 // Send the fault to commit. This thread will not do anything
1260 // until commit handles the fault. The only other way it can
1261 // wake up is if a squash comes along and changes the PC.
1262#if FULL_SYSTEM
1263 assert(numInst != fetchWidth);
1264 // Get a sequence number.
1265 inst_seq = cpu->getAndIncrementInstSeq();
1266 // We will use a nop in order to carry the fault.
1267 ext_inst = TheISA::NoopMachInst;
1268
1269 // Create a new DynInst from the dummy nop.
1270 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1271 next_PC,
1272 inst_seq, cpu);
1273 instruction->setPredTarg(next_PC + instSize);
1274 instruction->setTid(tid);
1275
1276 instruction->setASID(tid);
1277
1278 instruction->setThreadState(cpu->thread[tid]);
1279
1280 instruction->traceData = NULL;
1281
1282 instruction->setInstListIt(cpu->addInst(instruction));
1283
1284 instruction->fault = fault;
1285
1286 toDecode->insts[numInst] = instruction;
1287 toDecode->size++;
1288
1289 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1290
1291 fetchStatus[tid] = TrapPending;
1292 status_change = true;
1293#else // !FULL_SYSTEM
1294 fetchStatus[tid] = TrapPending;
1295 status_change = true;
1296
1297#endif // FULL_SYSTEM
1298 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1299 tid, fault->name(), PC[tid]);
1300 }
1301}
1302
1303template<class Impl>
1304void
1305DefaultFetch<Impl>::recvRetry()
1306{
1307 if (retryPkt != NULL) {
1308 assert(cacheBlocked);
1309 assert(retryTid != -1);
1310 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1311
1312 if (icachePort->sendTiming(retryPkt)) {
1313 fetchStatus[retryTid] = IcacheWaitResponse;
1314 retryPkt = NULL;
1315 retryTid = -1;
1316 cacheBlocked = false;
1317 }
1318 } else {
1319 assert(retryTid == -1);
1320 // Access has been squashed since it was sent out. Just clear
1321 // the cache being blocked.
1322 cacheBlocked = false;
1323 }
1324}
1325
1326///////////////////////////////////////
1327// //
1328// SMT FETCH POLICY MAINTAINED HERE //
1329// //
1330///////////////////////////////////////
1331template<class Impl>
1332int
1333DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1334{
1335 if (numThreads > 1) {
1336 switch (fetch_priority) {
1337
1338 case SingleThread:
1339 return 0;
1340
1341 case RoundRobin:
1342 return roundRobin();
1343
1344 case IQ:
1345 return iqCount();
1346
1347 case LSQ:
1348 return lsqCount();
1349
1350 case Branch:
1351 return branchCount();
1352
1353 default:
1354 return -1;
1355 }
1356 } else {
1357 int tid = *((*activeThreads).begin());
1358
1359 if (fetchStatus[tid] == Running ||
1360 fetchStatus[tid] == IcacheAccessComplete ||
1361 fetchStatus[tid] == Idle) {
1362 return tid;
1363 } else {
1364 return -1;
1365 }
1366 }
1367
1368}
1369
1370
1371template<class Impl>
1372int
1373DefaultFetch<Impl>::roundRobin()
1374{
1375 std::list<unsigned>::iterator pri_iter = priorityList.begin();
1376 std::list<unsigned>::iterator end = priorityList.end();
1377
1378 int high_pri;
1379
1380 while (pri_iter != end) {
1381 high_pri = *pri_iter;
1382
1383 assert(high_pri <= numThreads);
1384
1385 if (fetchStatus[high_pri] == Running ||
1386 fetchStatus[high_pri] == IcacheAccessComplete ||
1387 fetchStatus[high_pri] == Idle) {
1388
1389 priorityList.erase(pri_iter);
1390 priorityList.push_back(high_pri);
1391
1392 return high_pri;
1393 }
1394
1395 pri_iter++;
1396 }
1397
1398 return -1;
1399}
1400
1401template<class Impl>
1402int
1403DefaultFetch<Impl>::iqCount()
1404{
1405 std::priority_queue<unsigned> PQ;
1406
1407 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1408
1409 while (threads != (*activeThreads).end()) {
1410 unsigned tid = *threads++;
1411
1412 PQ.push(fromIEW->iewInfo[tid].iqCount);
1413 }
1414
1415 while (!PQ.empty()) {
1416
1417 unsigned high_pri = PQ.top();
1418
1419 if (fetchStatus[high_pri] == Running ||
1420 fetchStatus[high_pri] == IcacheAccessComplete ||
1421 fetchStatus[high_pri] == Idle)
1422 return high_pri;
1423 else
1424 PQ.pop();
1425
1426 }
1427
1428 return -1;
1429}
1430
1431template<class Impl>
1432int
1433DefaultFetch<Impl>::lsqCount()
1434{
1435 std::priority_queue<unsigned> PQ;
1436
1437
1438 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1439
1440 while (threads != (*activeThreads).end()) {
1441 unsigned tid = *threads++;
1442
1443 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1444 }
1445
1446 while (!PQ.empty()) {
1447
1448 unsigned high_pri = PQ.top();
1449
1450 if (fetchStatus[high_pri] == Running ||
1451 fetchStatus[high_pri] == IcacheAccessComplete ||
1452 fetchStatus[high_pri] == Idle)
1453 return high_pri;
1454 else
1455 PQ.pop();
1456
1457 }
1458
1459 return -1;
1460}
1461
1462template<class Impl>
1463int
1464DefaultFetch<Impl>::branchCount()
1465{
1466 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1467 panic("Branch Count Fetch policy unimplemented\n");
1468 return *threads;
1469}
| 297#if USE_CHECKER
298 if (cpu->checker) {
299 cpu->checker->setIcachePort(icachePort);
300 }
301#endif
302
303 // Schedule fetch to get the correct PC from the CPU
304 // scheduleFetchStartupEvent(1);
305
306 // Fetch needs to start fetching instructions at the very beginning,
307 // so it must start up in active state.
308 switchToActive();
309}
310
311template<class Impl>
312void
313DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
314{
315 DPRINTF(Fetch, "Setting the time buffer pointer.\n");
316 timeBuffer = time_buffer;
317
318 // Create wires to get information from proper places in time buffer.
319 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
320 fromRename = timeBuffer->getWire(-renameToFetchDelay);
321 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
322 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
323}
324
325template<class Impl>
326void
327DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
328{
329 DPRINTF(Fetch, "Setting active threads list pointer.\n");
330 activeThreads = at_ptr;
331}
332
333template<class Impl>
334void
335DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
336{
337 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
338 fetchQueue = fq_ptr;
339
340 // Create wire to write information to proper place in fetch queue.
341 toDecode = fetchQueue->getWire(0);
342}
343
344template<class Impl>
345void
346DefaultFetch<Impl>::initStage()
347{
348 // Setup PC and nextPC with initial state.
349 for (int tid = 0; tid < numThreads; tid++) {
350 PC[tid] = cpu->readPC(tid);
351 nextPC[tid] = cpu->readNextPC(tid);
352#if ISA_HAS_DELAY_SLOT
353 nextNPC[tid] = cpu->readNextNPC(tid);
354#endif
355 }
356}
357
358template<class Impl>
359void
360DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
361{
362 unsigned tid = pkt->req->getThreadNum();
363
364 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
365
366 // Only change the status if it's still waiting on the icache access
367 // to return.
368 if (fetchStatus[tid] != IcacheWaitResponse ||
369 pkt->req != memReq[tid] ||
370 isSwitchedOut()) {
371 ++fetchIcacheSquashes;
372 delete pkt->req;
373 delete pkt;
374 return;
375 }
376
377 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
378 cacheDataValid[tid] = true;
379
380 if (!drainPending) {
381 // Wake up the CPU (if it went to sleep and was waiting on
382 // this completion event).
383 cpu->wakeCPU();
384
385 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
386 tid);
387
388 switchToActive();
389 }
390
391 // Only switch to IcacheAccessComplete if we're not stalled as well.
392 if (checkStall(tid)) {
393 fetchStatus[tid] = Blocked;
394 } else {
395 fetchStatus[tid] = IcacheAccessComplete;
396 }
397
398 // Reset the mem req to NULL.
399 delete pkt->req;
400 delete pkt;
401 memReq[tid] = NULL;
402}
403
404template <class Impl>
405bool
406DefaultFetch<Impl>::drain()
407{
408 // Fetch is ready to drain at any time.
409 cpu->signalDrained();
410 drainPending = true;
411 return true;
412}
413
414template <class Impl>
415void
416DefaultFetch<Impl>::resume()
417{
418 drainPending = false;
419}
420
421template <class Impl>
422void
423DefaultFetch<Impl>::switchOut()
424{
425 switchedOut = true;
426 // Branch predictor needs to have its state cleared.
427 branchPred.switchOut();
428}
429
430template <class Impl>
431void
432DefaultFetch<Impl>::takeOverFrom()
433{
434 // Reset all state
435 for (int i = 0; i < Impl::MaxThreads; ++i) {
436 stalls[i].decode = 0;
437 stalls[i].rename = 0;
438 stalls[i].iew = 0;
439 stalls[i].commit = 0;
440 PC[i] = cpu->readPC(i);
441 nextPC[i] = cpu->readNextPC(i);
442#if ISA_HAS_DELAY_SLOT
443 nextNPC[i] = cpu->readNextNPC(i);
444 delaySlotInfo[i].branchSeqNum = -1;
445 delaySlotInfo[i].numInsts = 0;
446 delaySlotInfo[i].targetAddr = 0;
447 delaySlotInfo[i].targetReady = false;
448#endif
449 fetchStatus[i] = Running;
450 }
451 numInst = 0;
452 wroteToTimeBuffer = false;
453 _status = Inactive;
454 switchedOut = false;
455 interruptPending = false;
456 branchPred.takeOverFrom();
457}
458
459template <class Impl>
460void
461DefaultFetch<Impl>::wakeFromQuiesce()
462{
463 DPRINTF(Fetch, "Waking up from quiesce\n");
464 // Hopefully this is safe
465 // @todo: Allow other threads to wake from quiesce.
466 fetchStatus[0] = Running;
467}
468
469template <class Impl>
470inline void
471DefaultFetch<Impl>::switchToActive()
472{
473 if (_status == Inactive) {
474 DPRINTF(Activity, "Activating stage.\n");
475
476 cpu->activateStage(O3CPU::FetchIdx);
477
478 _status = Active;
479 }
480}
481
482template <class Impl>
483inline void
484DefaultFetch<Impl>::switchToInactive()
485{
486 if (_status == Active) {
487 DPRINTF(Activity, "Deactivating stage.\n");
488
489 cpu->deactivateStage(O3CPU::FetchIdx);
490
491 _status = Inactive;
492 }
493}
494
495template <class Impl>
496bool
497DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
498 Addr &next_NPC)
499{
500 // Do branch prediction check here.
501 // A bit of a misnomer...next_PC is actually the current PC until
502 // this function updates it.
503 bool predict_taken;
504
505 if (!inst->isControl()) {
506#if ISA_HAS_DELAY_SLOT
507 Addr cur_PC = next_PC;
508 next_PC = cur_PC + instSize; //next_NPC;
509 next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
510 inst->setPredTarg(next_NPC);
511#else
512 next_PC = next_PC + instSize;
513 inst->setPredTarg(next_PC);
514#endif
515 return false;
516 }
517
518 int tid = inst->threadNumber;
519#if ISA_HAS_DELAY_SLOT
520 Addr pred_PC = next_PC;
521 predict_taken = branchPred.predict(inst, pred_PC, tid);
522
523 if (predict_taken) {
524 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
525 } else {
526 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
527 }
528
529 if (predict_taken) {
530 next_PC = next_NPC;
531 next_NPC = pred_PC;
532
533 // Update delay slot info
534 ++delaySlotInfo[tid].numInsts;
535 delaySlotInfo[tid].targetAddr = pred_PC;
536 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
537 delaySlotInfo[tid].numInsts);
538 } else { // !predict_taken
539 if (inst->isCondDelaySlot()) {
540 next_PC = pred_PC;
541 // The delay slot is skipped here if there is on
542 // prediction
543 } else {
544 next_PC = next_NPC;
545 // No need to declare a delay slot here since
546 // there is no for the pred. target to jump
547 }
548
549 next_NPC = next_NPC + instSize;
550 }
551#else
552 predict_taken = branchPred.predict(inst, next_PC, tid);
553#endif
554
555 ++fetchedBranches;
556
557 if (predict_taken) {
558 ++predictedBranches;
559 }
560
561 return predict_taken;
562}
563
564template <class Impl>
565bool
566DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
567{
568 Fault fault = NoFault;
569
570 //AlphaDep
571 if (cacheBlocked) {
572 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
573 tid);
574 return false;
575 } else if (isSwitchedOut()) {
576 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
577 tid);
578 return false;
579 } else if (interruptPending && !(fetch_PC & 0x3)) {
580 // Hold off fetch from getting new instructions when:
581 // Cache is blocked, or
582 // while an interrupt is pending and we're not in PAL mode, or
583 // fetch is switched out.
584 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
585 tid);
586 return false;
587 }
588
589 // Align the fetch PC so it's at the start of a cache block.
590 Addr block_PC = icacheBlockAlignPC(fetch_PC);
591
592 // If we've already got the block, no need to try to fetch it again.
593 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
594 return true;
595 }
596
597 // Setup the memReq to do a read of the first instruction's address.
598 // Set the appropriate read size and flags as well.
599 // Build request here.
600 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
601 fetch_PC, cpu->readCpuId(), tid);
602
603 memReq[tid] = mem_req;
604
605 // Translate the instruction request.
606 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
607
608 // In the case of faults, the fetch stage may need to stall and wait
609 // for the ITB miss to be handled.
610
611 // If translation was successful, attempt to read the first
612 // instruction.
613 if (fault == NoFault) {
614#if 0
615 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
616 memReq[tid]->isUncacheable()) {
617 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
618 "misspeculating path)!",
619 memReq[tid]->paddr);
620 ret_fault = TheISA::genMachineCheckFault();
621 return false;
622 }
623#endif
624
625 // Build packet here.
626 PacketPtr data_pkt = new Packet(mem_req,
627 Packet::ReadReq, Packet::Broadcast);
628 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
629
630 cacheDataPC[tid] = block_PC;
631 cacheDataValid[tid] = false;
632
633 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
634
635 fetchedCacheLines++;
636
637 // Now do the timing access to see whether or not the instruction
638 // exists within the cache.
639 if (!icachePort->sendTiming(data_pkt)) {
640 if (data_pkt->result == Packet::BadAddress) {
641 fault = TheISA::genMachineCheckFault();
642 delete mem_req;
643 memReq[tid] = NULL;
644 }
645 assert(retryPkt == NULL);
646 assert(retryTid == -1);
647 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
648 fetchStatus[tid] = IcacheWaitRetry;
649 retryPkt = data_pkt;
650 retryTid = tid;
651 cacheBlocked = true;
652 return false;
653 }
654
655 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
656
657 lastIcacheStall[tid] = curTick;
658
659 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
660 "response.\n", tid);
661
662 fetchStatus[tid] = IcacheWaitResponse;
663 } else {
664 delete mem_req;
665 memReq[tid] = NULL;
666 }
667
668 ret_fault = fault;
669 return true;
670}
671
672template <class Impl>
673inline void
674DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
675{
676 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
677 tid, new_PC);
678
679 PC[tid] = new_PC;
680 nextPC[tid] = new_PC + instSize;
681 nextNPC[tid] = new_PC + (2 * instSize);
682
683 // Clear the icache miss if it's outstanding.
684 if (fetchStatus[tid] == IcacheWaitResponse) {
685 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
686 tid);
687 memReq[tid] = NULL;
688 }
689
690 // Get rid of the retrying packet if it was from this thread.
691 if (retryTid == tid) {
692 assert(cacheBlocked);
693 cacheBlocked = false;
694 retryTid = -1;
695 delete retryPkt->req;
696 delete retryPkt;
697 retryPkt = NULL;
698 }
699
700 fetchStatus[tid] = Squashing;
701
702 ++fetchSquashCycles;
703}
704
705template<class Impl>
706void
707DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
708 const InstSeqNum &seq_num,
709 unsigned tid)
710{
711 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
712
713 doSquash(new_PC, tid);
714
715#if ISA_HAS_DELAY_SLOT
716 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
717 delaySlotInfo[tid].numInsts = 0;
718 delaySlotInfo[tid].targetAddr = 0;
719 delaySlotInfo[tid].targetReady = false;
720 }
721#endif
722
723 // Tell the CPU to remove any instructions that are in flight between
724 // fetch and decode.
725 cpu->removeInstsUntil(seq_num, tid);
726}
727
728template<class Impl>
729bool
730DefaultFetch<Impl>::checkStall(unsigned tid) const
731{
732 bool ret_val = false;
733
734 if (cpu->contextSwitch) {
735 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
736 ret_val = true;
737 } else if (stalls[tid].decode) {
738 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
739 ret_val = true;
740 } else if (stalls[tid].rename) {
741 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
742 ret_val = true;
743 } else if (stalls[tid].iew) {
744 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
745 ret_val = true;
746 } else if (stalls[tid].commit) {
747 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
748 ret_val = true;
749 }
750
751 return ret_val;
752}
753
754template<class Impl>
755typename DefaultFetch<Impl>::FetchStatus
756DefaultFetch<Impl>::updateFetchStatus()
757{
758 //Check Running
759 std::list<unsigned>::iterator threads = (*activeThreads).begin();
760
761 while (threads != (*activeThreads).end()) {
762
763 unsigned tid = *threads++;
764
765 if (fetchStatus[tid] == Running ||
766 fetchStatus[tid] == Squashing ||
767 fetchStatus[tid] == IcacheAccessComplete) {
768
769 if (_status == Inactive) {
770 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
771
772 if (fetchStatus[tid] == IcacheAccessComplete) {
773 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
774 "completion\n",tid);
775 }
776
777 cpu->activateStage(O3CPU::FetchIdx);
778 }
779
780 return Active;
781 }
782 }
783
784 // Stage is switching from active to inactive, notify CPU of it.
785 if (_status == Active) {
786 DPRINTF(Activity, "Deactivating stage.\n");
787
788 cpu->deactivateStage(O3CPU::FetchIdx);
789 }
790
791 return Inactive;
792}
793
794template <class Impl>
795void
796DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
797 bool squash_delay_slot, unsigned tid)
798{
799 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
800
801 doSquash(new_PC, tid);
802
803#if ISA_HAS_DELAY_SLOT
804 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
805 delaySlotInfo[tid].numInsts = 0;
806 delaySlotInfo[tid].targetAddr = 0;
807 delaySlotInfo[tid].targetReady = false;
808 }
809
810 // Tell the CPU to remove any instructions that are not in the ROB.
811 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
812#else
813 // Tell the CPU to remove any instructions that are not in the ROB.
814 cpu->removeInstsNotInROB(tid, true, 0);
815#endif
816}
817
818template <class Impl>
819void
820DefaultFetch<Impl>::tick()
821{
822 std::list<unsigned>::iterator threads = (*activeThreads).begin();
823 bool status_change = false;
824
825 wroteToTimeBuffer = false;
826
827 while (threads != (*activeThreads).end()) {
828 unsigned tid = *threads++;
829
830 // Check the signals for each thread to determine the proper status
831 // for each thread.
832 bool updated_status = checkSignalsAndUpdate(tid);
833 status_change = status_change || updated_status;
834 }
835
836 DPRINTF(Fetch, "Running stage.\n");
837
838 // Reset the number of the instruction we're fetching.
839 numInst = 0;
840
841#if FULL_SYSTEM
842 if (fromCommit->commitInfo[0].interruptPending) {
843 interruptPending = true;
844 }
845
846 if (fromCommit->commitInfo[0].clearInterrupt) {
847 interruptPending = false;
848 }
849#endif
850
851 for (threadFetched = 0; threadFetched < numFetchingThreads;
852 threadFetched++) {
853 // Fetch each of the actively fetching threads.
854 fetch(status_change);
855 }
856
857 // Record number of instructions fetched this cycle for distribution.
858 fetchNisnDist.sample(numInst);
859
860 if (status_change) {
861 // Change the fetch stage status if there was a status change.
862 _status = updateFetchStatus();
863 }
864
865 // If there was activity this cycle, inform the CPU of it.
866 if (wroteToTimeBuffer || cpu->contextSwitch) {
867 DPRINTF(Activity, "Activity this cycle.\n");
868
869 cpu->activityThisCycle();
870 }
871}
872
873template <class Impl>
874bool
875DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
876{
877 // Update the per thread stall statuses.
878 if (fromDecode->decodeBlock[tid]) {
879 stalls[tid].decode = true;
880 }
881
882 if (fromDecode->decodeUnblock[tid]) {
883 assert(stalls[tid].decode);
884 assert(!fromDecode->decodeBlock[tid]);
885 stalls[tid].decode = false;
886 }
887
888 if (fromRename->renameBlock[tid]) {
889 stalls[tid].rename = true;
890 }
891
892 if (fromRename->renameUnblock[tid]) {
893 assert(stalls[tid].rename);
894 assert(!fromRename->renameBlock[tid]);
895 stalls[tid].rename = false;
896 }
897
898 if (fromIEW->iewBlock[tid]) {
899 stalls[tid].iew = true;
900 }
901
902 if (fromIEW->iewUnblock[tid]) {
903 assert(stalls[tid].iew);
904 assert(!fromIEW->iewBlock[tid]);
905 stalls[tid].iew = false;
906 }
907
908 if (fromCommit->commitBlock[tid]) {
909 stalls[tid].commit = true;
910 }
911
912 if (fromCommit->commitUnblock[tid]) {
913 assert(stalls[tid].commit);
914 assert(!fromCommit->commitBlock[tid]);
915 stalls[tid].commit = false;
916 }
917
918 // Check squash signals from commit.
919 if (fromCommit->commitInfo[tid].squash) {
920
921 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
922 "from commit.\n",tid);
923
924#if ISA_HAS_DELAY_SLOT
925 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
926#else
927 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
928#endif
929 // In any case, squash.
930 squash(fromCommit->commitInfo[tid].nextPC,
931 doneSeqNum,
932 fromCommit->commitInfo[tid].squashDelaySlot,
933 tid);
934
935 // Also check if there's a mispredict that happened.
936 if (fromCommit->commitInfo[tid].branchMispredict) {
937 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
938 fromCommit->commitInfo[tid].nextPC,
939 fromCommit->commitInfo[tid].branchTaken,
940 tid);
941 } else {
942 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
943 tid);
944 }
945
946 return true;
947 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
948 // Update the branch predictor if it wasn't a squashed instruction
949 // that was broadcasted.
950 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
951 }
952
953 // Check ROB squash signals from commit.
954 if (fromCommit->commitInfo[tid].robSquashing) {
955 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
956
957 // Continue to squash.
958 fetchStatus[tid] = Squashing;
959
960 return true;
961 }
962
963 // Check squash signals from decode.
964 if (fromDecode->decodeInfo[tid].squash) {
965 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
966 "from decode.\n",tid);
967
968 // Update the branch predictor.
969 if (fromDecode->decodeInfo[tid].branchMispredict) {
970 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
971 fromDecode->decodeInfo[tid].nextPC,
972 fromDecode->decodeInfo[tid].branchTaken,
973 tid);
974 } else {
975 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
976 tid);
977 }
978
979 if (fetchStatus[tid] != Squashing) {
980
981#if ISA_HAS_DELAY_SLOT
982 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
983#else
984 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
985#endif
986 // Squash unless we're already squashing
987 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
988 doneSeqNum,
989 tid);
990
991 return true;
992 }
993 }
994
995 if (checkStall(tid) &&
996 fetchStatus[tid] != IcacheWaitResponse &&
997 fetchStatus[tid] != IcacheWaitRetry) {
998 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
999
1000 fetchStatus[tid] = Blocked;
1001
1002 return true;
1003 }
1004
1005 if (fetchStatus[tid] == Blocked ||
1006 fetchStatus[tid] == Squashing) {
1007 // Switch status to running if fetch isn't being told to block or
1008 // squash this cycle.
1009 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1010 tid);
1011
1012 fetchStatus[tid] = Running;
1013
1014 return true;
1015 }
1016
1017 // If we've reached this point, we have not gotten any signals that
1018 // cause fetch to change its status. Fetch remains the same as before.
1019 return false;
1020}
1021
1022template<class Impl>
1023void
1024DefaultFetch<Impl>::fetch(bool &status_change)
1025{
1026 //////////////////////////////////////////
1027 // Start actual fetch
1028 //////////////////////////////////////////
1029 int tid = getFetchingThread(fetchPolicy);
1030
1031 if (tid == -1 || drainPending) {
1032 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1033
1034 // Breaks looping condition in tick()
1035 threadFetched = numFetchingThreads;
1036 return;
1037 }
1038
1039 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1040
1041 // The current PC.
1042 Addr &fetch_PC = PC[tid];
1043
1044 // Fault code for memory access.
1045 Fault fault = NoFault;
1046
1047 // If returning from the delay of a cache miss, then update the status
1048 // to running, otherwise do the cache access. Possibly move this up
1049 // to tick() function.
1050 if (fetchStatus[tid] == IcacheAccessComplete) {
1051 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1052 tid);
1053
1054 fetchStatus[tid] = Running;
1055 status_change = true;
1056 } else if (fetchStatus[tid] == Running) {
1057 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1058 "instruction, starting at PC %08p.\n",
1059 tid, fetch_PC);
1060
1061 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1062 if (!fetch_success) {
1063 if (cacheBlocked) {
1064 ++icacheStallCycles;
1065 } else {
1066 ++fetchMiscStallCycles;
1067 }
1068 return;
1069 }
1070 } else {
1071 if (fetchStatus[tid] == Idle) {
1072 ++fetchIdleCycles;
1073 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1074 } else if (fetchStatus[tid] == Blocked) {
1075 ++fetchBlockedCycles;
1076 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1077 } else if (fetchStatus[tid] == Squashing) {
1078 ++fetchSquashCycles;
1079 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1080 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1081 ++icacheStallCycles;
1082 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1083 }
1084
1085 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1086 // fetch should do nothing.
1087 return;
1088 }
1089
1090 ++fetchCycles;
1091
1092 // If we had a stall due to an icache miss, then return.
1093 if (fetchStatus[tid] == IcacheWaitResponse) {
1094 ++icacheStallCycles;
1095 status_change = true;
1096 return;
1097 }
1098
1099 Addr next_PC = fetch_PC;
1100 Addr next_NPC = next_PC + instSize;
1101 InstSeqNum inst_seq;
1102 MachInst inst;
1103 ExtMachInst ext_inst;
1104 // @todo: Fix this hack.
1105 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1106
1107 if (fault == NoFault) {
1108 // If the read of the first instruction was successful, then grab the
1109 // instructions from the rest of the cache line and put them into the
1110 // queue heading to decode.
1111
1112 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1113 "decode.\n",tid);
1114
1115 // Need to keep track of whether or not a predicted branch
1116 // ended this fetch block.
1117 bool predicted_branch = false;
1118
1119 // Need to keep track of whether or not a delay slot
1120 // instruction has been fetched
1121
1122 for (;
1123 offset < cacheBlkSize &&
1124 numInst < fetchWidth &&
1125 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1126 ++numInst) {
1127
1128 // Get a sequence number.
1129 inst_seq = cpu->getAndIncrementInstSeq();
1130
1131 // Make sure this is a valid index.
1132 assert(offset <= cacheBlkSize - instSize);
1133
1134 // Get the instruction from the array of the cache line.
1135 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1136 (&cacheData[tid][offset]));
1137
1138#if THE_ISA == ALPHA_ISA
1139 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1140#elif THE_ISA == SPARC_ISA
1141 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1142#endif
1143
1144 // Create a new DynInst from the instruction fetched.
1145 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1146 next_PC,
1147 inst_seq, cpu);
1148 instruction->setTid(tid);
1149
1150 instruction->setASID(tid);
1151
1152 instruction->setThreadState(cpu->thread[tid]);
1153
1154 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1155 "[sn:%lli]\n",
1156 tid, instruction->readPC(), inst_seq);
1157
1158 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1159 tid, instruction->staticInst->disassemble(fetch_PC));
1160
1161 instruction->traceData =
1162 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1163 instruction->staticInst,
1164 instruction->readPC());
1165
1166 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1167 next_NPC);
1168
1169 // Add instruction to the CPU's list of instructions.
1170 instruction->setInstListIt(cpu->addInst(instruction));
1171
1172 // Write the instruction to the first slot in the queue
1173 // that heads to decode.
1174 toDecode->insts[numInst] = instruction;
1175
1176 toDecode->size++;
1177
1178 // Increment stat of fetched instructions.
1179 ++fetchedInsts;
1180
1181 // Move to the next instruction, unless we have a branch.
1182 fetch_PC = next_PC;
1183
1184 if (instruction->isQuiesce()) {
1185 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1186 curTick);
1187 fetchStatus[tid] = QuiescePending;
1188 ++numInst;
1189 status_change = true;
1190 break;
1191 }
1192
1193 offset += instSize;
1194
1195#if ISA_HAS_DELAY_SLOT
1196 if (predicted_branch) {
1197 delaySlotInfo[tid].branchSeqNum = inst_seq;
1198
1199 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1200 tid, inst_seq);
1201 continue;
1202 } else if (delaySlotInfo[tid].numInsts > 0) {
1203 --delaySlotInfo[tid].numInsts;
1204
1205 // It's OK to set PC to target of branch
1206 if (delaySlotInfo[tid].numInsts == 0) {
1207 delaySlotInfo[tid].targetReady = true;
1208
1209 // Break the looping condition
1210 predicted_branch = true;
1211 }
1212
1213 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1214 " process.\n", tid, delaySlotInfo[tid].numInsts);
1215 }
1216#endif
1217 }
1218
1219 if (offset >= cacheBlkSize) {
1220 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1221 "block.\n", tid);
1222 } else if (numInst >= fetchWidth) {
1223 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1224 "for this cycle.\n", tid);
1225 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1226 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1227 "instruction encountered.\n", tid);
1228 }
1229 }
1230
1231 if (numInst > 0) {
1232 wroteToTimeBuffer = true;
1233 }
1234
1235 // Now that fetching is completed, update the PC to signify what the next
1236 // cycle will be.
1237 if (fault == NoFault) {
1238#if ISA_HAS_DELAY_SLOT
1239 if (delaySlotInfo[tid].targetReady &&
1240 delaySlotInfo[tid].numInsts == 0) {
1241 // Set PC to target
1242 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1243 nextPC[tid] = next_PC + instSize; //next_NPC
1244 nextNPC[tid] = next_PC + (2 * instSize);
1245
1246 delaySlotInfo[tid].targetReady = false;
1247 } else {
1248 PC[tid] = next_PC;
1249 nextPC[tid] = next_NPC;
1250 nextNPC[tid] = next_NPC + instSize;
1251 }
1252
1253 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1254#else
1255 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1256 PC[tid] = next_PC;
1257 nextPC[tid] = next_PC + instSize;
1258#endif
1259 } else {
1260 // We shouldn't be in an icache miss and also have a fault (an ITB
1261 // miss)
1262 if (fetchStatus[tid] == IcacheWaitResponse) {
1263 panic("Fetch should have exited prior to this!");
1264 }
1265
1266 // Send the fault to commit. This thread will not do anything
1267 // until commit handles the fault. The only other way it can
1268 // wake up is if a squash comes along and changes the PC.
1269#if FULL_SYSTEM
1270 assert(numInst != fetchWidth);
1271 // Get a sequence number.
1272 inst_seq = cpu->getAndIncrementInstSeq();
1273 // We will use a nop in order to carry the fault.
1274 ext_inst = TheISA::NoopMachInst;
1275
1276 // Create a new DynInst from the dummy nop.
1277 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1278 next_PC,
1279 inst_seq, cpu);
1280 instruction->setPredTarg(next_PC + instSize);
1281 instruction->setTid(tid);
1282
1283 instruction->setASID(tid);
1284
1285 instruction->setThreadState(cpu->thread[tid]);
1286
1287 instruction->traceData = NULL;
1288
1289 instruction->setInstListIt(cpu->addInst(instruction));
1290
1291 instruction->fault = fault;
1292
1293 toDecode->insts[numInst] = instruction;
1294 toDecode->size++;
1295
1296 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1297
1298 fetchStatus[tid] = TrapPending;
1299 status_change = true;
1300#else // !FULL_SYSTEM
1301 fetchStatus[tid] = TrapPending;
1302 status_change = true;
1303
1304#endif // FULL_SYSTEM
1305 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1306 tid, fault->name(), PC[tid]);
1307 }
1308}
1309
1310template<class Impl>
1311void
1312DefaultFetch<Impl>::recvRetry()
1313{
1314 if (retryPkt != NULL) {
1315 assert(cacheBlocked);
1316 assert(retryTid != -1);
1317 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1318
1319 if (icachePort->sendTiming(retryPkt)) {
1320 fetchStatus[retryTid] = IcacheWaitResponse;
1321 retryPkt = NULL;
1322 retryTid = -1;
1323 cacheBlocked = false;
1324 }
1325 } else {
1326 assert(retryTid == -1);
1327 // Access has been squashed since it was sent out. Just clear
1328 // the cache being blocked.
1329 cacheBlocked = false;
1330 }
1331}
1332
1333///////////////////////////////////////
1334// //
1335// SMT FETCH POLICY MAINTAINED HERE //
1336// //
1337///////////////////////////////////////
1338template<class Impl>
1339int
1340DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1341{
1342 if (numThreads > 1) {
1343 switch (fetch_priority) {
1344
1345 case SingleThread:
1346 return 0;
1347
1348 case RoundRobin:
1349 return roundRobin();
1350
1351 case IQ:
1352 return iqCount();
1353
1354 case LSQ:
1355 return lsqCount();
1356
1357 case Branch:
1358 return branchCount();
1359
1360 default:
1361 return -1;
1362 }
1363 } else {
1364 int tid = *((*activeThreads).begin());
1365
1366 if (fetchStatus[tid] == Running ||
1367 fetchStatus[tid] == IcacheAccessComplete ||
1368 fetchStatus[tid] == Idle) {
1369 return tid;
1370 } else {
1371 return -1;
1372 }
1373 }
1374
1375}
1376
1377
1378template<class Impl>
1379int
1380DefaultFetch<Impl>::roundRobin()
1381{
1382 std::list<unsigned>::iterator pri_iter = priorityList.begin();
1383 std::list<unsigned>::iterator end = priorityList.end();
1384
1385 int high_pri;
1386
1387 while (pri_iter != end) {
1388 high_pri = *pri_iter;
1389
1390 assert(high_pri <= numThreads);
1391
1392 if (fetchStatus[high_pri] == Running ||
1393 fetchStatus[high_pri] == IcacheAccessComplete ||
1394 fetchStatus[high_pri] == Idle) {
1395
1396 priorityList.erase(pri_iter);
1397 priorityList.push_back(high_pri);
1398
1399 return high_pri;
1400 }
1401
1402 pri_iter++;
1403 }
1404
1405 return -1;
1406}
1407
1408template<class Impl>
1409int
1410DefaultFetch<Impl>::iqCount()
1411{
1412 std::priority_queue<unsigned> PQ;
1413
1414 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1415
1416 while (threads != (*activeThreads).end()) {
1417 unsigned tid = *threads++;
1418
1419 PQ.push(fromIEW->iewInfo[tid].iqCount);
1420 }
1421
1422 while (!PQ.empty()) {
1423
1424 unsigned high_pri = PQ.top();
1425
1426 if (fetchStatus[high_pri] == Running ||
1427 fetchStatus[high_pri] == IcacheAccessComplete ||
1428 fetchStatus[high_pri] == Idle)
1429 return high_pri;
1430 else
1431 PQ.pop();
1432
1433 }
1434
1435 return -1;
1436}
1437
1438template<class Impl>
1439int
1440DefaultFetch<Impl>::lsqCount()
1441{
1442 std::priority_queue<unsigned> PQ;
1443
1444
1445 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1446
1447 while (threads != (*activeThreads).end()) {
1448 unsigned tid = *threads++;
1449
1450 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1451 }
1452
1453 while (!PQ.empty()) {
1454
1455 unsigned high_pri = PQ.top();
1456
1457 if (fetchStatus[high_pri] == Running ||
1458 fetchStatus[high_pri] == IcacheAccessComplete ||
1459 fetchStatus[high_pri] == Idle)
1460 return high_pri;
1461 else
1462 PQ.pop();
1463
1464 }
1465
1466 return -1;
1467}
1468
1469template<class Impl>
1470int
1471DefaultFetch<Impl>::branchCount()
1472{
1473 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1474 panic("Branch Count Fetch policy unimplemented\n");
1475 return *threads;
1476}
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