101 decodeToFetchDelay(params->decodeToFetchDelay),
102 renameToFetchDelay(params->renameToFetchDelay),
103 iewToFetchDelay(params->iewToFetchDelay),
104 commitToFetchDelay(params->commitToFetchDelay),
105 fetchWidth(params->fetchWidth),
106 cacheBlocked(false),
107 retryPkt(NULL),
108 retryTid(-1),
109 numThreads(params->numberOfThreads),
110 numFetchingThreads(params->smtNumFetchingThreads),
111 interruptPending(false),
112 drainPending(false),
113 switchedOut(false)
114{
115 if (numThreads > Impl::MaxThreads)
116 fatal("numThreads is not a valid value\n");
117
118 // Set fetch stage's status to inactive.
119 _status = Inactive;
120
121 std::string policy = params->smtFetchPolicy;
122
123 // Convert string to lowercase
124 std::transform(policy.begin(), policy.end(), policy.begin(),
125 (int(*)(int)) tolower);
126
127 // Figure out fetch policy
128 if (policy == "singlethread") {
129 fetchPolicy = SingleThread;
130 if (numThreads > 1)
131 panic("Invalid Fetch Policy for a SMT workload.");
132 } else if (policy == "roundrobin") {
133 fetchPolicy = RoundRobin;
134 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
135 } else if (policy == "branch") {
136 fetchPolicy = Branch;
137 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
138 } else if (policy == "iqcount") {
139 fetchPolicy = IQ;
140 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
141 } else if (policy == "lsqcount") {
142 fetchPolicy = LSQ;
143 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
144 } else {
145 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
146 " RoundRobin,LSQcount,IQcount}\n");
147 }
148
149 // Size of cache block.
150 cacheBlkSize = 64;
151
152 // Create mask to get rid of offset bits.
153 cacheBlkMask = (cacheBlkSize - 1);
154
155 for (int tid=0; tid < numThreads; tid++) {
156
157 fetchStatus[tid] = Running;
158
159 priorityList.push_back(tid);
160
161 memReq[tid] = NULL;
162
163 // Create space to store a cache line.
164 cacheData[tid] = new uint8_t[cacheBlkSize];
165 cacheDataPC[tid] = 0;
166 cacheDataValid[tid] = false;
167
168 delaySlotInfo[tid].branchSeqNum = -1;
169 delaySlotInfo[tid].numInsts = 0;
170 delaySlotInfo[tid].targetAddr = 0;
171 delaySlotInfo[tid].targetReady = false;
172
173 stalls[tid].decode = false;
174 stalls[tid].rename = false;
175 stalls[tid].iew = false;
176 stalls[tid].commit = false;
177 }
178
179 // Get the size of an instruction.
180 instSize = sizeof(TheISA::MachInst);
181}
182
183template <class Impl>
184std::string
185DefaultFetch<Impl>::name() const
186{
187 return cpu->name() + ".fetch";
188}
189
190template <class Impl>
191void
192DefaultFetch<Impl>::regStats()
193{
194 icacheStallCycles
195 .name(name() + ".icacheStallCycles")
196 .desc("Number of cycles fetch is stalled on an Icache miss")
197 .prereq(icacheStallCycles);
198
199 fetchedInsts
200 .name(name() + ".Insts")
201 .desc("Number of instructions fetch has processed")
202 .prereq(fetchedInsts);
203
204 fetchedBranches
205 .name(name() + ".Branches")
206 .desc("Number of branches that fetch encountered")
207 .prereq(fetchedBranches);
208
209 predictedBranches
210 .name(name() + ".predictedBranches")
211 .desc("Number of branches that fetch has predicted taken")
212 .prereq(predictedBranches);
213
214 fetchCycles
215 .name(name() + ".Cycles")
216 .desc("Number of cycles fetch has run and was not squashing or"
217 " blocked")
218 .prereq(fetchCycles);
219
220 fetchSquashCycles
221 .name(name() + ".SquashCycles")
222 .desc("Number of cycles fetch has spent squashing")
223 .prereq(fetchSquashCycles);
224
225 fetchIdleCycles
226 .name(name() + ".IdleCycles")
227 .desc("Number of cycles fetch was idle")
228 .prereq(fetchIdleCycles);
229
230 fetchBlockedCycles
231 .name(name() + ".BlockedCycles")
232 .desc("Number of cycles fetch has spent blocked")
233 .prereq(fetchBlockedCycles);
234
235 fetchedCacheLines
236 .name(name() + ".CacheLines")
237 .desc("Number of cache lines fetched")
238 .prereq(fetchedCacheLines);
239
240 fetchMiscStallCycles
241 .name(name() + ".MiscStallCycles")
242 .desc("Number of cycles fetch has spent waiting on interrupts, or "
243 "bad addresses, or out of MSHRs")
244 .prereq(fetchMiscStallCycles);
245
246 fetchIcacheSquashes
247 .name(name() + ".IcacheSquashes")
248 .desc("Number of outstanding Icache misses that were squashed")
249 .prereq(fetchIcacheSquashes);
250
251 fetchNisnDist
252 .init(/* base value */ 0,
253 /* last value */ fetchWidth,
254 /* bucket size */ 1)
255 .name(name() + ".rateDist")
256 .desc("Number of instructions fetched each cycle (Total)")
257 .flags(Stats::pdf);
258
259 idleRate
260 .name(name() + ".idleRate")
261 .desc("Percent of cycles fetch was idle")
262 .prereq(idleRate);
263 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
264
265 branchRate
266 .name(name() + ".branchRate")
267 .desc("Number of branch fetches per cycle")
268 .flags(Stats::total);
269 branchRate = fetchedBranches / cpu->numCycles;
270
271 fetchRate
272 .name(name() + ".rate")
273 .desc("Number of inst fetches per cycle")
274 .flags(Stats::total);
275 fetchRate = fetchedInsts / cpu->numCycles;
276
277 branchPred.regStats();
278}
279
280template<class Impl>
281void
282DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
283{
284 DPRINTF(Fetch, "Setting the CPU pointer.\n");
285 cpu = cpu_ptr;
286
287 // Name is finally available, so create the port.
288 icachePort = new IcachePort(this);
289
290#if USE_CHECKER
291 if (cpu->checker) {
292 cpu->checker->setIcachePort(icachePort);
293 }
294#endif
295
296 // Schedule fetch to get the correct PC from the CPU
297 // scheduleFetchStartupEvent(1);
298
299 // Fetch needs to start fetching instructions at the very beginning,
300 // so it must start up in active state.
301 switchToActive();
302}
303
304template<class Impl>
305void
306DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
307{
308 DPRINTF(Fetch, "Setting the time buffer pointer.\n");
309 timeBuffer = time_buffer;
310
311 // Create wires to get information from proper places in time buffer.
312 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
313 fromRename = timeBuffer->getWire(-renameToFetchDelay);
314 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
315 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
316}
317
318template<class Impl>
319void
320DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
321{
322 DPRINTF(Fetch, "Setting active threads list pointer.\n");
323 activeThreads = at_ptr;
324}
325
326template<class Impl>
327void
328DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
329{
330 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
331 fetchQueue = fq_ptr;
332
333 // Create wire to write information to proper place in fetch queue.
334 toDecode = fetchQueue->getWire(0);
335}
336
337template<class Impl>
338void
339DefaultFetch<Impl>::initStage()
340{
341 // Setup PC and nextPC with initial state.
342 for (int tid = 0; tid < numThreads; tid++) {
343 PC[tid] = cpu->readPC(tid);
344 nextPC[tid] = cpu->readNextPC(tid);
345#if ISA_HAS_DELAY_SLOT
346 nextNPC[tid] = cpu->readNextNPC(tid);
347#endif
348 }
349}
350
351template<class Impl>
352void
353DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
354{
355 unsigned tid = pkt->req->getThreadNum();
356
357 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
358
359 // Only change the status if it's still waiting on the icache access
360 // to return.
361 if (fetchStatus[tid] != IcacheWaitResponse ||
362 pkt->req != memReq[tid] ||
363 isSwitchedOut()) {
364 ++fetchIcacheSquashes;
365 delete pkt->req;
366 delete pkt;
367 return;
368 }
369
370 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
371 cacheDataValid[tid] = true;
372
373 if (!drainPending) {
374 // Wake up the CPU (if it went to sleep and was waiting on
375 // this completion event).
376 cpu->wakeCPU();
377
378 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
379 tid);
380
381 switchToActive();
382 }
383
384 // Only switch to IcacheAccessComplete if we're not stalled as well.
385 if (checkStall(tid)) {
386 fetchStatus[tid] = Blocked;
387 } else {
388 fetchStatus[tid] = IcacheAccessComplete;
389 }
390
391 // Reset the mem req to NULL.
392 delete pkt->req;
393 delete pkt;
394 memReq[tid] = NULL;
395}
396
397template <class Impl>
398bool
399DefaultFetch<Impl>::drain()
400{
401 // Fetch is ready to drain at any time.
402 cpu->signalDrained();
403 drainPending = true;
404 return true;
405}
406
407template <class Impl>
408void
409DefaultFetch<Impl>::resume()
410{
411 drainPending = false;
412}
413
414template <class Impl>
415void
416DefaultFetch<Impl>::switchOut()
417{
418 switchedOut = true;
419 // Branch predictor needs to have its state cleared.
420 branchPred.switchOut();
421}
422
423template <class Impl>
424void
425DefaultFetch<Impl>::takeOverFrom()
426{
427 // Reset all state
428 for (int i = 0; i < Impl::MaxThreads; ++i) {
429 stalls[i].decode = 0;
430 stalls[i].rename = 0;
431 stalls[i].iew = 0;
432 stalls[i].commit = 0;
433 PC[i] = cpu->readPC(i);
434 nextPC[i] = cpu->readNextPC(i);
435#if ISA_HAS_DELAY_SLOT
436 nextNPC[i] = cpu->readNextNPC(i);
437 delaySlotInfo[i].branchSeqNum = -1;
438 delaySlotInfo[i].numInsts = 0;
439 delaySlotInfo[i].targetAddr = 0;
440 delaySlotInfo[i].targetReady = false;
441#endif
442 fetchStatus[i] = Running;
443 }
444 numInst = 0;
445 wroteToTimeBuffer = false;
446 _status = Inactive;
447 switchedOut = false;
448 interruptPending = false;
449 branchPred.takeOverFrom();
450}
451
452template <class Impl>
453void
454DefaultFetch<Impl>::wakeFromQuiesce()
455{
456 DPRINTF(Fetch, "Waking up from quiesce\n");
457 // Hopefully this is safe
458 // @todo: Allow other threads to wake from quiesce.
459 fetchStatus[0] = Running;
460}
461
462template <class Impl>
463inline void
464DefaultFetch<Impl>::switchToActive()
465{
466 if (_status == Inactive) {
467 DPRINTF(Activity, "Activating stage.\n");
468
469 cpu->activateStage(O3CPU::FetchIdx);
470
471 _status = Active;
472 }
473}
474
475template <class Impl>
476inline void
477DefaultFetch<Impl>::switchToInactive()
478{
479 if (_status == Active) {
480 DPRINTF(Activity, "Deactivating stage.\n");
481
482 cpu->deactivateStage(O3CPU::FetchIdx);
483
484 _status = Inactive;
485 }
486}
487
488template <class Impl>
489bool
490DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
491 Addr &next_NPC)
492{
493 // Do branch prediction check here.
494 // A bit of a misnomer...next_PC is actually the current PC until
495 // this function updates it.
496 bool predict_taken;
497
498 if (!inst->isControl()) {
499#if ISA_HAS_DELAY_SLOT
500 Addr cur_PC = next_PC;
501 next_PC = cur_PC + instSize; //next_NPC;
502 next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
503 inst->setPredTarg(next_NPC);
504#else
505 next_PC = next_PC + instSize;
506 inst->setPredTarg(next_PC);
507#endif
508 return false;
509 }
510
511 int tid = inst->threadNumber;
512#if ISA_HAS_DELAY_SLOT
513 Addr pred_PC = next_PC;
514 predict_taken = branchPred.predict(inst, pred_PC, tid);
515
516 if (predict_taken) {
517 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
518 } else {
519 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
520 }
521
522 if (predict_taken) {
523 next_PC = next_NPC;
524 next_NPC = pred_PC;
525
526 // Update delay slot info
527 ++delaySlotInfo[tid].numInsts;
528 delaySlotInfo[tid].targetAddr = pred_PC;
529 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
530 delaySlotInfo[tid].numInsts);
531 } else { // !predict_taken
532 if (inst->isCondDelaySlot()) {
533 next_PC = pred_PC;
534 // The delay slot is skipped here if there is on
535 // prediction
536 } else {
537 next_PC = next_NPC;
538 // No need to declare a delay slot here since
539 // there is no for the pred. target to jump
540 }
541
542 next_NPC = next_NPC + instSize;
543 }
544#else
545 predict_taken = branchPred.predict(inst, next_PC, tid);
546#endif
547
548 ++fetchedBranches;
549
550 if (predict_taken) {
551 ++predictedBranches;
552 }
553
554 return predict_taken;
555}
556
557template <class Impl>
558bool
559DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
560{
561 Fault fault = NoFault;
562
563#if FULL_SYSTEM
564 // Flag to say whether or not address is physical addr.
565 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
566#else
567 unsigned flags = 0;
568#endif // FULL_SYSTEM
569
570 if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
571 // Hold off fetch from getting new instructions when:
572 // Cache is blocked, or
573 // while an interrupt is pending and we're not in PAL mode, or
574 // fetch is switched out.
575 return false;
576 }
577
578 // Align the fetch PC so it's at the start of a cache block.
579 fetch_PC = icacheBlockAlignPC(fetch_PC);
580
581 // If we've already got the block, no need to try to fetch it again.
582 if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
583 return true;
584 }
585
586 // Setup the memReq to do a read of the first instruction's address.
587 // Set the appropriate read size and flags as well.
588 // Build request here.
589 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
590 fetch_PC, cpu->readCpuId(), tid);
591
592 memReq[tid] = mem_req;
593
594 // Translate the instruction request.
595 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
596
597 // In the case of faults, the fetch stage may need to stall and wait
598 // for the ITB miss to be handled.
599
600 // If translation was successful, attempt to read the first
601 // instruction.
602 if (fault == NoFault) {
603#if 0
604 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
605 memReq[tid]->isUncacheable()) {
606 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
607 "misspeculating path)!",
608 memReq[tid]->paddr);
609 ret_fault = TheISA::genMachineCheckFault();
610 return false;
611 }
612#endif
613
614 // Build packet here.
615 PacketPtr data_pkt = new Packet(mem_req,
616 Packet::ReadReq, Packet::Broadcast);
617 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
618
619 cacheDataPC[tid] = fetch_PC;
620 cacheDataValid[tid] = false;
621
622 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
623
624 fetchedCacheLines++;
625
626 // Now do the timing access to see whether or not the instruction
627 // exists within the cache.
628 if (!icachePort->sendTiming(data_pkt)) {
629 if (data_pkt->result == Packet::BadAddress) {
630 fault = TheISA::genMachineCheckFault();
631 delete mem_req;
632 memReq[tid] = NULL;
633 }
634 assert(retryPkt == NULL);
635 assert(retryTid == -1);
636 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
637 fetchStatus[tid] = IcacheWaitRetry;
638 retryPkt = data_pkt;
639 retryTid = tid;
640 cacheBlocked = true;
641 return false;
642 }
643
644 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
645
646 lastIcacheStall[tid] = curTick;
647
648 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
649 "response.\n", tid);
650
651 fetchStatus[tid] = IcacheWaitResponse;
652 } else {
653 delete mem_req;
654 memReq[tid] = NULL;
655 }
656
657 ret_fault = fault;
658 return true;
659}
660
661template <class Impl>
662inline void
663DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
664{
665 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
666 tid, new_PC);
667
668 PC[tid] = new_PC;
669 nextPC[tid] = new_PC + instSize;
670 nextNPC[tid] = new_PC + (2 * instSize);
671
672 // Clear the icache miss if it's outstanding.
673 if (fetchStatus[tid] == IcacheWaitResponse) {
674 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
675 tid);
676 memReq[tid] = NULL;
677 }
678
679 // Get rid of the retrying packet if it was from this thread.
680 if (retryTid == tid) {
681 assert(cacheBlocked);
682 cacheBlocked = false;
683 retryTid = -1;
684 delete retryPkt->req;
685 delete retryPkt;
686 retryPkt = NULL;
687 }
688
689 fetchStatus[tid] = Squashing;
690
691 ++fetchSquashCycles;
692}
693
694template<class Impl>
695void
696DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
697 const InstSeqNum &seq_num,
698 unsigned tid)
699{
700 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
701
702 doSquash(new_PC, tid);
703
704#if ISA_HAS_DELAY_SLOT
705 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
706 delaySlotInfo[tid].numInsts = 0;
707 delaySlotInfo[tid].targetAddr = 0;
708 delaySlotInfo[tid].targetReady = false;
709 }
710#endif
711
712 // Tell the CPU to remove any instructions that are in flight between
713 // fetch and decode.
714 cpu->removeInstsUntil(seq_num, tid);
715}
716
717template<class Impl>
718bool
719DefaultFetch<Impl>::checkStall(unsigned tid) const
720{
721 bool ret_val = false;
722
723 if (cpu->contextSwitch) {
724 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
725 ret_val = true;
726 } else if (stalls[tid].decode) {
727 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
728 ret_val = true;
729 } else if (stalls[tid].rename) {
730 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
731 ret_val = true;
732 } else if (stalls[tid].iew) {
733 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
734 ret_val = true;
735 } else if (stalls[tid].commit) {
736 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
737 ret_val = true;
738 }
739
740 return ret_val;
741}
742
743template<class Impl>
744typename DefaultFetch<Impl>::FetchStatus
745DefaultFetch<Impl>::updateFetchStatus()
746{
747 //Check Running
748 std::list<unsigned>::iterator threads = (*activeThreads).begin();
749
750 while (threads != (*activeThreads).end()) {
751
752 unsigned tid = *threads++;
753
754 if (fetchStatus[tid] == Running ||
755 fetchStatus[tid] == Squashing ||
756 fetchStatus[tid] == IcacheAccessComplete) {
757
758 if (_status == Inactive) {
759 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
760
761 if (fetchStatus[tid] == IcacheAccessComplete) {
762 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
763 "completion\n",tid);
764 }
765
766 cpu->activateStage(O3CPU::FetchIdx);
767 }
768
769 return Active;
770 }
771 }
772
773 // Stage is switching from active to inactive, notify CPU of it.
774 if (_status == Active) {
775 DPRINTF(Activity, "Deactivating stage.\n");
776
777 cpu->deactivateStage(O3CPU::FetchIdx);
778 }
779
780 return Inactive;
781}
782
783template <class Impl>
784void
785DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
786 bool squash_delay_slot, unsigned tid)
787{
788 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
789
790 doSquash(new_PC, tid);
791
792#if ISA_HAS_DELAY_SLOT
793 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
794 delaySlotInfo[tid].numInsts = 0;
795 delaySlotInfo[tid].targetAddr = 0;
796 delaySlotInfo[tid].targetReady = false;
797 }
798
799 // Tell the CPU to remove any instructions that are not in the ROB.
800 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
801#else
802 // Tell the CPU to remove any instructions that are not in the ROB.
803 cpu->removeInstsNotInROB(tid, true, 0);
804#endif
805}
806
807template <class Impl>
808void
809DefaultFetch<Impl>::tick()
810{
811 std::list<unsigned>::iterator threads = (*activeThreads).begin();
812 bool status_change = false;
813
814 wroteToTimeBuffer = false;
815
816 while (threads != (*activeThreads).end()) {
817 unsigned tid = *threads++;
818
819 // Check the signals for each thread to determine the proper status
820 // for each thread.
821 bool updated_status = checkSignalsAndUpdate(tid);
822 status_change = status_change || updated_status;
823 }
824
825 DPRINTF(Fetch, "Running stage.\n");
826
827 // Reset the number of the instruction we're fetching.
828 numInst = 0;
829
830#if FULL_SYSTEM
831 if (fromCommit->commitInfo[0].interruptPending) {
832 interruptPending = true;
833 }
834
835 if (fromCommit->commitInfo[0].clearInterrupt) {
836 interruptPending = false;
837 }
838#endif
839
840 for (threadFetched = 0; threadFetched < numFetchingThreads;
841 threadFetched++) {
842 // Fetch each of the actively fetching threads.
843 fetch(status_change);
844 }
845
846 // Record number of instructions fetched this cycle for distribution.
847 fetchNisnDist.sample(numInst);
848
849 if (status_change) {
850 // Change the fetch stage status if there was a status change.
851 _status = updateFetchStatus();
852 }
853
854 // If there was activity this cycle, inform the CPU of it.
855 if (wroteToTimeBuffer || cpu->contextSwitch) {
856 DPRINTF(Activity, "Activity this cycle.\n");
857
858 cpu->activityThisCycle();
859 }
860}
861
862template <class Impl>
863bool
864DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
865{
866 // Update the per thread stall statuses.
867 if (fromDecode->decodeBlock[tid]) {
868 stalls[tid].decode = true;
869 }
870
871 if (fromDecode->decodeUnblock[tid]) {
872 assert(stalls[tid].decode);
873 assert(!fromDecode->decodeBlock[tid]);
874 stalls[tid].decode = false;
875 }
876
877 if (fromRename->renameBlock[tid]) {
878 stalls[tid].rename = true;
879 }
880
881 if (fromRename->renameUnblock[tid]) {
882 assert(stalls[tid].rename);
883 assert(!fromRename->renameBlock[tid]);
884 stalls[tid].rename = false;
885 }
886
887 if (fromIEW->iewBlock[tid]) {
888 stalls[tid].iew = true;
889 }
890
891 if (fromIEW->iewUnblock[tid]) {
892 assert(stalls[tid].iew);
893 assert(!fromIEW->iewBlock[tid]);
894 stalls[tid].iew = false;
895 }
896
897 if (fromCommit->commitBlock[tid]) {
898 stalls[tid].commit = true;
899 }
900
901 if (fromCommit->commitUnblock[tid]) {
902 assert(stalls[tid].commit);
903 assert(!fromCommit->commitBlock[tid]);
904 stalls[tid].commit = false;
905 }
906
907 // Check squash signals from commit.
908 if (fromCommit->commitInfo[tid].squash) {
909
910 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
911 "from commit.\n",tid);
912
913#if ISA_HAS_DELAY_SLOT
914 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
915#else
916 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
917#endif
918 // In any case, squash.
919 squash(fromCommit->commitInfo[tid].nextPC,
920 doneSeqNum,
921 fromCommit->commitInfo[tid].squashDelaySlot,
922 tid);
923
924 // Also check if there's a mispredict that happened.
925 if (fromCommit->commitInfo[tid].branchMispredict) {
926 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
927 fromCommit->commitInfo[tid].nextPC,
928 fromCommit->commitInfo[tid].branchTaken,
929 tid);
930 } else {
931 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
932 tid);
933 }
934
935 return true;
936 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
937 // Update the branch predictor if it wasn't a squashed instruction
938 // that was broadcasted.
939 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
940 }
941
942 // Check ROB squash signals from commit.
943 if (fromCommit->commitInfo[tid].robSquashing) {
944 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
945
946 // Continue to squash.
947 fetchStatus[tid] = Squashing;
948
949 return true;
950 }
951
952 // Check squash signals from decode.
953 if (fromDecode->decodeInfo[tid].squash) {
954 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
955 "from decode.\n",tid);
956
957 // Update the branch predictor.
958 if (fromDecode->decodeInfo[tid].branchMispredict) {
959 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
960 fromDecode->decodeInfo[tid].nextPC,
961 fromDecode->decodeInfo[tid].branchTaken,
962 tid);
963 } else {
964 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
965 tid);
966 }
967
968 if (fetchStatus[tid] != Squashing) {
969
970#if ISA_HAS_DELAY_SLOT
971 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
972#else
973 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
974#endif
975 // Squash unless we're already squashing
976 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
977 doneSeqNum,
978 tid);
979
980 return true;
981 }
982 }
983
984 if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
985 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
986
987 fetchStatus[tid] = Blocked;
988
989 return true;
990 }
991
992 if (fetchStatus[tid] == Blocked ||
993 fetchStatus[tid] == Squashing) {
994 // Switch status to running if fetch isn't being told to block or
995 // squash this cycle.
996 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
997 tid);
998
999 fetchStatus[tid] = Running;
1000
1001 return true;
1002 }
1003
1004 // If we've reached this point, we have not gotten any signals that
1005 // cause fetch to change its status. Fetch remains the same as before.
1006 return false;
1007}
1008
1009template<class Impl>
1010void
1011DefaultFetch<Impl>::fetch(bool &status_change)
1012{
1013 //////////////////////////////////////////
1014 // Start actual fetch
1015 //////////////////////////////////////////
1016 int tid = getFetchingThread(fetchPolicy);
1017
1018 if (tid == -1 || drainPending) {
1019 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1020
1021 // Breaks looping condition in tick()
1022 threadFetched = numFetchingThreads;
1023 return;
1024 }
1025
1026 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1027
1028 // The current PC.
1029 Addr &fetch_PC = PC[tid];
1030
1031 // Fault code for memory access.
1032 Fault fault = NoFault;
1033
1034 // If returning from the delay of a cache miss, then update the status
1035 // to running, otherwise do the cache access. Possibly move this up
1036 // to tick() function.
1037 if (fetchStatus[tid] == IcacheAccessComplete) {
1038 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1039 tid);
1040
1041 fetchStatus[tid] = Running;
1042 status_change = true;
1043 } else if (fetchStatus[tid] == Running) {
1044 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1045 "instruction, starting at PC %08p.\n",
1046 tid, fetch_PC);
1047
1048 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1049 if (!fetch_success) {
1050 if (cacheBlocked) {
1051 ++icacheStallCycles;
1052 } else {
1053 ++fetchMiscStallCycles;
1054 }
1055 return;
1056 }
1057 } else {
1058 if (fetchStatus[tid] == Idle) {
1059 ++fetchIdleCycles;
1060 } else if (fetchStatus[tid] == Blocked) {
1061 ++fetchBlockedCycles;
1062 } else if (fetchStatus[tid] == Squashing) {
1063 ++fetchSquashCycles;
1064 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1065 ++icacheStallCycles;
1066 }
1067
1068 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1069 // fetch should do nothing.
1070 return;
1071 }
1072
1073 ++fetchCycles;
1074
1075 // If we had a stall due to an icache miss, then return.
1076 if (fetchStatus[tid] == IcacheWaitResponse) {
1077 ++icacheStallCycles;
1078 status_change = true;
1079 return;
1080 }
1081
1082 Addr next_PC = fetch_PC;
1083 Addr next_NPC = next_PC + instSize;
1084 InstSeqNum inst_seq;
1085 MachInst inst;
1086 ExtMachInst ext_inst;
1087 // @todo: Fix this hack.
1088 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1089
1090 if (fault == NoFault) {
1091 // If the read of the first instruction was successful, then grab the
1092 // instructions from the rest of the cache line and put them into the
1093 // queue heading to decode.
1094
1095 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1096 "decode.\n",tid);
1097
1098 // Need to keep track of whether or not a predicted branch
1099 // ended this fetch block.
1100 bool predicted_branch = false;
1101
1102 // Need to keep track of whether or not a delay slot
1103 // instruction has been fetched
1104
1105 for (;
1106 offset < cacheBlkSize &&
1107 numInst < fetchWidth &&
1108 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1109 ++numInst) {
1110
1111 // Get a sequence number.
1112 inst_seq = cpu->getAndIncrementInstSeq();
1113
1114 // Make sure this is a valid index.
1115 assert(offset <= cacheBlkSize - instSize);
1116
1117 // Get the instruction from the array of the cache line.
1118 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1119 (&cacheData[tid][offset]));
1120
1121 ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid));
1122
1123 // Create a new DynInst from the instruction fetched.
1124 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1125 next_PC,
1126 inst_seq, cpu);
1127 instruction->setTid(tid);
1128
1129 instruction->setASID(tid);
1130
1131 instruction->setThreadState(cpu->thread[tid]);
1132
1133 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1134 "[sn:%lli]\n",
1135 tid, instruction->readPC(), inst_seq);
1136
1137 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1138 tid, instruction->staticInst->disassemble(fetch_PC));
1139
1140 instruction->traceData =
1141 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1142 instruction->staticInst,
1143 instruction->readPC());
1144
1145 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1146 next_NPC);
1147
1148 // Add instruction to the CPU's list of instructions.
1149 instruction->setInstListIt(cpu->addInst(instruction));
1150
1151 // Write the instruction to the first slot in the queue
1152 // that heads to decode.
1153 toDecode->insts[numInst] = instruction;
1154
1155 toDecode->size++;
1156
1157 // Increment stat of fetched instructions.
1158 ++fetchedInsts;
1159
1160 // Move to the next instruction, unless we have a branch.
1161 fetch_PC = next_PC;
1162
1163 if (instruction->isQuiesce()) {
1164// warn("%lli: Quiesce instruction encountered, halting fetch!",
1165// curTick);
1166 fetchStatus[tid] = QuiescePending;
1167 ++numInst;
1168 status_change = true;
1169 break;
1170 }
1171
1172 offset += instSize;
1173
1174#if ISA_HAS_DELAY_SLOT
1175 if (predicted_branch) {
1176 delaySlotInfo[tid].branchSeqNum = inst_seq;
1177
1178 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1179 tid, inst_seq);
1180 continue;
1181 } else if (delaySlotInfo[tid].numInsts > 0) {
1182 --delaySlotInfo[tid].numInsts;
1183
1184 // It's OK to set PC to target of branch
1185 if (delaySlotInfo[tid].numInsts == 0) {
1186 delaySlotInfo[tid].targetReady = true;
1187
1188 // Break the looping condition
1189 predicted_branch = true;
1190 }
1191
1192 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1193 " process.\n", tid, delaySlotInfo[tid].numInsts);
1194 }
1195#endif
1196 }
1197
1198 if (offset >= cacheBlkSize) {
1199 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1200 "block.\n", tid);
1201 } else if (numInst >= fetchWidth) {
1202 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1203 "for this cycle.\n", tid);
1204 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1205 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1206 "instruction encountered.\n", tid);
1207 }
1208 }
1209
1210 if (numInst > 0) {
1211 wroteToTimeBuffer = true;
1212 }
1213
1214 // Now that fetching is completed, update the PC to signify what the next
1215 // cycle will be.
1216 if (fault == NoFault) {
1217#if ISA_HAS_DELAY_SLOT
1218 if (delaySlotInfo[tid].targetReady &&
1219 delaySlotInfo[tid].numInsts == 0) {
1220 // Set PC to target
1221 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1222 nextPC[tid] = next_PC + instSize; //next_NPC
1223 nextNPC[tid] = next_PC + (2 * instSize);
1224
1225 delaySlotInfo[tid].targetReady = false;
1226 } else {
1227 PC[tid] = next_PC;
1228 nextPC[tid] = next_NPC;
1229 nextNPC[tid] = next_NPC + instSize;
1230 }
1231
1232 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1233#else
1234 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1235 PC[tid] = next_PC;
1236 nextPC[tid] = next_PC + instSize;
1237#endif
1238 } else {
1239 // We shouldn't be in an icache miss and also have a fault (an ITB
1240 // miss)
1241 if (fetchStatus[tid] == IcacheWaitResponse) {
1242 panic("Fetch should have exited prior to this!");
1243 }
1244
1245 // Send the fault to commit. This thread will not do anything
1246 // until commit handles the fault. The only other way it can
1247 // wake up is if a squash comes along and changes the PC.
1248#if FULL_SYSTEM
1249 assert(numInst != fetchWidth);
1250 // Get a sequence number.
1251 inst_seq = cpu->getAndIncrementInstSeq();
1252 // We will use a nop in order to carry the fault.
1253 ext_inst = TheISA::NoopMachInst;
1254
1255 // Create a new DynInst from the dummy nop.
1256 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1257 next_PC,
1258 inst_seq, cpu);
1259 instruction->setPredTarg(next_PC + instSize);
1260 instruction->setTid(tid);
1261
1262 instruction->setASID(tid);
1263
1264 instruction->setThreadState(cpu->thread[tid]);
1265
1266 instruction->traceData = NULL;
1267
1268 instruction->setInstListIt(cpu->addInst(instruction));
1269
1270 instruction->fault = fault;
1271
1272 toDecode->insts[numInst] = instruction;
1273 toDecode->size++;
1274
1275 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1276
1277 fetchStatus[tid] = TrapPending;
1278 status_change = true;
1279
1280// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1281#else // !FULL_SYSTEM
1282 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1283#endif // FULL_SYSTEM
1284 }
1285}
1286
1287template<class Impl>
1288void
1289DefaultFetch<Impl>::recvRetry()
1290{
1291 if (retryPkt != NULL) {
1292 assert(cacheBlocked);
1293 assert(retryTid != -1);
1294 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1295
1296 if (icachePort->sendTiming(retryPkt)) {
1297 fetchStatus[retryTid] = IcacheWaitResponse;
1298 retryPkt = NULL;
1299 retryTid = -1;
1300 cacheBlocked = false;
1301 }
1302 } else {
1303 assert(retryTid == -1);
1304 // Access has been squashed since it was sent out. Just clear
1305 // the cache being blocked.
1306 cacheBlocked = false;
1307 }
1308}
1309
1310///////////////////////////////////////
1311// //
1312// SMT FETCH POLICY MAINTAINED HERE //
1313// //
1314///////////////////////////////////////
1315template<class Impl>
1316int
1317DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1318{
1319 if (numThreads > 1) {
1320 switch (fetch_priority) {
1321
1322 case SingleThread:
1323 return 0;
1324
1325 case RoundRobin:
1326 return roundRobin();
1327
1328 case IQ:
1329 return iqCount();
1330
1331 case LSQ:
1332 return lsqCount();
1333
1334 case Branch:
1335 return branchCount();
1336
1337 default:
1338 return -1;
1339 }
1340 } else {
1341 int tid = *((*activeThreads).begin());
1342
1343 if (fetchStatus[tid] == Running ||
1344 fetchStatus[tid] == IcacheAccessComplete ||
1345 fetchStatus[tid] == Idle) {
1346 return tid;
1347 } else {
1348 return -1;
1349 }
1350 }
1351
1352}
1353
1354
1355template<class Impl>
1356int
1357DefaultFetch<Impl>::roundRobin()
1358{
1359 std::list<unsigned>::iterator pri_iter = priorityList.begin();
1360 std::list<unsigned>::iterator end = priorityList.end();
1361
1362 int high_pri;
1363
1364 while (pri_iter != end) {
1365 high_pri = *pri_iter;
1366
1367 assert(high_pri <= numThreads);
1368
1369 if (fetchStatus[high_pri] == Running ||
1370 fetchStatus[high_pri] == IcacheAccessComplete ||
1371 fetchStatus[high_pri] == Idle) {
1372
1373 priorityList.erase(pri_iter);
1374 priorityList.push_back(high_pri);
1375
1376 return high_pri;
1377 }
1378
1379 pri_iter++;
1380 }
1381
1382 return -1;
1383}
1384
1385template<class Impl>
1386int
1387DefaultFetch<Impl>::iqCount()
1388{
1389 std::priority_queue<unsigned> PQ;
1390
1391 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1392
1393 while (threads != (*activeThreads).end()) {
1394 unsigned tid = *threads++;
1395
1396 PQ.push(fromIEW->iewInfo[tid].iqCount);
1397 }
1398
1399 while (!PQ.empty()) {
1400
1401 unsigned high_pri = PQ.top();
1402
1403 if (fetchStatus[high_pri] == Running ||
1404 fetchStatus[high_pri] == IcacheAccessComplete ||
1405 fetchStatus[high_pri] == Idle)
1406 return high_pri;
1407 else
1408 PQ.pop();
1409
1410 }
1411
1412 return -1;
1413}
1414
1415template<class Impl>
1416int
1417DefaultFetch<Impl>::lsqCount()
1418{
1419 std::priority_queue<unsigned> PQ;
1420
1421
1422 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1423
1424 while (threads != (*activeThreads).end()) {
1425 unsigned tid = *threads++;
1426
1427 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1428 }
1429
1430 while (!PQ.empty()) {
1431
1432 unsigned high_pri = PQ.top();
1433
1434 if (fetchStatus[high_pri] == Running ||
1435 fetchStatus[high_pri] == IcacheAccessComplete ||
1436 fetchStatus[high_pri] == Idle)
1437 return high_pri;
1438 else
1439 PQ.pop();
1440
1441 }
1442
1443 return -1;
1444}
1445
1446template<class Impl>
1447int
1448DefaultFetch<Impl>::branchCount()
1449{
1450 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1451 panic("Branch Count Fetch policy unimplemented\n");
1452 return *threads;
1453}
| 100 decodeToFetchDelay(params->decodeToFetchDelay),
101 renameToFetchDelay(params->renameToFetchDelay),
102 iewToFetchDelay(params->iewToFetchDelay),
103 commitToFetchDelay(params->commitToFetchDelay),
104 fetchWidth(params->fetchWidth),
105 cacheBlocked(false),
106 retryPkt(NULL),
107 retryTid(-1),
108 numThreads(params->numberOfThreads),
109 numFetchingThreads(params->smtNumFetchingThreads),
110 interruptPending(false),
111 drainPending(false),
112 switchedOut(false)
113{
114 if (numThreads > Impl::MaxThreads)
115 fatal("numThreads is not a valid value\n");
116
117 // Set fetch stage's status to inactive.
118 _status = Inactive;
119
120 std::string policy = params->smtFetchPolicy;
121
122 // Convert string to lowercase
123 std::transform(policy.begin(), policy.end(), policy.begin(),
124 (int(*)(int)) tolower);
125
126 // Figure out fetch policy
127 if (policy == "singlethread") {
128 fetchPolicy = SingleThread;
129 if (numThreads > 1)
130 panic("Invalid Fetch Policy for a SMT workload.");
131 } else if (policy == "roundrobin") {
132 fetchPolicy = RoundRobin;
133 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
134 } else if (policy == "branch") {
135 fetchPolicy = Branch;
136 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
137 } else if (policy == "iqcount") {
138 fetchPolicy = IQ;
139 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
140 } else if (policy == "lsqcount") {
141 fetchPolicy = LSQ;
142 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
143 } else {
144 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
145 " RoundRobin,LSQcount,IQcount}\n");
146 }
147
148 // Size of cache block.
149 cacheBlkSize = 64;
150
151 // Create mask to get rid of offset bits.
152 cacheBlkMask = (cacheBlkSize - 1);
153
154 for (int tid=0; tid < numThreads; tid++) {
155
156 fetchStatus[tid] = Running;
157
158 priorityList.push_back(tid);
159
160 memReq[tid] = NULL;
161
162 // Create space to store a cache line.
163 cacheData[tid] = new uint8_t[cacheBlkSize];
164 cacheDataPC[tid] = 0;
165 cacheDataValid[tid] = false;
166
167 delaySlotInfo[tid].branchSeqNum = -1;
168 delaySlotInfo[tid].numInsts = 0;
169 delaySlotInfo[tid].targetAddr = 0;
170 delaySlotInfo[tid].targetReady = false;
171
172 stalls[tid].decode = false;
173 stalls[tid].rename = false;
174 stalls[tid].iew = false;
175 stalls[tid].commit = false;
176 }
177
178 // Get the size of an instruction.
179 instSize = sizeof(TheISA::MachInst);
180}
181
182template <class Impl>
183std::string
184DefaultFetch<Impl>::name() const
185{
186 return cpu->name() + ".fetch";
187}
188
189template <class Impl>
190void
191DefaultFetch<Impl>::regStats()
192{
193 icacheStallCycles
194 .name(name() + ".icacheStallCycles")
195 .desc("Number of cycles fetch is stalled on an Icache miss")
196 .prereq(icacheStallCycles);
197
198 fetchedInsts
199 .name(name() + ".Insts")
200 .desc("Number of instructions fetch has processed")
201 .prereq(fetchedInsts);
202
203 fetchedBranches
204 .name(name() + ".Branches")
205 .desc("Number of branches that fetch encountered")
206 .prereq(fetchedBranches);
207
208 predictedBranches
209 .name(name() + ".predictedBranches")
210 .desc("Number of branches that fetch has predicted taken")
211 .prereq(predictedBranches);
212
213 fetchCycles
214 .name(name() + ".Cycles")
215 .desc("Number of cycles fetch has run and was not squashing or"
216 " blocked")
217 .prereq(fetchCycles);
218
219 fetchSquashCycles
220 .name(name() + ".SquashCycles")
221 .desc("Number of cycles fetch has spent squashing")
222 .prereq(fetchSquashCycles);
223
224 fetchIdleCycles
225 .name(name() + ".IdleCycles")
226 .desc("Number of cycles fetch was idle")
227 .prereq(fetchIdleCycles);
228
229 fetchBlockedCycles
230 .name(name() + ".BlockedCycles")
231 .desc("Number of cycles fetch has spent blocked")
232 .prereq(fetchBlockedCycles);
233
234 fetchedCacheLines
235 .name(name() + ".CacheLines")
236 .desc("Number of cache lines fetched")
237 .prereq(fetchedCacheLines);
238
239 fetchMiscStallCycles
240 .name(name() + ".MiscStallCycles")
241 .desc("Number of cycles fetch has spent waiting on interrupts, or "
242 "bad addresses, or out of MSHRs")
243 .prereq(fetchMiscStallCycles);
244
245 fetchIcacheSquashes
246 .name(name() + ".IcacheSquashes")
247 .desc("Number of outstanding Icache misses that were squashed")
248 .prereq(fetchIcacheSquashes);
249
250 fetchNisnDist
251 .init(/* base value */ 0,
252 /* last value */ fetchWidth,
253 /* bucket size */ 1)
254 .name(name() + ".rateDist")
255 .desc("Number of instructions fetched each cycle (Total)")
256 .flags(Stats::pdf);
257
258 idleRate
259 .name(name() + ".idleRate")
260 .desc("Percent of cycles fetch was idle")
261 .prereq(idleRate);
262 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
263
264 branchRate
265 .name(name() + ".branchRate")
266 .desc("Number of branch fetches per cycle")
267 .flags(Stats::total);
268 branchRate = fetchedBranches / cpu->numCycles;
269
270 fetchRate
271 .name(name() + ".rate")
272 .desc("Number of inst fetches per cycle")
273 .flags(Stats::total);
274 fetchRate = fetchedInsts / cpu->numCycles;
275
276 branchPred.regStats();
277}
278
279template<class Impl>
280void
281DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
282{
283 DPRINTF(Fetch, "Setting the CPU pointer.\n");
284 cpu = cpu_ptr;
285
286 // Name is finally available, so create the port.
287 icachePort = new IcachePort(this);
288
289#if USE_CHECKER
290 if (cpu->checker) {
291 cpu->checker->setIcachePort(icachePort);
292 }
293#endif
294
295 // Schedule fetch to get the correct PC from the CPU
296 // scheduleFetchStartupEvent(1);
297
298 // Fetch needs to start fetching instructions at the very beginning,
299 // so it must start up in active state.
300 switchToActive();
301}
302
303template<class Impl>
304void
305DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
306{
307 DPRINTF(Fetch, "Setting the time buffer pointer.\n");
308 timeBuffer = time_buffer;
309
310 // Create wires to get information from proper places in time buffer.
311 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
312 fromRename = timeBuffer->getWire(-renameToFetchDelay);
313 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
314 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
315}
316
317template<class Impl>
318void
319DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
320{
321 DPRINTF(Fetch, "Setting active threads list pointer.\n");
322 activeThreads = at_ptr;
323}
324
325template<class Impl>
326void
327DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
328{
329 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
330 fetchQueue = fq_ptr;
331
332 // Create wire to write information to proper place in fetch queue.
333 toDecode = fetchQueue->getWire(0);
334}
335
336template<class Impl>
337void
338DefaultFetch<Impl>::initStage()
339{
340 // Setup PC and nextPC with initial state.
341 for (int tid = 0; tid < numThreads; tid++) {
342 PC[tid] = cpu->readPC(tid);
343 nextPC[tid] = cpu->readNextPC(tid);
344#if ISA_HAS_DELAY_SLOT
345 nextNPC[tid] = cpu->readNextNPC(tid);
346#endif
347 }
348}
349
350template<class Impl>
351void
352DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
353{
354 unsigned tid = pkt->req->getThreadNum();
355
356 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
357
358 // Only change the status if it's still waiting on the icache access
359 // to return.
360 if (fetchStatus[tid] != IcacheWaitResponse ||
361 pkt->req != memReq[tid] ||
362 isSwitchedOut()) {
363 ++fetchIcacheSquashes;
364 delete pkt->req;
365 delete pkt;
366 return;
367 }
368
369 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
370 cacheDataValid[tid] = true;
371
372 if (!drainPending) {
373 // Wake up the CPU (if it went to sleep and was waiting on
374 // this completion event).
375 cpu->wakeCPU();
376
377 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
378 tid);
379
380 switchToActive();
381 }
382
383 // Only switch to IcacheAccessComplete if we're not stalled as well.
384 if (checkStall(tid)) {
385 fetchStatus[tid] = Blocked;
386 } else {
387 fetchStatus[tid] = IcacheAccessComplete;
388 }
389
390 // Reset the mem req to NULL.
391 delete pkt->req;
392 delete pkt;
393 memReq[tid] = NULL;
394}
395
396template <class Impl>
397bool
398DefaultFetch<Impl>::drain()
399{
400 // Fetch is ready to drain at any time.
401 cpu->signalDrained();
402 drainPending = true;
403 return true;
404}
405
406template <class Impl>
407void
408DefaultFetch<Impl>::resume()
409{
410 drainPending = false;
411}
412
413template <class Impl>
414void
415DefaultFetch<Impl>::switchOut()
416{
417 switchedOut = true;
418 // Branch predictor needs to have its state cleared.
419 branchPred.switchOut();
420}
421
422template <class Impl>
423void
424DefaultFetch<Impl>::takeOverFrom()
425{
426 // Reset all state
427 for (int i = 0; i < Impl::MaxThreads; ++i) {
428 stalls[i].decode = 0;
429 stalls[i].rename = 0;
430 stalls[i].iew = 0;
431 stalls[i].commit = 0;
432 PC[i] = cpu->readPC(i);
433 nextPC[i] = cpu->readNextPC(i);
434#if ISA_HAS_DELAY_SLOT
435 nextNPC[i] = cpu->readNextNPC(i);
436 delaySlotInfo[i].branchSeqNum = -1;
437 delaySlotInfo[i].numInsts = 0;
438 delaySlotInfo[i].targetAddr = 0;
439 delaySlotInfo[i].targetReady = false;
440#endif
441 fetchStatus[i] = Running;
442 }
443 numInst = 0;
444 wroteToTimeBuffer = false;
445 _status = Inactive;
446 switchedOut = false;
447 interruptPending = false;
448 branchPred.takeOverFrom();
449}
450
451template <class Impl>
452void
453DefaultFetch<Impl>::wakeFromQuiesce()
454{
455 DPRINTF(Fetch, "Waking up from quiesce\n");
456 // Hopefully this is safe
457 // @todo: Allow other threads to wake from quiesce.
458 fetchStatus[0] = Running;
459}
460
461template <class Impl>
462inline void
463DefaultFetch<Impl>::switchToActive()
464{
465 if (_status == Inactive) {
466 DPRINTF(Activity, "Activating stage.\n");
467
468 cpu->activateStage(O3CPU::FetchIdx);
469
470 _status = Active;
471 }
472}
473
474template <class Impl>
475inline void
476DefaultFetch<Impl>::switchToInactive()
477{
478 if (_status == Active) {
479 DPRINTF(Activity, "Deactivating stage.\n");
480
481 cpu->deactivateStage(O3CPU::FetchIdx);
482
483 _status = Inactive;
484 }
485}
486
487template <class Impl>
488bool
489DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
490 Addr &next_NPC)
491{
492 // Do branch prediction check here.
493 // A bit of a misnomer...next_PC is actually the current PC until
494 // this function updates it.
495 bool predict_taken;
496
497 if (!inst->isControl()) {
498#if ISA_HAS_DELAY_SLOT
499 Addr cur_PC = next_PC;
500 next_PC = cur_PC + instSize; //next_NPC;
501 next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
502 inst->setPredTarg(next_NPC);
503#else
504 next_PC = next_PC + instSize;
505 inst->setPredTarg(next_PC);
506#endif
507 return false;
508 }
509
510 int tid = inst->threadNumber;
511#if ISA_HAS_DELAY_SLOT
512 Addr pred_PC = next_PC;
513 predict_taken = branchPred.predict(inst, pred_PC, tid);
514
515 if (predict_taken) {
516 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
517 } else {
518 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
519 }
520
521 if (predict_taken) {
522 next_PC = next_NPC;
523 next_NPC = pred_PC;
524
525 // Update delay slot info
526 ++delaySlotInfo[tid].numInsts;
527 delaySlotInfo[tid].targetAddr = pred_PC;
528 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
529 delaySlotInfo[tid].numInsts);
530 } else { // !predict_taken
531 if (inst->isCondDelaySlot()) {
532 next_PC = pred_PC;
533 // The delay slot is skipped here if there is on
534 // prediction
535 } else {
536 next_PC = next_NPC;
537 // No need to declare a delay slot here since
538 // there is no for the pred. target to jump
539 }
540
541 next_NPC = next_NPC + instSize;
542 }
543#else
544 predict_taken = branchPred.predict(inst, next_PC, tid);
545#endif
546
547 ++fetchedBranches;
548
549 if (predict_taken) {
550 ++predictedBranches;
551 }
552
553 return predict_taken;
554}
555
556template <class Impl>
557bool
558DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
559{
560 Fault fault = NoFault;
561
562#if FULL_SYSTEM
563 // Flag to say whether or not address is physical addr.
564 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
565#else
566 unsigned flags = 0;
567#endif // FULL_SYSTEM
568
569 if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
570 // Hold off fetch from getting new instructions when:
571 // Cache is blocked, or
572 // while an interrupt is pending and we're not in PAL mode, or
573 // fetch is switched out.
574 return false;
575 }
576
577 // Align the fetch PC so it's at the start of a cache block.
578 fetch_PC = icacheBlockAlignPC(fetch_PC);
579
580 // If we've already got the block, no need to try to fetch it again.
581 if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
582 return true;
583 }
584
585 // Setup the memReq to do a read of the first instruction's address.
586 // Set the appropriate read size and flags as well.
587 // Build request here.
588 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
589 fetch_PC, cpu->readCpuId(), tid);
590
591 memReq[tid] = mem_req;
592
593 // Translate the instruction request.
594 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
595
596 // In the case of faults, the fetch stage may need to stall and wait
597 // for the ITB miss to be handled.
598
599 // If translation was successful, attempt to read the first
600 // instruction.
601 if (fault == NoFault) {
602#if 0
603 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
604 memReq[tid]->isUncacheable()) {
605 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
606 "misspeculating path)!",
607 memReq[tid]->paddr);
608 ret_fault = TheISA::genMachineCheckFault();
609 return false;
610 }
611#endif
612
613 // Build packet here.
614 PacketPtr data_pkt = new Packet(mem_req,
615 Packet::ReadReq, Packet::Broadcast);
616 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
617
618 cacheDataPC[tid] = fetch_PC;
619 cacheDataValid[tid] = false;
620
621 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
622
623 fetchedCacheLines++;
624
625 // Now do the timing access to see whether or not the instruction
626 // exists within the cache.
627 if (!icachePort->sendTiming(data_pkt)) {
628 if (data_pkt->result == Packet::BadAddress) {
629 fault = TheISA::genMachineCheckFault();
630 delete mem_req;
631 memReq[tid] = NULL;
632 }
633 assert(retryPkt == NULL);
634 assert(retryTid == -1);
635 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
636 fetchStatus[tid] = IcacheWaitRetry;
637 retryPkt = data_pkt;
638 retryTid = tid;
639 cacheBlocked = true;
640 return false;
641 }
642
643 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
644
645 lastIcacheStall[tid] = curTick;
646
647 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
648 "response.\n", tid);
649
650 fetchStatus[tid] = IcacheWaitResponse;
651 } else {
652 delete mem_req;
653 memReq[tid] = NULL;
654 }
655
656 ret_fault = fault;
657 return true;
658}
659
660template <class Impl>
661inline void
662DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
663{
664 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
665 tid, new_PC);
666
667 PC[tid] = new_PC;
668 nextPC[tid] = new_PC + instSize;
669 nextNPC[tid] = new_PC + (2 * instSize);
670
671 // Clear the icache miss if it's outstanding.
672 if (fetchStatus[tid] == IcacheWaitResponse) {
673 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
674 tid);
675 memReq[tid] = NULL;
676 }
677
678 // Get rid of the retrying packet if it was from this thread.
679 if (retryTid == tid) {
680 assert(cacheBlocked);
681 cacheBlocked = false;
682 retryTid = -1;
683 delete retryPkt->req;
684 delete retryPkt;
685 retryPkt = NULL;
686 }
687
688 fetchStatus[tid] = Squashing;
689
690 ++fetchSquashCycles;
691}
692
693template<class Impl>
694void
695DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
696 const InstSeqNum &seq_num,
697 unsigned tid)
698{
699 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
700
701 doSquash(new_PC, tid);
702
703#if ISA_HAS_DELAY_SLOT
704 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
705 delaySlotInfo[tid].numInsts = 0;
706 delaySlotInfo[tid].targetAddr = 0;
707 delaySlotInfo[tid].targetReady = false;
708 }
709#endif
710
711 // Tell the CPU to remove any instructions that are in flight between
712 // fetch and decode.
713 cpu->removeInstsUntil(seq_num, tid);
714}
715
716template<class Impl>
717bool
718DefaultFetch<Impl>::checkStall(unsigned tid) const
719{
720 bool ret_val = false;
721
722 if (cpu->contextSwitch) {
723 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
724 ret_val = true;
725 } else if (stalls[tid].decode) {
726 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
727 ret_val = true;
728 } else if (stalls[tid].rename) {
729 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
730 ret_val = true;
731 } else if (stalls[tid].iew) {
732 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
733 ret_val = true;
734 } else if (stalls[tid].commit) {
735 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
736 ret_val = true;
737 }
738
739 return ret_val;
740}
741
742template<class Impl>
743typename DefaultFetch<Impl>::FetchStatus
744DefaultFetch<Impl>::updateFetchStatus()
745{
746 //Check Running
747 std::list<unsigned>::iterator threads = (*activeThreads).begin();
748
749 while (threads != (*activeThreads).end()) {
750
751 unsigned tid = *threads++;
752
753 if (fetchStatus[tid] == Running ||
754 fetchStatus[tid] == Squashing ||
755 fetchStatus[tid] == IcacheAccessComplete) {
756
757 if (_status == Inactive) {
758 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
759
760 if (fetchStatus[tid] == IcacheAccessComplete) {
761 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
762 "completion\n",tid);
763 }
764
765 cpu->activateStage(O3CPU::FetchIdx);
766 }
767
768 return Active;
769 }
770 }
771
772 // Stage is switching from active to inactive, notify CPU of it.
773 if (_status == Active) {
774 DPRINTF(Activity, "Deactivating stage.\n");
775
776 cpu->deactivateStage(O3CPU::FetchIdx);
777 }
778
779 return Inactive;
780}
781
782template <class Impl>
783void
784DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
785 bool squash_delay_slot, unsigned tid)
786{
787 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
788
789 doSquash(new_PC, tid);
790
791#if ISA_HAS_DELAY_SLOT
792 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
793 delaySlotInfo[tid].numInsts = 0;
794 delaySlotInfo[tid].targetAddr = 0;
795 delaySlotInfo[tid].targetReady = false;
796 }
797
798 // Tell the CPU to remove any instructions that are not in the ROB.
799 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
800#else
801 // Tell the CPU to remove any instructions that are not in the ROB.
802 cpu->removeInstsNotInROB(tid, true, 0);
803#endif
804}
805
806template <class Impl>
807void
808DefaultFetch<Impl>::tick()
809{
810 std::list<unsigned>::iterator threads = (*activeThreads).begin();
811 bool status_change = false;
812
813 wroteToTimeBuffer = false;
814
815 while (threads != (*activeThreads).end()) {
816 unsigned tid = *threads++;
817
818 // Check the signals for each thread to determine the proper status
819 // for each thread.
820 bool updated_status = checkSignalsAndUpdate(tid);
821 status_change = status_change || updated_status;
822 }
823
824 DPRINTF(Fetch, "Running stage.\n");
825
826 // Reset the number of the instruction we're fetching.
827 numInst = 0;
828
829#if FULL_SYSTEM
830 if (fromCommit->commitInfo[0].interruptPending) {
831 interruptPending = true;
832 }
833
834 if (fromCommit->commitInfo[0].clearInterrupt) {
835 interruptPending = false;
836 }
837#endif
838
839 for (threadFetched = 0; threadFetched < numFetchingThreads;
840 threadFetched++) {
841 // Fetch each of the actively fetching threads.
842 fetch(status_change);
843 }
844
845 // Record number of instructions fetched this cycle for distribution.
846 fetchNisnDist.sample(numInst);
847
848 if (status_change) {
849 // Change the fetch stage status if there was a status change.
850 _status = updateFetchStatus();
851 }
852
853 // If there was activity this cycle, inform the CPU of it.
854 if (wroteToTimeBuffer || cpu->contextSwitch) {
855 DPRINTF(Activity, "Activity this cycle.\n");
856
857 cpu->activityThisCycle();
858 }
859}
860
861template <class Impl>
862bool
863DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
864{
865 // Update the per thread stall statuses.
866 if (fromDecode->decodeBlock[tid]) {
867 stalls[tid].decode = true;
868 }
869
870 if (fromDecode->decodeUnblock[tid]) {
871 assert(stalls[tid].decode);
872 assert(!fromDecode->decodeBlock[tid]);
873 stalls[tid].decode = false;
874 }
875
876 if (fromRename->renameBlock[tid]) {
877 stalls[tid].rename = true;
878 }
879
880 if (fromRename->renameUnblock[tid]) {
881 assert(stalls[tid].rename);
882 assert(!fromRename->renameBlock[tid]);
883 stalls[tid].rename = false;
884 }
885
886 if (fromIEW->iewBlock[tid]) {
887 stalls[tid].iew = true;
888 }
889
890 if (fromIEW->iewUnblock[tid]) {
891 assert(stalls[tid].iew);
892 assert(!fromIEW->iewBlock[tid]);
893 stalls[tid].iew = false;
894 }
895
896 if (fromCommit->commitBlock[tid]) {
897 stalls[tid].commit = true;
898 }
899
900 if (fromCommit->commitUnblock[tid]) {
901 assert(stalls[tid].commit);
902 assert(!fromCommit->commitBlock[tid]);
903 stalls[tid].commit = false;
904 }
905
906 // Check squash signals from commit.
907 if (fromCommit->commitInfo[tid].squash) {
908
909 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
910 "from commit.\n",tid);
911
912#if ISA_HAS_DELAY_SLOT
913 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
914#else
915 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
916#endif
917 // In any case, squash.
918 squash(fromCommit->commitInfo[tid].nextPC,
919 doneSeqNum,
920 fromCommit->commitInfo[tid].squashDelaySlot,
921 tid);
922
923 // Also check if there's a mispredict that happened.
924 if (fromCommit->commitInfo[tid].branchMispredict) {
925 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
926 fromCommit->commitInfo[tid].nextPC,
927 fromCommit->commitInfo[tid].branchTaken,
928 tid);
929 } else {
930 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
931 tid);
932 }
933
934 return true;
935 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
936 // Update the branch predictor if it wasn't a squashed instruction
937 // that was broadcasted.
938 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
939 }
940
941 // Check ROB squash signals from commit.
942 if (fromCommit->commitInfo[tid].robSquashing) {
943 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
944
945 // Continue to squash.
946 fetchStatus[tid] = Squashing;
947
948 return true;
949 }
950
951 // Check squash signals from decode.
952 if (fromDecode->decodeInfo[tid].squash) {
953 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
954 "from decode.\n",tid);
955
956 // Update the branch predictor.
957 if (fromDecode->decodeInfo[tid].branchMispredict) {
958 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
959 fromDecode->decodeInfo[tid].nextPC,
960 fromDecode->decodeInfo[tid].branchTaken,
961 tid);
962 } else {
963 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
964 tid);
965 }
966
967 if (fetchStatus[tid] != Squashing) {
968
969#if ISA_HAS_DELAY_SLOT
970 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
971#else
972 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
973#endif
974 // Squash unless we're already squashing
975 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
976 doneSeqNum,
977 tid);
978
979 return true;
980 }
981 }
982
983 if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
984 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
985
986 fetchStatus[tid] = Blocked;
987
988 return true;
989 }
990
991 if (fetchStatus[tid] == Blocked ||
992 fetchStatus[tid] == Squashing) {
993 // Switch status to running if fetch isn't being told to block or
994 // squash this cycle.
995 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
996 tid);
997
998 fetchStatus[tid] = Running;
999
1000 return true;
1001 }
1002
1003 // If we've reached this point, we have not gotten any signals that
1004 // cause fetch to change its status. Fetch remains the same as before.
1005 return false;
1006}
1007
1008template<class Impl>
1009void
1010DefaultFetch<Impl>::fetch(bool &status_change)
1011{
1012 //////////////////////////////////////////
1013 // Start actual fetch
1014 //////////////////////////////////////////
1015 int tid = getFetchingThread(fetchPolicy);
1016
1017 if (tid == -1 || drainPending) {
1018 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1019
1020 // Breaks looping condition in tick()
1021 threadFetched = numFetchingThreads;
1022 return;
1023 }
1024
1025 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1026
1027 // The current PC.
1028 Addr &fetch_PC = PC[tid];
1029
1030 // Fault code for memory access.
1031 Fault fault = NoFault;
1032
1033 // If returning from the delay of a cache miss, then update the status
1034 // to running, otherwise do the cache access. Possibly move this up
1035 // to tick() function.
1036 if (fetchStatus[tid] == IcacheAccessComplete) {
1037 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1038 tid);
1039
1040 fetchStatus[tid] = Running;
1041 status_change = true;
1042 } else if (fetchStatus[tid] == Running) {
1043 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1044 "instruction, starting at PC %08p.\n",
1045 tid, fetch_PC);
1046
1047 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1048 if (!fetch_success) {
1049 if (cacheBlocked) {
1050 ++icacheStallCycles;
1051 } else {
1052 ++fetchMiscStallCycles;
1053 }
1054 return;
1055 }
1056 } else {
1057 if (fetchStatus[tid] == Idle) {
1058 ++fetchIdleCycles;
1059 } else if (fetchStatus[tid] == Blocked) {
1060 ++fetchBlockedCycles;
1061 } else if (fetchStatus[tid] == Squashing) {
1062 ++fetchSquashCycles;
1063 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1064 ++icacheStallCycles;
1065 }
1066
1067 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1068 // fetch should do nothing.
1069 return;
1070 }
1071
1072 ++fetchCycles;
1073
1074 // If we had a stall due to an icache miss, then return.
1075 if (fetchStatus[tid] == IcacheWaitResponse) {
1076 ++icacheStallCycles;
1077 status_change = true;
1078 return;
1079 }
1080
1081 Addr next_PC = fetch_PC;
1082 Addr next_NPC = next_PC + instSize;
1083 InstSeqNum inst_seq;
1084 MachInst inst;
1085 ExtMachInst ext_inst;
1086 // @todo: Fix this hack.
1087 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1088
1089 if (fault == NoFault) {
1090 // If the read of the first instruction was successful, then grab the
1091 // instructions from the rest of the cache line and put them into the
1092 // queue heading to decode.
1093
1094 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1095 "decode.\n",tid);
1096
1097 // Need to keep track of whether or not a predicted branch
1098 // ended this fetch block.
1099 bool predicted_branch = false;
1100
1101 // Need to keep track of whether or not a delay slot
1102 // instruction has been fetched
1103
1104 for (;
1105 offset < cacheBlkSize &&
1106 numInst < fetchWidth &&
1107 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1108 ++numInst) {
1109
1110 // Get a sequence number.
1111 inst_seq = cpu->getAndIncrementInstSeq();
1112
1113 // Make sure this is a valid index.
1114 assert(offset <= cacheBlkSize - instSize);
1115
1116 // Get the instruction from the array of the cache line.
1117 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1118 (&cacheData[tid][offset]));
1119
1120 ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid));
1121
1122 // Create a new DynInst from the instruction fetched.
1123 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1124 next_PC,
1125 inst_seq, cpu);
1126 instruction->setTid(tid);
1127
1128 instruction->setASID(tid);
1129
1130 instruction->setThreadState(cpu->thread[tid]);
1131
1132 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1133 "[sn:%lli]\n",
1134 tid, instruction->readPC(), inst_seq);
1135
1136 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1137 tid, instruction->staticInst->disassemble(fetch_PC));
1138
1139 instruction->traceData =
1140 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1141 instruction->staticInst,
1142 instruction->readPC());
1143
1144 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1145 next_NPC);
1146
1147 // Add instruction to the CPU's list of instructions.
1148 instruction->setInstListIt(cpu->addInst(instruction));
1149
1150 // Write the instruction to the first slot in the queue
1151 // that heads to decode.
1152 toDecode->insts[numInst] = instruction;
1153
1154 toDecode->size++;
1155
1156 // Increment stat of fetched instructions.
1157 ++fetchedInsts;
1158
1159 // Move to the next instruction, unless we have a branch.
1160 fetch_PC = next_PC;
1161
1162 if (instruction->isQuiesce()) {
1163// warn("%lli: Quiesce instruction encountered, halting fetch!",
1164// curTick);
1165 fetchStatus[tid] = QuiescePending;
1166 ++numInst;
1167 status_change = true;
1168 break;
1169 }
1170
1171 offset += instSize;
1172
1173#if ISA_HAS_DELAY_SLOT
1174 if (predicted_branch) {
1175 delaySlotInfo[tid].branchSeqNum = inst_seq;
1176
1177 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1178 tid, inst_seq);
1179 continue;
1180 } else if (delaySlotInfo[tid].numInsts > 0) {
1181 --delaySlotInfo[tid].numInsts;
1182
1183 // It's OK to set PC to target of branch
1184 if (delaySlotInfo[tid].numInsts == 0) {
1185 delaySlotInfo[tid].targetReady = true;
1186
1187 // Break the looping condition
1188 predicted_branch = true;
1189 }
1190
1191 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1192 " process.\n", tid, delaySlotInfo[tid].numInsts);
1193 }
1194#endif
1195 }
1196
1197 if (offset >= cacheBlkSize) {
1198 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1199 "block.\n", tid);
1200 } else if (numInst >= fetchWidth) {
1201 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1202 "for this cycle.\n", tid);
1203 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1204 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1205 "instruction encountered.\n", tid);
1206 }
1207 }
1208
1209 if (numInst > 0) {
1210 wroteToTimeBuffer = true;
1211 }
1212
1213 // Now that fetching is completed, update the PC to signify what the next
1214 // cycle will be.
1215 if (fault == NoFault) {
1216#if ISA_HAS_DELAY_SLOT
1217 if (delaySlotInfo[tid].targetReady &&
1218 delaySlotInfo[tid].numInsts == 0) {
1219 // Set PC to target
1220 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1221 nextPC[tid] = next_PC + instSize; //next_NPC
1222 nextNPC[tid] = next_PC + (2 * instSize);
1223
1224 delaySlotInfo[tid].targetReady = false;
1225 } else {
1226 PC[tid] = next_PC;
1227 nextPC[tid] = next_NPC;
1228 nextNPC[tid] = next_NPC + instSize;
1229 }
1230
1231 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1232#else
1233 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1234 PC[tid] = next_PC;
1235 nextPC[tid] = next_PC + instSize;
1236#endif
1237 } else {
1238 // We shouldn't be in an icache miss and also have a fault (an ITB
1239 // miss)
1240 if (fetchStatus[tid] == IcacheWaitResponse) {
1241 panic("Fetch should have exited prior to this!");
1242 }
1243
1244 // Send the fault to commit. This thread will not do anything
1245 // until commit handles the fault. The only other way it can
1246 // wake up is if a squash comes along and changes the PC.
1247#if FULL_SYSTEM
1248 assert(numInst != fetchWidth);
1249 // Get a sequence number.
1250 inst_seq = cpu->getAndIncrementInstSeq();
1251 // We will use a nop in order to carry the fault.
1252 ext_inst = TheISA::NoopMachInst;
1253
1254 // Create a new DynInst from the dummy nop.
1255 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1256 next_PC,
1257 inst_seq, cpu);
1258 instruction->setPredTarg(next_PC + instSize);
1259 instruction->setTid(tid);
1260
1261 instruction->setASID(tid);
1262
1263 instruction->setThreadState(cpu->thread[tid]);
1264
1265 instruction->traceData = NULL;
1266
1267 instruction->setInstListIt(cpu->addInst(instruction));
1268
1269 instruction->fault = fault;
1270
1271 toDecode->insts[numInst] = instruction;
1272 toDecode->size++;
1273
1274 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1275
1276 fetchStatus[tid] = TrapPending;
1277 status_change = true;
1278
1279// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1280#else // !FULL_SYSTEM
1281 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1282#endif // FULL_SYSTEM
1283 }
1284}
1285
1286template<class Impl>
1287void
1288DefaultFetch<Impl>::recvRetry()
1289{
1290 if (retryPkt != NULL) {
1291 assert(cacheBlocked);
1292 assert(retryTid != -1);
1293 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1294
1295 if (icachePort->sendTiming(retryPkt)) {
1296 fetchStatus[retryTid] = IcacheWaitResponse;
1297 retryPkt = NULL;
1298 retryTid = -1;
1299 cacheBlocked = false;
1300 }
1301 } else {
1302 assert(retryTid == -1);
1303 // Access has been squashed since it was sent out. Just clear
1304 // the cache being blocked.
1305 cacheBlocked = false;
1306 }
1307}
1308
1309///////////////////////////////////////
1310// //
1311// SMT FETCH POLICY MAINTAINED HERE //
1312// //
1313///////////////////////////////////////
1314template<class Impl>
1315int
1316DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1317{
1318 if (numThreads > 1) {
1319 switch (fetch_priority) {
1320
1321 case SingleThread:
1322 return 0;
1323
1324 case RoundRobin:
1325 return roundRobin();
1326
1327 case IQ:
1328 return iqCount();
1329
1330 case LSQ:
1331 return lsqCount();
1332
1333 case Branch:
1334 return branchCount();
1335
1336 default:
1337 return -1;
1338 }
1339 } else {
1340 int tid = *((*activeThreads).begin());
1341
1342 if (fetchStatus[tid] == Running ||
1343 fetchStatus[tid] == IcacheAccessComplete ||
1344 fetchStatus[tid] == Idle) {
1345 return tid;
1346 } else {
1347 return -1;
1348 }
1349 }
1350
1351}
1352
1353
1354template<class Impl>
1355int
1356DefaultFetch<Impl>::roundRobin()
1357{
1358 std::list<unsigned>::iterator pri_iter = priorityList.begin();
1359 std::list<unsigned>::iterator end = priorityList.end();
1360
1361 int high_pri;
1362
1363 while (pri_iter != end) {
1364 high_pri = *pri_iter;
1365
1366 assert(high_pri <= numThreads);
1367
1368 if (fetchStatus[high_pri] == Running ||
1369 fetchStatus[high_pri] == IcacheAccessComplete ||
1370 fetchStatus[high_pri] == Idle) {
1371
1372 priorityList.erase(pri_iter);
1373 priorityList.push_back(high_pri);
1374
1375 return high_pri;
1376 }
1377
1378 pri_iter++;
1379 }
1380
1381 return -1;
1382}
1383
1384template<class Impl>
1385int
1386DefaultFetch<Impl>::iqCount()
1387{
1388 std::priority_queue<unsigned> PQ;
1389
1390 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1391
1392 while (threads != (*activeThreads).end()) {
1393 unsigned tid = *threads++;
1394
1395 PQ.push(fromIEW->iewInfo[tid].iqCount);
1396 }
1397
1398 while (!PQ.empty()) {
1399
1400 unsigned high_pri = PQ.top();
1401
1402 if (fetchStatus[high_pri] == Running ||
1403 fetchStatus[high_pri] == IcacheAccessComplete ||
1404 fetchStatus[high_pri] == Idle)
1405 return high_pri;
1406 else
1407 PQ.pop();
1408
1409 }
1410
1411 return -1;
1412}
1413
1414template<class Impl>
1415int
1416DefaultFetch<Impl>::lsqCount()
1417{
1418 std::priority_queue<unsigned> PQ;
1419
1420
1421 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1422
1423 while (threads != (*activeThreads).end()) {
1424 unsigned tid = *threads++;
1425
1426 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1427 }
1428
1429 while (!PQ.empty()) {
1430
1431 unsigned high_pri = PQ.top();
1432
1433 if (fetchStatus[high_pri] == Running ||
1434 fetchStatus[high_pri] == IcacheAccessComplete ||
1435 fetchStatus[high_pri] == Idle)
1436 return high_pri;
1437 else
1438 PQ.pop();
1439
1440 }
1441
1442 return -1;
1443}
1444
1445template<class Impl>
1446int
1447DefaultFetch<Impl>::branchCount()
1448{
1449 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1450 panic("Branch Count Fetch policy unimplemented\n");
1451 return *threads;
1452}
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