84 return true;
85}
86
87template<class Impl>
88void
89DefaultFetch<Impl>::IcachePort::recvRetry()
90{
91 fetch->recvRetry();
92}
93
94template<class Impl>
95DefaultFetch<Impl>::DefaultFetch(Params *params)
96 : mem(params->mem),
97 branchPred(params),
98 decodeToFetchDelay(params->decodeToFetchDelay),
99 renameToFetchDelay(params->renameToFetchDelay),
100 iewToFetchDelay(params->iewToFetchDelay),
101 commitToFetchDelay(params->commitToFetchDelay),
102 fetchWidth(params->fetchWidth),
103 cacheBlocked(false),
104 retryPkt(NULL),
105 retryTid(-1),
106 numThreads(params->numberOfThreads),
107 numFetchingThreads(params->smtNumFetchingThreads),
108 interruptPending(false),
109 drainPending(false),
110 switchedOut(false)
111{
112 if (numThreads > Impl::MaxThreads)
113 fatal("numThreads is not a valid value\n");
114
115 // Set fetch stage's status to inactive.
116 _status = Inactive;
117
118 std::string policy = params->smtFetchPolicy;
119
120 // Convert string to lowercase
121 std::transform(policy.begin(), policy.end(), policy.begin(),
122 (int(*)(int)) tolower);
123
124 // Figure out fetch policy
125 if (policy == "singlethread") {
126 fetchPolicy = SingleThread;
127 if (numThreads > 1)
128 panic("Invalid Fetch Policy for a SMT workload.");
129 } else if (policy == "roundrobin") {
130 fetchPolicy = RoundRobin;
131 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
132 } else if (policy == "branch") {
133 fetchPolicy = Branch;
134 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
135 } else if (policy == "iqcount") {
136 fetchPolicy = IQ;
137 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
138 } else if (policy == "lsqcount") {
139 fetchPolicy = LSQ;
140 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
141 } else {
142 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
143 " RoundRobin,LSQcount,IQcount}\n");
144 }
145
146 // Size of cache block.
147 cacheBlkSize = 64;
148
149 // Create mask to get rid of offset bits.
150 cacheBlkMask = (cacheBlkSize - 1);
151
152 for (int tid=0; tid < numThreads; tid++) {
153
154 fetchStatus[tid] = Running;
155
156 priorityList.push_back(tid);
157
158 memReq[tid] = NULL;
159
160 // Create space to store a cache line.
161 cacheData[tid] = new uint8_t[cacheBlkSize];
162 cacheDataPC[tid] = 0;
163 cacheDataValid[tid] = false;
164
165 delaySlotInfo[tid].branchSeqNum = -1;
166 delaySlotInfo[tid].numInsts = 0;
167 delaySlotInfo[tid].targetAddr = 0;
168 delaySlotInfo[tid].targetReady = false;
169
170 stalls[tid].decode = false;
171 stalls[tid].rename = false;
172 stalls[tid].iew = false;
173 stalls[tid].commit = false;
174 }
175
176 // Get the size of an instruction.
177 instSize = sizeof(TheISA::MachInst);
178}
179
180template <class Impl>
181std::string
182DefaultFetch<Impl>::name() const
183{
184 return cpu->name() + ".fetch";
185}
186
187template <class Impl>
188void
189DefaultFetch<Impl>::regStats()
190{
191 icacheStallCycles
192 .name(name() + ".icacheStallCycles")
193 .desc("Number of cycles fetch is stalled on an Icache miss")
194 .prereq(icacheStallCycles);
195
196 fetchedInsts
197 .name(name() + ".Insts")
198 .desc("Number of instructions fetch has processed")
199 .prereq(fetchedInsts);
200
201 fetchedBranches
202 .name(name() + ".Branches")
203 .desc("Number of branches that fetch encountered")
204 .prereq(fetchedBranches);
205
206 predictedBranches
207 .name(name() + ".predictedBranches")
208 .desc("Number of branches that fetch has predicted taken")
209 .prereq(predictedBranches);
210
211 fetchCycles
212 .name(name() + ".Cycles")
213 .desc("Number of cycles fetch has run and was not squashing or"
214 " blocked")
215 .prereq(fetchCycles);
216
217 fetchSquashCycles
218 .name(name() + ".SquashCycles")
219 .desc("Number of cycles fetch has spent squashing")
220 .prereq(fetchSquashCycles);
221
222 fetchIdleCycles
223 .name(name() + ".IdleCycles")
224 .desc("Number of cycles fetch was idle")
225 .prereq(fetchIdleCycles);
226
227 fetchBlockedCycles
228 .name(name() + ".BlockedCycles")
229 .desc("Number of cycles fetch has spent blocked")
230 .prereq(fetchBlockedCycles);
231
232 fetchedCacheLines
233 .name(name() + ".CacheLines")
234 .desc("Number of cache lines fetched")
235 .prereq(fetchedCacheLines);
236
237 fetchMiscStallCycles
238 .name(name() + ".MiscStallCycles")
239 .desc("Number of cycles fetch has spent waiting on interrupts, or "
240 "bad addresses, or out of MSHRs")
241 .prereq(fetchMiscStallCycles);
242
243 fetchIcacheSquashes
244 .name(name() + ".IcacheSquashes")
245 .desc("Number of outstanding Icache misses that were squashed")
246 .prereq(fetchIcacheSquashes);
247
248 fetchNisnDist
249 .init(/* base value */ 0,
250 /* last value */ fetchWidth,
251 /* bucket size */ 1)
252 .name(name() + ".rateDist")
253 .desc("Number of instructions fetched each cycle (Total)")
254 .flags(Stats::pdf);
255
256 idleRate
257 .name(name() + ".idleRate")
258 .desc("Percent of cycles fetch was idle")
259 .prereq(idleRate);
260 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
261
262 branchRate
263 .name(name() + ".branchRate")
264 .desc("Number of branch fetches per cycle")
265 .flags(Stats::total);
266 branchRate = fetchedBranches / cpu->numCycles;
267
268 fetchRate
269 .name(name() + ".rate")
270 .desc("Number of inst fetches per cycle")
271 .flags(Stats::total);
272 fetchRate = fetchedInsts / cpu->numCycles;
273
274 branchPred.regStats();
275}
276
277template<class Impl>
278void
279DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
280{
281 DPRINTF(Fetch, "Setting the CPU pointer.\n");
282 cpu = cpu_ptr;
283
284 // Name is finally available, so create the port.
285 icachePort = new IcachePort(this);
286
287#if USE_CHECKER
288 if (cpu->checker) {
289 cpu->checker->setIcachePort(icachePort);
290 }
291#endif
292
293 // Schedule fetch to get the correct PC from the CPU
294 // scheduleFetchStartupEvent(1);
295
296 // Fetch needs to start fetching instructions at the very beginning,
297 // so it must start up in active state.
298 switchToActive();
299}
300
301template<class Impl>
302void
303DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
304{
305 DPRINTF(Fetch, "Setting the time buffer pointer.\n");
306 timeBuffer = time_buffer;
307
308 // Create wires to get information from proper places in time buffer.
309 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
310 fromRename = timeBuffer->getWire(-renameToFetchDelay);
311 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
312 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
313}
314
315template<class Impl>
316void
317DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
318{
319 DPRINTF(Fetch, "Setting active threads list pointer.\n");
320 activeThreads = at_ptr;
321}
322
323template<class Impl>
324void
325DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
326{
327 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
328 fetchQueue = fq_ptr;
329
330 // Create wire to write information to proper place in fetch queue.
331 toDecode = fetchQueue->getWire(0);
332}
333
334template<class Impl>
335void
336DefaultFetch<Impl>::initStage()
337{
338 // Setup PC and nextPC with initial state.
339 for (int tid = 0; tid < numThreads; tid++) {
340 PC[tid] = cpu->readPC(tid);
341 nextPC[tid] = cpu->readNextPC(tid);
342#if ISA_HAS_DELAY_SLOT
343 nextNPC[tid] = cpu->readNextNPC(tid);
344#endif
345 }
346}
347
348template<class Impl>
349void
350DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
351{
352 unsigned tid = pkt->req->getThreadNum();
353
354 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
355
356 // Only change the status if it's still waiting on the icache access
357 // to return.
358 if (fetchStatus[tid] != IcacheWaitResponse ||
359 pkt->req != memReq[tid] ||
360 isSwitchedOut()) {
361 ++fetchIcacheSquashes;
362 delete pkt->req;
363 delete pkt;
364 return;
365 }
366
367 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
368 cacheDataValid[tid] = true;
369
370 if (!drainPending) {
371 // Wake up the CPU (if it went to sleep and was waiting on
372 // this completion event).
373 cpu->wakeCPU();
374
375 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
376 tid);
377
378 switchToActive();
379 }
380
381 // Only switch to IcacheAccessComplete if we're not stalled as well.
382 if (checkStall(tid)) {
383 fetchStatus[tid] = Blocked;
384 } else {
385 fetchStatus[tid] = IcacheAccessComplete;
386 }
387
388 // Reset the mem req to NULL.
389 delete pkt->req;
390 delete pkt;
391 memReq[tid] = NULL;
392}
393
394template <class Impl>
395bool
396DefaultFetch<Impl>::drain()
397{
398 // Fetch is ready to drain at any time.
399 cpu->signalDrained();
400 drainPending = true;
401 return true;
402}
403
404template <class Impl>
405void
406DefaultFetch<Impl>::resume()
407{
408 drainPending = false;
409}
410
411template <class Impl>
412void
413DefaultFetch<Impl>::switchOut()
414{
415 switchedOut = true;
416 // Branch predictor needs to have its state cleared.
417 branchPred.switchOut();
418}
419
420template <class Impl>
421void
422DefaultFetch<Impl>::takeOverFrom()
423{
424 // Reset all state
425 for (int i = 0; i < Impl::MaxThreads; ++i) {
426 stalls[i].decode = 0;
427 stalls[i].rename = 0;
428 stalls[i].iew = 0;
429 stalls[i].commit = 0;
430 PC[i] = cpu->readPC(i);
431 nextPC[i] = cpu->readNextPC(i);
432#if ISA_HAS_DELAY_SLOT
433 nextNPC[i] = cpu->readNextNPC(i);
434 delaySlotInfo[i].branchSeqNum = -1;
435 delaySlotInfo[i].numInsts = 0;
436 delaySlotInfo[i].targetAddr = 0;
437 delaySlotInfo[i].targetReady = false;
438#endif
439 fetchStatus[i] = Running;
440 }
441 numInst = 0;
442 wroteToTimeBuffer = false;
443 _status = Inactive;
444 switchedOut = false;
445 interruptPending = false;
446 branchPred.takeOverFrom();
447}
448
449template <class Impl>
450void
451DefaultFetch<Impl>::wakeFromQuiesce()
452{
453 DPRINTF(Fetch, "Waking up from quiesce\n");
454 // Hopefully this is safe
455 // @todo: Allow other threads to wake from quiesce.
456 fetchStatus[0] = Running;
457}
458
459template <class Impl>
460inline void
461DefaultFetch<Impl>::switchToActive()
462{
463 if (_status == Inactive) {
464 DPRINTF(Activity, "Activating stage.\n");
465
466 cpu->activateStage(O3CPU::FetchIdx);
467
468 _status = Active;
469 }
470}
471
472template <class Impl>
473inline void
474DefaultFetch<Impl>::switchToInactive()
475{
476 if (_status == Active) {
477 DPRINTF(Activity, "Deactivating stage.\n");
478
479 cpu->deactivateStage(O3CPU::FetchIdx);
480
481 _status = Inactive;
482 }
483}
484
485template <class Impl>
486bool
487DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
488 Addr &next_NPC)
489{
490 // Do branch prediction check here.
491 // A bit of a misnomer...next_PC is actually the current PC until
492 // this function updates it.
493 bool predict_taken;
494
495 if (!inst->isControl()) {
496#if ISA_HAS_DELAY_SLOT
497 Addr cur_PC = next_PC;
498 next_PC = cur_PC + instSize; //next_NPC;
499 next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
500 inst->setPredTarg(next_NPC);
501#else
502 next_PC = next_PC + instSize;
503 inst->setPredTarg(next_PC);
504#endif
505 return false;
506 }
507
508 int tid = inst->threadNumber;
509#if ISA_HAS_DELAY_SLOT
510 Addr pred_PC = next_PC;
511 predict_taken = branchPred.predict(inst, pred_PC, tid);
512
513 if (predict_taken) {
514 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
515 } else {
516 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
517 }
518
519 if (predict_taken) {
520 next_PC = next_NPC;
521 next_NPC = pred_PC;
522
523 // Update delay slot info
524 ++delaySlotInfo[tid].numInsts;
525 delaySlotInfo[tid].targetAddr = pred_PC;
526 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
527 delaySlotInfo[tid].numInsts);
528 } else { // !predict_taken
529 if (inst->isCondDelaySlot()) {
530 next_PC = pred_PC;
531 // The delay slot is skipped here if there is on
532 // prediction
533 } else {
534 next_PC = next_NPC;
535 // No need to declare a delay slot here since
536 // there is no for the pred. target to jump
537 }
538
539 next_NPC = next_NPC + instSize;
540 }
541#else
542 predict_taken = branchPred.predict(inst, next_PC, tid);
543#endif
544
545 ++fetchedBranches;
546
547 if (predict_taken) {
548 ++predictedBranches;
549 }
550
551 return predict_taken;
552}
553
554template <class Impl>
555bool
556DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
557{
558 Fault fault = NoFault;
559
560#if FULL_SYSTEM
561 // Flag to say whether or not address is physical addr.
562 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
563#else
564 unsigned flags = 0;
565#endif // FULL_SYSTEM
566
567 if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
568 // Hold off fetch from getting new instructions when:
569 // Cache is blocked, or
570 // while an interrupt is pending and we're not in PAL mode, or
571 // fetch is switched out.
572 return false;
573 }
574
575 // Align the fetch PC so it's at the start of a cache block.
576 fetch_PC = icacheBlockAlignPC(fetch_PC);
577
578 // If we've already got the block, no need to try to fetch it again.
579 if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
580 return true;
581 }
582
583 // Setup the memReq to do a read of the first instruction's address.
584 // Set the appropriate read size and flags as well.
585 // Build request here.
586 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
587 fetch_PC, cpu->readCpuId(), tid);
588
589 memReq[tid] = mem_req;
590
591 // Translate the instruction request.
592 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
593
594 // In the case of faults, the fetch stage may need to stall and wait
595 // for the ITB miss to be handled.
596
597 // If translation was successful, attempt to read the first
598 // instruction.
599 if (fault == NoFault) {
600#if 0
601 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
602 memReq[tid]->isUncacheable()) {
603 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
604 "misspeculating path)!",
605 memReq[tid]->paddr);
606 ret_fault = TheISA::genMachineCheckFault();
607 return false;
608 }
609#endif
610
611 // Build packet here.
612 PacketPtr data_pkt = new Packet(mem_req,
613 Packet::ReadReq, Packet::Broadcast);
614 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
615
616 cacheDataPC[tid] = fetch_PC;
617 cacheDataValid[tid] = false;
618
619 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
620
621 fetchedCacheLines++;
622
623 // Now do the timing access to see whether or not the instruction
624 // exists within the cache.
625 if (!icachePort->sendTiming(data_pkt)) {
626 if (data_pkt->result == Packet::BadAddress) {
627 fault = TheISA::genMachineCheckFault();
628 delete mem_req;
629 memReq[tid] = NULL;
630 }
631 assert(retryPkt == NULL);
632 assert(retryTid == -1);
633 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
634 fetchStatus[tid] = IcacheWaitRetry;
635 retryPkt = data_pkt;
636 retryTid = tid;
637 cacheBlocked = true;
638 return false;
639 }
640
641 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
642
643 lastIcacheStall[tid] = curTick;
644
645 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
646 "response.\n", tid);
647
648 fetchStatus[tid] = IcacheWaitResponse;
649 } else {
650 delete mem_req;
651 memReq[tid] = NULL;
652 }
653
654 ret_fault = fault;
655 return true;
656}
657
658template <class Impl>
659inline void
660DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
661{
662 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
663 tid, new_PC);
664
665 PC[tid] = new_PC;
666 nextPC[tid] = new_PC + instSize;
667 nextNPC[tid] = new_PC + (2 * instSize);
668
669 // Clear the icache miss if it's outstanding.
670 if (fetchStatus[tid] == IcacheWaitResponse) {
671 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
672 tid);
673 memReq[tid] = NULL;
674 }
675
676 // Get rid of the retrying packet if it was from this thread.
677 if (retryTid == tid) {
678 assert(cacheBlocked);
679 cacheBlocked = false;
680 retryTid = -1;
681 delete retryPkt->req;
682 delete retryPkt;
683 retryPkt = NULL;
684 }
685
686 fetchStatus[tid] = Squashing;
687
688 ++fetchSquashCycles;
689}
690
691template<class Impl>
692void
693DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
694 const InstSeqNum &seq_num,
695 unsigned tid)
696{
697 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
698
699 doSquash(new_PC, tid);
700
701#if ISA_HAS_DELAY_SLOT
702 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
703 delaySlotInfo[tid].numInsts = 0;
704 delaySlotInfo[tid].targetAddr = 0;
705 delaySlotInfo[tid].targetReady = false;
706 }
707#endif
708
709 // Tell the CPU to remove any instructions that are in flight between
710 // fetch and decode.
711 cpu->removeInstsUntil(seq_num, tid);
712}
713
714template<class Impl>
715bool
716DefaultFetch<Impl>::checkStall(unsigned tid) const
717{
718 bool ret_val = false;
719
720 if (cpu->contextSwitch) {
721 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
722 ret_val = true;
723 } else if (stalls[tid].decode) {
724 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
725 ret_val = true;
726 } else if (stalls[tid].rename) {
727 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
728 ret_val = true;
729 } else if (stalls[tid].iew) {
730 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
731 ret_val = true;
732 } else if (stalls[tid].commit) {
733 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
734 ret_val = true;
735 }
736
737 return ret_val;
738}
739
740template<class Impl>
741typename DefaultFetch<Impl>::FetchStatus
742DefaultFetch<Impl>::updateFetchStatus()
743{
744 //Check Running
745 std::list<unsigned>::iterator threads = (*activeThreads).begin();
746
747 while (threads != (*activeThreads).end()) {
748
749 unsigned tid = *threads++;
750
751 if (fetchStatus[tid] == Running ||
752 fetchStatus[tid] == Squashing ||
753 fetchStatus[tid] == IcacheAccessComplete) {
754
755 if (_status == Inactive) {
756 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
757
758 if (fetchStatus[tid] == IcacheAccessComplete) {
759 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
760 "completion\n",tid);
761 }
762
763 cpu->activateStage(O3CPU::FetchIdx);
764 }
765
766 return Active;
767 }
768 }
769
770 // Stage is switching from active to inactive, notify CPU of it.
771 if (_status == Active) {
772 DPRINTF(Activity, "Deactivating stage.\n");
773
774 cpu->deactivateStage(O3CPU::FetchIdx);
775 }
776
777 return Inactive;
778}
779
780template <class Impl>
781void
782DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
783 bool squash_delay_slot, unsigned tid)
784{
785 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
786
787 doSquash(new_PC, tid);
788
789#if ISA_HAS_DELAY_SLOT
790 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
791 delaySlotInfo[tid].numInsts = 0;
792 delaySlotInfo[tid].targetAddr = 0;
793 delaySlotInfo[tid].targetReady = false;
794 }
795
796 // Tell the CPU to remove any instructions that are not in the ROB.
797 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
798#else
799 // Tell the CPU to remove any instructions that are not in the ROB.
800 cpu->removeInstsNotInROB(tid, true, 0);
801#endif
802}
803
804template <class Impl>
805void
806DefaultFetch<Impl>::tick()
807{
808 std::list<unsigned>::iterator threads = (*activeThreads).begin();
809 bool status_change = false;
810
811 wroteToTimeBuffer = false;
812
813 while (threads != (*activeThreads).end()) {
814 unsigned tid = *threads++;
815
816 // Check the signals for each thread to determine the proper status
817 // for each thread.
818 bool updated_status = checkSignalsAndUpdate(tid);
819 status_change = status_change || updated_status;
820 }
821
822 DPRINTF(Fetch, "Running stage.\n");
823
824 // Reset the number of the instruction we're fetching.
825 numInst = 0;
826
827#if FULL_SYSTEM
828 if (fromCommit->commitInfo[0].interruptPending) {
829 interruptPending = true;
830 }
831
832 if (fromCommit->commitInfo[0].clearInterrupt) {
833 interruptPending = false;
834 }
835#endif
836
837 for (threadFetched = 0; threadFetched < numFetchingThreads;
838 threadFetched++) {
839 // Fetch each of the actively fetching threads.
840 fetch(status_change);
841 }
842
843 // Record number of instructions fetched this cycle for distribution.
844 fetchNisnDist.sample(numInst);
845
846 if (status_change) {
847 // Change the fetch stage status if there was a status change.
848 _status = updateFetchStatus();
849 }
850
851 // If there was activity this cycle, inform the CPU of it.
852 if (wroteToTimeBuffer || cpu->contextSwitch) {
853 DPRINTF(Activity, "Activity this cycle.\n");
854
855 cpu->activityThisCycle();
856 }
857}
858
859template <class Impl>
860bool
861DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
862{
863 // Update the per thread stall statuses.
864 if (fromDecode->decodeBlock[tid]) {
865 stalls[tid].decode = true;
866 }
867
868 if (fromDecode->decodeUnblock[tid]) {
869 assert(stalls[tid].decode);
870 assert(!fromDecode->decodeBlock[tid]);
871 stalls[tid].decode = false;
872 }
873
874 if (fromRename->renameBlock[tid]) {
875 stalls[tid].rename = true;
876 }
877
878 if (fromRename->renameUnblock[tid]) {
879 assert(stalls[tid].rename);
880 assert(!fromRename->renameBlock[tid]);
881 stalls[tid].rename = false;
882 }
883
884 if (fromIEW->iewBlock[tid]) {
885 stalls[tid].iew = true;
886 }
887
888 if (fromIEW->iewUnblock[tid]) {
889 assert(stalls[tid].iew);
890 assert(!fromIEW->iewBlock[tid]);
891 stalls[tid].iew = false;
892 }
893
894 if (fromCommit->commitBlock[tid]) {
895 stalls[tid].commit = true;
896 }
897
898 if (fromCommit->commitUnblock[tid]) {
899 assert(stalls[tid].commit);
900 assert(!fromCommit->commitBlock[tid]);
901 stalls[tid].commit = false;
902 }
903
904 // Check squash signals from commit.
905 if (fromCommit->commitInfo[tid].squash) {
906
907 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
908 "from commit.\n",tid);
909
910#if ISA_HAS_DELAY_SLOT
911 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
912#else
913 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
914#endif
915 // In any case, squash.
916 squash(fromCommit->commitInfo[tid].nextPC,
917 doneSeqNum,
918 fromCommit->commitInfo[tid].squashDelaySlot,
919 tid);
920
921 // Also check if there's a mispredict that happened.
922 if (fromCommit->commitInfo[tid].branchMispredict) {
923 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
924 fromCommit->commitInfo[tid].nextPC,
925 fromCommit->commitInfo[tid].branchTaken,
926 tid);
927 } else {
928 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
929 tid);
930 }
931
932 return true;
933 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
934 // Update the branch predictor if it wasn't a squashed instruction
935 // that was broadcasted.
936 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
937 }
938
939 // Check ROB squash signals from commit.
940 if (fromCommit->commitInfo[tid].robSquashing) {
941 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
942
943 // Continue to squash.
944 fetchStatus[tid] = Squashing;
945
946 return true;
947 }
948
949 // Check squash signals from decode.
950 if (fromDecode->decodeInfo[tid].squash) {
951 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
952 "from decode.\n",tid);
953
954 // Update the branch predictor.
955 if (fromDecode->decodeInfo[tid].branchMispredict) {
956 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
957 fromDecode->decodeInfo[tid].nextPC,
958 fromDecode->decodeInfo[tid].branchTaken,
959 tid);
960 } else {
961 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
962 tid);
963 }
964
965 if (fetchStatus[tid] != Squashing) {
966
967#if ISA_HAS_DELAY_SLOT
968 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
969#else
970 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
971#endif
972 // Squash unless we're already squashing
973 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
974 doneSeqNum,
975 tid);
976
977 return true;
978 }
979 }
980
981 if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
982 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
983
984 fetchStatus[tid] = Blocked;
985
986 return true;
987 }
988
989 if (fetchStatus[tid] == Blocked ||
990 fetchStatus[tid] == Squashing) {
991 // Switch status to running if fetch isn't being told to block or
992 // squash this cycle.
993 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
994 tid);
995
996 fetchStatus[tid] = Running;
997
998 return true;
999 }
1000
1001 // If we've reached this point, we have not gotten any signals that
1002 // cause fetch to change its status. Fetch remains the same as before.
1003 return false;
1004}
1005
1006template<class Impl>
1007void
1008DefaultFetch<Impl>::fetch(bool &status_change)
1009{
1010 //////////////////////////////////////////
1011 // Start actual fetch
1012 //////////////////////////////////////////
1013 int tid = getFetchingThread(fetchPolicy);
1014
1015 if (tid == -1 || drainPending) {
1016 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1017
1018 // Breaks looping condition in tick()
1019 threadFetched = numFetchingThreads;
1020 return;
1021 }
1022
1023 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1024
1025 // The current PC.
1026 Addr &fetch_PC = PC[tid];
1027
1028 // Fault code for memory access.
1029 Fault fault = NoFault;
1030
1031 // If returning from the delay of a cache miss, then update the status
1032 // to running, otherwise do the cache access. Possibly move this up
1033 // to tick() function.
1034 if (fetchStatus[tid] == IcacheAccessComplete) {
1035 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1036 tid);
1037
1038 fetchStatus[tid] = Running;
1039 status_change = true;
1040 } else if (fetchStatus[tid] == Running) {
1041 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1042 "instruction, starting at PC %08p.\n",
1043 tid, fetch_PC);
1044
1045 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1046 if (!fetch_success) {
1047 if (cacheBlocked) {
1048 ++icacheStallCycles;
1049 } else {
1050 ++fetchMiscStallCycles;
1051 }
1052 return;
1053 }
1054 } else {
1055 if (fetchStatus[tid] == Idle) {
1056 ++fetchIdleCycles;
1057 } else if (fetchStatus[tid] == Blocked) {
1058 ++fetchBlockedCycles;
1059 } else if (fetchStatus[tid] == Squashing) {
1060 ++fetchSquashCycles;
1061 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1062 ++icacheStallCycles;
1063 }
1064
1065 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1066 // fetch should do nothing.
1067 return;
1068 }
1069
1070 ++fetchCycles;
1071
1072 // If we had a stall due to an icache miss, then return.
1073 if (fetchStatus[tid] == IcacheWaitResponse) {
1074 ++icacheStallCycles;
1075 status_change = true;
1076 return;
1077 }
1078
1079 Addr next_PC = fetch_PC;
1080 Addr next_NPC = next_PC + instSize;
1081 InstSeqNum inst_seq;
1082 MachInst inst;
1083 ExtMachInst ext_inst;
1084 // @todo: Fix this hack.
1085 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1086
1087 if (fault == NoFault) {
1088 // If the read of the first instruction was successful, then grab the
1089 // instructions from the rest of the cache line and put them into the
1090 // queue heading to decode.
1091
1092 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1093 "decode.\n",tid);
1094
1095 // Need to keep track of whether or not a predicted branch
1096 // ended this fetch block.
1097 bool predicted_branch = false;
1098
1099 // Need to keep track of whether or not a delay slot
1100 // instruction has been fetched
1101
1102 for (;
1103 offset < cacheBlkSize &&
1104 numInst < fetchWidth &&
1105 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1106 ++numInst) {
1107
1108 // Get a sequence number.
1109 inst_seq = cpu->getAndIncrementInstSeq();
1110
1111 // Make sure this is a valid index.
1112 assert(offset <= cacheBlkSize - instSize);
1113
1114 // Get the instruction from the array of the cache line.
1115 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1116 (&cacheData[tid][offset]));
1117
1118 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1119
1120 // Create a new DynInst from the instruction fetched.
1121 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1122 next_PC,
1123 inst_seq, cpu);
1124 instruction->setTid(tid);
1125
1126 instruction->setASID(tid);
1127
1128 instruction->setThreadState(cpu->thread[tid]);
1129
1130 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1131 "[sn:%lli]\n",
1132 tid, instruction->readPC(), inst_seq);
1133
1134 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1135 tid, instruction->staticInst->disassemble(fetch_PC));
1136
1137 instruction->traceData =
1138 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1139 instruction->staticInst,
1140 instruction->readPC());
1141
1142 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1143 next_NPC);
1144
1145 // Add instruction to the CPU's list of instructions.
1146 instruction->setInstListIt(cpu->addInst(instruction));
1147
1148 // Write the instruction to the first slot in the queue
1149 // that heads to decode.
1150 toDecode->insts[numInst] = instruction;
1151
1152 toDecode->size++;
1153
1154 // Increment stat of fetched instructions.
1155 ++fetchedInsts;
1156
1157 // Move to the next instruction, unless we have a branch.
1158 fetch_PC = next_PC;
1159
1160 if (instruction->isQuiesce()) {
1161// warn("%lli: Quiesce instruction encountered, halting fetch!",
1162// curTick);
1163 fetchStatus[tid] = QuiescePending;
1164 ++numInst;
1165 status_change = true;
1166 break;
1167 }
1168
1169 offset += instSize;
1170
1171#if ISA_HAS_DELAY_SLOT
1172 if (predicted_branch) {
1173 delaySlotInfo[tid].branchSeqNum = inst_seq;
1174
1175 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1176 tid, inst_seq);
1177 continue;
1178 } else if (delaySlotInfo[tid].numInsts > 0) {
1179 --delaySlotInfo[tid].numInsts;
1180
1181 // It's OK to set PC to target of branch
1182 if (delaySlotInfo[tid].numInsts == 0) {
1183 delaySlotInfo[tid].targetReady = true;
1184
1185 // Break the looping condition
1186 predicted_branch = true;
1187 }
1188
1189 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1190 " process.\n", tid, delaySlotInfo[tid].numInsts);
1191 }
1192#endif
1193 }
1194
1195 if (offset >= cacheBlkSize) {
1196 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1197 "block.\n", tid);
1198 } else if (numInst >= fetchWidth) {
1199 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1200 "for this cycle.\n", tid);
1201 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1202 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1203 "instruction encountered.\n", tid);
1204 }
1205 }
1206
1207 if (numInst > 0) {
1208 wroteToTimeBuffer = true;
1209 }
1210
1211 // Now that fetching is completed, update the PC to signify what the next
1212 // cycle will be.
1213 if (fault == NoFault) {
1214#if ISA_HAS_DELAY_SLOT
1215 if (delaySlotInfo[tid].targetReady &&
1216 delaySlotInfo[tid].numInsts == 0) {
1217 // Set PC to target
1218 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1219 nextPC[tid] = next_PC + instSize; //next_NPC
1220 nextNPC[tid] = next_PC + (2 * instSize);
1221
1222 delaySlotInfo[tid].targetReady = false;
1223 } else {
1224 PC[tid] = next_PC;
1225 nextPC[tid] = next_NPC;
1226 nextNPC[tid] = next_NPC + instSize;
1227 }
1228
1229 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1230#else
1231 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1232 PC[tid] = next_PC;
1233 nextPC[tid] = next_PC + instSize;
1234#endif
1235 } else {
1236 // We shouldn't be in an icache miss and also have a fault (an ITB
1237 // miss)
1238 if (fetchStatus[tid] == IcacheWaitResponse) {
1239 panic("Fetch should have exited prior to this!");
1240 }
1241
1242 // Send the fault to commit. This thread will not do anything
1243 // until commit handles the fault. The only other way it can
1244 // wake up is if a squash comes along and changes the PC.
1245#if FULL_SYSTEM
1246 assert(numInst != fetchWidth);
1247 // Get a sequence number.
1248 inst_seq = cpu->getAndIncrementInstSeq();
1249 // We will use a nop in order to carry the fault.
1250 ext_inst = TheISA::NoopMachInst;
1251
1252 // Create a new DynInst from the dummy nop.
1253 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1254 next_PC,
1255 inst_seq, cpu);
1256 instruction->setPredTarg(next_PC + instSize);
1257 instruction->setTid(tid);
1258
1259 instruction->setASID(tid);
1260
1261 instruction->setThreadState(cpu->thread[tid]);
1262
1263 instruction->traceData = NULL;
1264
1265 instruction->setInstListIt(cpu->addInst(instruction));
1266
1267 instruction->fault = fault;
1268
1269 toDecode->insts[numInst] = instruction;
1270 toDecode->size++;
1271
1272 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1273
1274 fetchStatus[tid] = TrapPending;
1275 status_change = true;
1276
1277// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1278#else // !FULL_SYSTEM
1279 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1280#endif // FULL_SYSTEM
1281 }
1282}
1283
1284template<class Impl>
1285void
1286DefaultFetch<Impl>::recvRetry()
1287{
1288 if (retryPkt != NULL) {
1289 assert(cacheBlocked);
1290 assert(retryTid != -1);
1291 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1292
1293 if (icachePort->sendTiming(retryPkt)) {
1294 fetchStatus[retryTid] = IcacheWaitResponse;
1295 retryPkt = NULL;
1296 retryTid = -1;
1297 cacheBlocked = false;
1298 }
1299 } else {
1300 assert(retryTid == -1);
1301 // Access has been squashed since it was sent out. Just clear
1302 // the cache being blocked.
1303 cacheBlocked = false;
1304 }
1305}
1306
1307///////////////////////////////////////
1308// //
1309// SMT FETCH POLICY MAINTAINED HERE //
1310// //
1311///////////////////////////////////////
1312template<class Impl>
1313int
1314DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1315{
1316 if (numThreads > 1) {
1317 switch (fetch_priority) {
1318
1319 case SingleThread:
1320 return 0;
1321
1322 case RoundRobin:
1323 return roundRobin();
1324
1325 case IQ:
1326 return iqCount();
1327
1328 case LSQ:
1329 return lsqCount();
1330
1331 case Branch:
1332 return branchCount();
1333
1334 default:
1335 return -1;
1336 }
1337 } else {
1338 int tid = *((*activeThreads).begin());
1339
1340 if (fetchStatus[tid] == Running ||
1341 fetchStatus[tid] == IcacheAccessComplete ||
1342 fetchStatus[tid] == Idle) {
1343 return tid;
1344 } else {
1345 return -1;
1346 }
1347 }
1348
1349}
1350
1351
1352template<class Impl>
1353int
1354DefaultFetch<Impl>::roundRobin()
1355{
1356 std::list<unsigned>::iterator pri_iter = priorityList.begin();
1357 std::list<unsigned>::iterator end = priorityList.end();
1358
1359 int high_pri;
1360
1361 while (pri_iter != end) {
1362 high_pri = *pri_iter;
1363
1364 assert(high_pri <= numThreads);
1365
1366 if (fetchStatus[high_pri] == Running ||
1367 fetchStatus[high_pri] == IcacheAccessComplete ||
1368 fetchStatus[high_pri] == Idle) {
1369
1370 priorityList.erase(pri_iter);
1371 priorityList.push_back(high_pri);
1372
1373 return high_pri;
1374 }
1375
1376 pri_iter++;
1377 }
1378
1379 return -1;
1380}
1381
1382template<class Impl>
1383int
1384DefaultFetch<Impl>::iqCount()
1385{
1386 std::priority_queue<unsigned> PQ;
1387
1388 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1389
1390 while (threads != (*activeThreads).end()) {
1391 unsigned tid = *threads++;
1392
1393 PQ.push(fromIEW->iewInfo[tid].iqCount);
1394 }
1395
1396 while (!PQ.empty()) {
1397
1398 unsigned high_pri = PQ.top();
1399
1400 if (fetchStatus[high_pri] == Running ||
1401 fetchStatus[high_pri] == IcacheAccessComplete ||
1402 fetchStatus[high_pri] == Idle)
1403 return high_pri;
1404 else
1405 PQ.pop();
1406
1407 }
1408
1409 return -1;
1410}
1411
1412template<class Impl>
1413int
1414DefaultFetch<Impl>::lsqCount()
1415{
1416 std::priority_queue<unsigned> PQ;
1417
1418
1419 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1420
1421 while (threads != (*activeThreads).end()) {
1422 unsigned tid = *threads++;
1423
1424 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1425 }
1426
1427 while (!PQ.empty()) {
1428
1429 unsigned high_pri = PQ.top();
1430
1431 if (fetchStatus[high_pri] == Running ||
1432 fetchStatus[high_pri] == IcacheAccessComplete ||
1433 fetchStatus[high_pri] == Idle)
1434 return high_pri;
1435 else
1436 PQ.pop();
1437
1438 }
1439
1440 return -1;
1441}
1442
1443template<class Impl>
1444int
1445DefaultFetch<Impl>::branchCount()
1446{
1447 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1448 panic("Branch Count Fetch policy unimplemented\n");
1449 return *threads;
1450}
| 87 return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94 fetch->recvRetry();
95}
96
97template<class Impl>
98DefaultFetch<Impl>::DefaultFetch(Params *params)
99 : mem(params->mem),
100 branchPred(params),
101 decodeToFetchDelay(params->decodeToFetchDelay),
102 renameToFetchDelay(params->renameToFetchDelay),
103 iewToFetchDelay(params->iewToFetchDelay),
104 commitToFetchDelay(params->commitToFetchDelay),
105 fetchWidth(params->fetchWidth),
106 cacheBlocked(false),
107 retryPkt(NULL),
108 retryTid(-1),
109 numThreads(params->numberOfThreads),
110 numFetchingThreads(params->smtNumFetchingThreads),
111 interruptPending(false),
112 drainPending(false),
113 switchedOut(false)
114{
115 if (numThreads > Impl::MaxThreads)
116 fatal("numThreads is not a valid value\n");
117
118 // Set fetch stage's status to inactive.
119 _status = Inactive;
120
121 std::string policy = params->smtFetchPolicy;
122
123 // Convert string to lowercase
124 std::transform(policy.begin(), policy.end(), policy.begin(),
125 (int(*)(int)) tolower);
126
127 // Figure out fetch policy
128 if (policy == "singlethread") {
129 fetchPolicy = SingleThread;
130 if (numThreads > 1)
131 panic("Invalid Fetch Policy for a SMT workload.");
132 } else if (policy == "roundrobin") {
133 fetchPolicy = RoundRobin;
134 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
135 } else if (policy == "branch") {
136 fetchPolicy = Branch;
137 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
138 } else if (policy == "iqcount") {
139 fetchPolicy = IQ;
140 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
141 } else if (policy == "lsqcount") {
142 fetchPolicy = LSQ;
143 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
144 } else {
145 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
146 " RoundRobin,LSQcount,IQcount}\n");
147 }
148
149 // Size of cache block.
150 cacheBlkSize = 64;
151
152 // Create mask to get rid of offset bits.
153 cacheBlkMask = (cacheBlkSize - 1);
154
155 for (int tid=0; tid < numThreads; tid++) {
156
157 fetchStatus[tid] = Running;
158
159 priorityList.push_back(tid);
160
161 memReq[tid] = NULL;
162
163 // Create space to store a cache line.
164 cacheData[tid] = new uint8_t[cacheBlkSize];
165 cacheDataPC[tid] = 0;
166 cacheDataValid[tid] = false;
167
168 delaySlotInfo[tid].branchSeqNum = -1;
169 delaySlotInfo[tid].numInsts = 0;
170 delaySlotInfo[tid].targetAddr = 0;
171 delaySlotInfo[tid].targetReady = false;
172
173 stalls[tid].decode = false;
174 stalls[tid].rename = false;
175 stalls[tid].iew = false;
176 stalls[tid].commit = false;
177 }
178
179 // Get the size of an instruction.
180 instSize = sizeof(TheISA::MachInst);
181}
182
183template <class Impl>
184std::string
185DefaultFetch<Impl>::name() const
186{
187 return cpu->name() + ".fetch";
188}
189
190template <class Impl>
191void
192DefaultFetch<Impl>::regStats()
193{
194 icacheStallCycles
195 .name(name() + ".icacheStallCycles")
196 .desc("Number of cycles fetch is stalled on an Icache miss")
197 .prereq(icacheStallCycles);
198
199 fetchedInsts
200 .name(name() + ".Insts")
201 .desc("Number of instructions fetch has processed")
202 .prereq(fetchedInsts);
203
204 fetchedBranches
205 .name(name() + ".Branches")
206 .desc("Number of branches that fetch encountered")
207 .prereq(fetchedBranches);
208
209 predictedBranches
210 .name(name() + ".predictedBranches")
211 .desc("Number of branches that fetch has predicted taken")
212 .prereq(predictedBranches);
213
214 fetchCycles
215 .name(name() + ".Cycles")
216 .desc("Number of cycles fetch has run and was not squashing or"
217 " blocked")
218 .prereq(fetchCycles);
219
220 fetchSquashCycles
221 .name(name() + ".SquashCycles")
222 .desc("Number of cycles fetch has spent squashing")
223 .prereq(fetchSquashCycles);
224
225 fetchIdleCycles
226 .name(name() + ".IdleCycles")
227 .desc("Number of cycles fetch was idle")
228 .prereq(fetchIdleCycles);
229
230 fetchBlockedCycles
231 .name(name() + ".BlockedCycles")
232 .desc("Number of cycles fetch has spent blocked")
233 .prereq(fetchBlockedCycles);
234
235 fetchedCacheLines
236 .name(name() + ".CacheLines")
237 .desc("Number of cache lines fetched")
238 .prereq(fetchedCacheLines);
239
240 fetchMiscStallCycles
241 .name(name() + ".MiscStallCycles")
242 .desc("Number of cycles fetch has spent waiting on interrupts, or "
243 "bad addresses, or out of MSHRs")
244 .prereq(fetchMiscStallCycles);
245
246 fetchIcacheSquashes
247 .name(name() + ".IcacheSquashes")
248 .desc("Number of outstanding Icache misses that were squashed")
249 .prereq(fetchIcacheSquashes);
250
251 fetchNisnDist
252 .init(/* base value */ 0,
253 /* last value */ fetchWidth,
254 /* bucket size */ 1)
255 .name(name() + ".rateDist")
256 .desc("Number of instructions fetched each cycle (Total)")
257 .flags(Stats::pdf);
258
259 idleRate
260 .name(name() + ".idleRate")
261 .desc("Percent of cycles fetch was idle")
262 .prereq(idleRate);
263 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
264
265 branchRate
266 .name(name() + ".branchRate")
267 .desc("Number of branch fetches per cycle")
268 .flags(Stats::total);
269 branchRate = fetchedBranches / cpu->numCycles;
270
271 fetchRate
272 .name(name() + ".rate")
273 .desc("Number of inst fetches per cycle")
274 .flags(Stats::total);
275 fetchRate = fetchedInsts / cpu->numCycles;
276
277 branchPred.regStats();
278}
279
280template<class Impl>
281void
282DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
283{
284 DPRINTF(Fetch, "Setting the CPU pointer.\n");
285 cpu = cpu_ptr;
286
287 // Name is finally available, so create the port.
288 icachePort = new IcachePort(this);
289
290#if USE_CHECKER
291 if (cpu->checker) {
292 cpu->checker->setIcachePort(icachePort);
293 }
294#endif
295
296 // Schedule fetch to get the correct PC from the CPU
297 // scheduleFetchStartupEvent(1);
298
299 // Fetch needs to start fetching instructions at the very beginning,
300 // so it must start up in active state.
301 switchToActive();
302}
303
304template<class Impl>
305void
306DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
307{
308 DPRINTF(Fetch, "Setting the time buffer pointer.\n");
309 timeBuffer = time_buffer;
310
311 // Create wires to get information from proper places in time buffer.
312 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
313 fromRename = timeBuffer->getWire(-renameToFetchDelay);
314 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
315 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
316}
317
318template<class Impl>
319void
320DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
321{
322 DPRINTF(Fetch, "Setting active threads list pointer.\n");
323 activeThreads = at_ptr;
324}
325
326template<class Impl>
327void
328DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
329{
330 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
331 fetchQueue = fq_ptr;
332
333 // Create wire to write information to proper place in fetch queue.
334 toDecode = fetchQueue->getWire(0);
335}
336
337template<class Impl>
338void
339DefaultFetch<Impl>::initStage()
340{
341 // Setup PC and nextPC with initial state.
342 for (int tid = 0; tid < numThreads; tid++) {
343 PC[tid] = cpu->readPC(tid);
344 nextPC[tid] = cpu->readNextPC(tid);
345#if ISA_HAS_DELAY_SLOT
346 nextNPC[tid] = cpu->readNextNPC(tid);
347#endif
348 }
349}
350
351template<class Impl>
352void
353DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
354{
355 unsigned tid = pkt->req->getThreadNum();
356
357 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
358
359 // Only change the status if it's still waiting on the icache access
360 // to return.
361 if (fetchStatus[tid] != IcacheWaitResponse ||
362 pkt->req != memReq[tid] ||
363 isSwitchedOut()) {
364 ++fetchIcacheSquashes;
365 delete pkt->req;
366 delete pkt;
367 return;
368 }
369
370 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
371 cacheDataValid[tid] = true;
372
373 if (!drainPending) {
374 // Wake up the CPU (if it went to sleep and was waiting on
375 // this completion event).
376 cpu->wakeCPU();
377
378 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
379 tid);
380
381 switchToActive();
382 }
383
384 // Only switch to IcacheAccessComplete if we're not stalled as well.
385 if (checkStall(tid)) {
386 fetchStatus[tid] = Blocked;
387 } else {
388 fetchStatus[tid] = IcacheAccessComplete;
389 }
390
391 // Reset the mem req to NULL.
392 delete pkt->req;
393 delete pkt;
394 memReq[tid] = NULL;
395}
396
397template <class Impl>
398bool
399DefaultFetch<Impl>::drain()
400{
401 // Fetch is ready to drain at any time.
402 cpu->signalDrained();
403 drainPending = true;
404 return true;
405}
406
407template <class Impl>
408void
409DefaultFetch<Impl>::resume()
410{
411 drainPending = false;
412}
413
414template <class Impl>
415void
416DefaultFetch<Impl>::switchOut()
417{
418 switchedOut = true;
419 // Branch predictor needs to have its state cleared.
420 branchPred.switchOut();
421}
422
423template <class Impl>
424void
425DefaultFetch<Impl>::takeOverFrom()
426{
427 // Reset all state
428 for (int i = 0; i < Impl::MaxThreads; ++i) {
429 stalls[i].decode = 0;
430 stalls[i].rename = 0;
431 stalls[i].iew = 0;
432 stalls[i].commit = 0;
433 PC[i] = cpu->readPC(i);
434 nextPC[i] = cpu->readNextPC(i);
435#if ISA_HAS_DELAY_SLOT
436 nextNPC[i] = cpu->readNextNPC(i);
437 delaySlotInfo[i].branchSeqNum = -1;
438 delaySlotInfo[i].numInsts = 0;
439 delaySlotInfo[i].targetAddr = 0;
440 delaySlotInfo[i].targetReady = false;
441#endif
442 fetchStatus[i] = Running;
443 }
444 numInst = 0;
445 wroteToTimeBuffer = false;
446 _status = Inactive;
447 switchedOut = false;
448 interruptPending = false;
449 branchPred.takeOverFrom();
450}
451
452template <class Impl>
453void
454DefaultFetch<Impl>::wakeFromQuiesce()
455{
456 DPRINTF(Fetch, "Waking up from quiesce\n");
457 // Hopefully this is safe
458 // @todo: Allow other threads to wake from quiesce.
459 fetchStatus[0] = Running;
460}
461
462template <class Impl>
463inline void
464DefaultFetch<Impl>::switchToActive()
465{
466 if (_status == Inactive) {
467 DPRINTF(Activity, "Activating stage.\n");
468
469 cpu->activateStage(O3CPU::FetchIdx);
470
471 _status = Active;
472 }
473}
474
475template <class Impl>
476inline void
477DefaultFetch<Impl>::switchToInactive()
478{
479 if (_status == Active) {
480 DPRINTF(Activity, "Deactivating stage.\n");
481
482 cpu->deactivateStage(O3CPU::FetchIdx);
483
484 _status = Inactive;
485 }
486}
487
488template <class Impl>
489bool
490DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
491 Addr &next_NPC)
492{
493 // Do branch prediction check here.
494 // A bit of a misnomer...next_PC is actually the current PC until
495 // this function updates it.
496 bool predict_taken;
497
498 if (!inst->isControl()) {
499#if ISA_HAS_DELAY_SLOT
500 Addr cur_PC = next_PC;
501 next_PC = cur_PC + instSize; //next_NPC;
502 next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
503 inst->setPredTarg(next_NPC);
504#else
505 next_PC = next_PC + instSize;
506 inst->setPredTarg(next_PC);
507#endif
508 return false;
509 }
510
511 int tid = inst->threadNumber;
512#if ISA_HAS_DELAY_SLOT
513 Addr pred_PC = next_PC;
514 predict_taken = branchPred.predict(inst, pred_PC, tid);
515
516 if (predict_taken) {
517 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
518 } else {
519 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
520 }
521
522 if (predict_taken) {
523 next_PC = next_NPC;
524 next_NPC = pred_PC;
525
526 // Update delay slot info
527 ++delaySlotInfo[tid].numInsts;
528 delaySlotInfo[tid].targetAddr = pred_PC;
529 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
530 delaySlotInfo[tid].numInsts);
531 } else { // !predict_taken
532 if (inst->isCondDelaySlot()) {
533 next_PC = pred_PC;
534 // The delay slot is skipped here if there is on
535 // prediction
536 } else {
537 next_PC = next_NPC;
538 // No need to declare a delay slot here since
539 // there is no for the pred. target to jump
540 }
541
542 next_NPC = next_NPC + instSize;
543 }
544#else
545 predict_taken = branchPred.predict(inst, next_PC, tid);
546#endif
547
548 ++fetchedBranches;
549
550 if (predict_taken) {
551 ++predictedBranches;
552 }
553
554 return predict_taken;
555}
556
557template <class Impl>
558bool
559DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
560{
561 Fault fault = NoFault;
562
563#if FULL_SYSTEM
564 // Flag to say whether or not address is physical addr.
565 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
566#else
567 unsigned flags = 0;
568#endif // FULL_SYSTEM
569
570 if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
571 // Hold off fetch from getting new instructions when:
572 // Cache is blocked, or
573 // while an interrupt is pending and we're not in PAL mode, or
574 // fetch is switched out.
575 return false;
576 }
577
578 // Align the fetch PC so it's at the start of a cache block.
579 fetch_PC = icacheBlockAlignPC(fetch_PC);
580
581 // If we've already got the block, no need to try to fetch it again.
582 if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
583 return true;
584 }
585
586 // Setup the memReq to do a read of the first instruction's address.
587 // Set the appropriate read size and flags as well.
588 // Build request here.
589 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
590 fetch_PC, cpu->readCpuId(), tid);
591
592 memReq[tid] = mem_req;
593
594 // Translate the instruction request.
595 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
596
597 // In the case of faults, the fetch stage may need to stall and wait
598 // for the ITB miss to be handled.
599
600 // If translation was successful, attempt to read the first
601 // instruction.
602 if (fault == NoFault) {
603#if 0
604 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
605 memReq[tid]->isUncacheable()) {
606 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
607 "misspeculating path)!",
608 memReq[tid]->paddr);
609 ret_fault = TheISA::genMachineCheckFault();
610 return false;
611 }
612#endif
613
614 // Build packet here.
615 PacketPtr data_pkt = new Packet(mem_req,
616 Packet::ReadReq, Packet::Broadcast);
617 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
618
619 cacheDataPC[tid] = fetch_PC;
620 cacheDataValid[tid] = false;
621
622 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
623
624 fetchedCacheLines++;
625
626 // Now do the timing access to see whether or not the instruction
627 // exists within the cache.
628 if (!icachePort->sendTiming(data_pkt)) {
629 if (data_pkt->result == Packet::BadAddress) {
630 fault = TheISA::genMachineCheckFault();
631 delete mem_req;
632 memReq[tid] = NULL;
633 }
634 assert(retryPkt == NULL);
635 assert(retryTid == -1);
636 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
637 fetchStatus[tid] = IcacheWaitRetry;
638 retryPkt = data_pkt;
639 retryTid = tid;
640 cacheBlocked = true;
641 return false;
642 }
643
644 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
645
646 lastIcacheStall[tid] = curTick;
647
648 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
649 "response.\n", tid);
650
651 fetchStatus[tid] = IcacheWaitResponse;
652 } else {
653 delete mem_req;
654 memReq[tid] = NULL;
655 }
656
657 ret_fault = fault;
658 return true;
659}
660
661template <class Impl>
662inline void
663DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
664{
665 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
666 tid, new_PC);
667
668 PC[tid] = new_PC;
669 nextPC[tid] = new_PC + instSize;
670 nextNPC[tid] = new_PC + (2 * instSize);
671
672 // Clear the icache miss if it's outstanding.
673 if (fetchStatus[tid] == IcacheWaitResponse) {
674 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
675 tid);
676 memReq[tid] = NULL;
677 }
678
679 // Get rid of the retrying packet if it was from this thread.
680 if (retryTid == tid) {
681 assert(cacheBlocked);
682 cacheBlocked = false;
683 retryTid = -1;
684 delete retryPkt->req;
685 delete retryPkt;
686 retryPkt = NULL;
687 }
688
689 fetchStatus[tid] = Squashing;
690
691 ++fetchSquashCycles;
692}
693
694template<class Impl>
695void
696DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
697 const InstSeqNum &seq_num,
698 unsigned tid)
699{
700 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
701
702 doSquash(new_PC, tid);
703
704#if ISA_HAS_DELAY_SLOT
705 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
706 delaySlotInfo[tid].numInsts = 0;
707 delaySlotInfo[tid].targetAddr = 0;
708 delaySlotInfo[tid].targetReady = false;
709 }
710#endif
711
712 // Tell the CPU to remove any instructions that are in flight between
713 // fetch and decode.
714 cpu->removeInstsUntil(seq_num, tid);
715}
716
717template<class Impl>
718bool
719DefaultFetch<Impl>::checkStall(unsigned tid) const
720{
721 bool ret_val = false;
722
723 if (cpu->contextSwitch) {
724 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
725 ret_val = true;
726 } else if (stalls[tid].decode) {
727 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
728 ret_val = true;
729 } else if (stalls[tid].rename) {
730 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
731 ret_val = true;
732 } else if (stalls[tid].iew) {
733 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
734 ret_val = true;
735 } else if (stalls[tid].commit) {
736 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
737 ret_val = true;
738 }
739
740 return ret_val;
741}
742
743template<class Impl>
744typename DefaultFetch<Impl>::FetchStatus
745DefaultFetch<Impl>::updateFetchStatus()
746{
747 //Check Running
748 std::list<unsigned>::iterator threads = (*activeThreads).begin();
749
750 while (threads != (*activeThreads).end()) {
751
752 unsigned tid = *threads++;
753
754 if (fetchStatus[tid] == Running ||
755 fetchStatus[tid] == Squashing ||
756 fetchStatus[tid] == IcacheAccessComplete) {
757
758 if (_status == Inactive) {
759 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
760
761 if (fetchStatus[tid] == IcacheAccessComplete) {
762 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
763 "completion\n",tid);
764 }
765
766 cpu->activateStage(O3CPU::FetchIdx);
767 }
768
769 return Active;
770 }
771 }
772
773 // Stage is switching from active to inactive, notify CPU of it.
774 if (_status == Active) {
775 DPRINTF(Activity, "Deactivating stage.\n");
776
777 cpu->deactivateStage(O3CPU::FetchIdx);
778 }
779
780 return Inactive;
781}
782
783template <class Impl>
784void
785DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
786 bool squash_delay_slot, unsigned tid)
787{
788 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
789
790 doSquash(new_PC, tid);
791
792#if ISA_HAS_DELAY_SLOT
793 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
794 delaySlotInfo[tid].numInsts = 0;
795 delaySlotInfo[tid].targetAddr = 0;
796 delaySlotInfo[tid].targetReady = false;
797 }
798
799 // Tell the CPU to remove any instructions that are not in the ROB.
800 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
801#else
802 // Tell the CPU to remove any instructions that are not in the ROB.
803 cpu->removeInstsNotInROB(tid, true, 0);
804#endif
805}
806
807template <class Impl>
808void
809DefaultFetch<Impl>::tick()
810{
811 std::list<unsigned>::iterator threads = (*activeThreads).begin();
812 bool status_change = false;
813
814 wroteToTimeBuffer = false;
815
816 while (threads != (*activeThreads).end()) {
817 unsigned tid = *threads++;
818
819 // Check the signals for each thread to determine the proper status
820 // for each thread.
821 bool updated_status = checkSignalsAndUpdate(tid);
822 status_change = status_change || updated_status;
823 }
824
825 DPRINTF(Fetch, "Running stage.\n");
826
827 // Reset the number of the instruction we're fetching.
828 numInst = 0;
829
830#if FULL_SYSTEM
831 if (fromCommit->commitInfo[0].interruptPending) {
832 interruptPending = true;
833 }
834
835 if (fromCommit->commitInfo[0].clearInterrupt) {
836 interruptPending = false;
837 }
838#endif
839
840 for (threadFetched = 0; threadFetched < numFetchingThreads;
841 threadFetched++) {
842 // Fetch each of the actively fetching threads.
843 fetch(status_change);
844 }
845
846 // Record number of instructions fetched this cycle for distribution.
847 fetchNisnDist.sample(numInst);
848
849 if (status_change) {
850 // Change the fetch stage status if there was a status change.
851 _status = updateFetchStatus();
852 }
853
854 // If there was activity this cycle, inform the CPU of it.
855 if (wroteToTimeBuffer || cpu->contextSwitch) {
856 DPRINTF(Activity, "Activity this cycle.\n");
857
858 cpu->activityThisCycle();
859 }
860}
861
862template <class Impl>
863bool
864DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
865{
866 // Update the per thread stall statuses.
867 if (fromDecode->decodeBlock[tid]) {
868 stalls[tid].decode = true;
869 }
870
871 if (fromDecode->decodeUnblock[tid]) {
872 assert(stalls[tid].decode);
873 assert(!fromDecode->decodeBlock[tid]);
874 stalls[tid].decode = false;
875 }
876
877 if (fromRename->renameBlock[tid]) {
878 stalls[tid].rename = true;
879 }
880
881 if (fromRename->renameUnblock[tid]) {
882 assert(stalls[tid].rename);
883 assert(!fromRename->renameBlock[tid]);
884 stalls[tid].rename = false;
885 }
886
887 if (fromIEW->iewBlock[tid]) {
888 stalls[tid].iew = true;
889 }
890
891 if (fromIEW->iewUnblock[tid]) {
892 assert(stalls[tid].iew);
893 assert(!fromIEW->iewBlock[tid]);
894 stalls[tid].iew = false;
895 }
896
897 if (fromCommit->commitBlock[tid]) {
898 stalls[tid].commit = true;
899 }
900
901 if (fromCommit->commitUnblock[tid]) {
902 assert(stalls[tid].commit);
903 assert(!fromCommit->commitBlock[tid]);
904 stalls[tid].commit = false;
905 }
906
907 // Check squash signals from commit.
908 if (fromCommit->commitInfo[tid].squash) {
909
910 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
911 "from commit.\n",tid);
912
913#if ISA_HAS_DELAY_SLOT
914 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
915#else
916 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
917#endif
918 // In any case, squash.
919 squash(fromCommit->commitInfo[tid].nextPC,
920 doneSeqNum,
921 fromCommit->commitInfo[tid].squashDelaySlot,
922 tid);
923
924 // Also check if there's a mispredict that happened.
925 if (fromCommit->commitInfo[tid].branchMispredict) {
926 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
927 fromCommit->commitInfo[tid].nextPC,
928 fromCommit->commitInfo[tid].branchTaken,
929 tid);
930 } else {
931 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
932 tid);
933 }
934
935 return true;
936 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
937 // Update the branch predictor if it wasn't a squashed instruction
938 // that was broadcasted.
939 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
940 }
941
942 // Check ROB squash signals from commit.
943 if (fromCommit->commitInfo[tid].robSquashing) {
944 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
945
946 // Continue to squash.
947 fetchStatus[tid] = Squashing;
948
949 return true;
950 }
951
952 // Check squash signals from decode.
953 if (fromDecode->decodeInfo[tid].squash) {
954 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
955 "from decode.\n",tid);
956
957 // Update the branch predictor.
958 if (fromDecode->decodeInfo[tid].branchMispredict) {
959 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
960 fromDecode->decodeInfo[tid].nextPC,
961 fromDecode->decodeInfo[tid].branchTaken,
962 tid);
963 } else {
964 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
965 tid);
966 }
967
968 if (fetchStatus[tid] != Squashing) {
969
970#if ISA_HAS_DELAY_SLOT
971 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
972#else
973 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
974#endif
975 // Squash unless we're already squashing
976 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
977 doneSeqNum,
978 tid);
979
980 return true;
981 }
982 }
983
984 if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
985 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
986
987 fetchStatus[tid] = Blocked;
988
989 return true;
990 }
991
992 if (fetchStatus[tid] == Blocked ||
993 fetchStatus[tid] == Squashing) {
994 // Switch status to running if fetch isn't being told to block or
995 // squash this cycle.
996 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
997 tid);
998
999 fetchStatus[tid] = Running;
1000
1001 return true;
1002 }
1003
1004 // If we've reached this point, we have not gotten any signals that
1005 // cause fetch to change its status. Fetch remains the same as before.
1006 return false;
1007}
1008
1009template<class Impl>
1010void
1011DefaultFetch<Impl>::fetch(bool &status_change)
1012{
1013 //////////////////////////////////////////
1014 // Start actual fetch
1015 //////////////////////////////////////////
1016 int tid = getFetchingThread(fetchPolicy);
1017
1018 if (tid == -1 || drainPending) {
1019 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1020
1021 // Breaks looping condition in tick()
1022 threadFetched = numFetchingThreads;
1023 return;
1024 }
1025
1026 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1027
1028 // The current PC.
1029 Addr &fetch_PC = PC[tid];
1030
1031 // Fault code for memory access.
1032 Fault fault = NoFault;
1033
1034 // If returning from the delay of a cache miss, then update the status
1035 // to running, otherwise do the cache access. Possibly move this up
1036 // to tick() function.
1037 if (fetchStatus[tid] == IcacheAccessComplete) {
1038 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1039 tid);
1040
1041 fetchStatus[tid] = Running;
1042 status_change = true;
1043 } else if (fetchStatus[tid] == Running) {
1044 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1045 "instruction, starting at PC %08p.\n",
1046 tid, fetch_PC);
1047
1048 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1049 if (!fetch_success) {
1050 if (cacheBlocked) {
1051 ++icacheStallCycles;
1052 } else {
1053 ++fetchMiscStallCycles;
1054 }
1055 return;
1056 }
1057 } else {
1058 if (fetchStatus[tid] == Idle) {
1059 ++fetchIdleCycles;
1060 } else if (fetchStatus[tid] == Blocked) {
1061 ++fetchBlockedCycles;
1062 } else if (fetchStatus[tid] == Squashing) {
1063 ++fetchSquashCycles;
1064 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1065 ++icacheStallCycles;
1066 }
1067
1068 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1069 // fetch should do nothing.
1070 return;
1071 }
1072
1073 ++fetchCycles;
1074
1075 // If we had a stall due to an icache miss, then return.
1076 if (fetchStatus[tid] == IcacheWaitResponse) {
1077 ++icacheStallCycles;
1078 status_change = true;
1079 return;
1080 }
1081
1082 Addr next_PC = fetch_PC;
1083 Addr next_NPC = next_PC + instSize;
1084 InstSeqNum inst_seq;
1085 MachInst inst;
1086 ExtMachInst ext_inst;
1087 // @todo: Fix this hack.
1088 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1089
1090 if (fault == NoFault) {
1091 // If the read of the first instruction was successful, then grab the
1092 // instructions from the rest of the cache line and put them into the
1093 // queue heading to decode.
1094
1095 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1096 "decode.\n",tid);
1097
1098 // Need to keep track of whether or not a predicted branch
1099 // ended this fetch block.
1100 bool predicted_branch = false;
1101
1102 // Need to keep track of whether or not a delay slot
1103 // instruction has been fetched
1104
1105 for (;
1106 offset < cacheBlkSize &&
1107 numInst < fetchWidth &&
1108 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1109 ++numInst) {
1110
1111 // Get a sequence number.
1112 inst_seq = cpu->getAndIncrementInstSeq();
1113
1114 // Make sure this is a valid index.
1115 assert(offset <= cacheBlkSize - instSize);
1116
1117 // Get the instruction from the array of the cache line.
1118 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1119 (&cacheData[tid][offset]));
1120
1121 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1122
1123 // Create a new DynInst from the instruction fetched.
1124 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1125 next_PC,
1126 inst_seq, cpu);
1127 instruction->setTid(tid);
1128
1129 instruction->setASID(tid);
1130
1131 instruction->setThreadState(cpu->thread[tid]);
1132
1133 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1134 "[sn:%lli]\n",
1135 tid, instruction->readPC(), inst_seq);
1136
1137 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1138 tid, instruction->staticInst->disassemble(fetch_PC));
1139
1140 instruction->traceData =
1141 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1142 instruction->staticInst,
1143 instruction->readPC());
1144
1145 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1146 next_NPC);
1147
1148 // Add instruction to the CPU's list of instructions.
1149 instruction->setInstListIt(cpu->addInst(instruction));
1150
1151 // Write the instruction to the first slot in the queue
1152 // that heads to decode.
1153 toDecode->insts[numInst] = instruction;
1154
1155 toDecode->size++;
1156
1157 // Increment stat of fetched instructions.
1158 ++fetchedInsts;
1159
1160 // Move to the next instruction, unless we have a branch.
1161 fetch_PC = next_PC;
1162
1163 if (instruction->isQuiesce()) {
1164// warn("%lli: Quiesce instruction encountered, halting fetch!",
1165// curTick);
1166 fetchStatus[tid] = QuiescePending;
1167 ++numInst;
1168 status_change = true;
1169 break;
1170 }
1171
1172 offset += instSize;
1173
1174#if ISA_HAS_DELAY_SLOT
1175 if (predicted_branch) {
1176 delaySlotInfo[tid].branchSeqNum = inst_seq;
1177
1178 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1179 tid, inst_seq);
1180 continue;
1181 } else if (delaySlotInfo[tid].numInsts > 0) {
1182 --delaySlotInfo[tid].numInsts;
1183
1184 // It's OK to set PC to target of branch
1185 if (delaySlotInfo[tid].numInsts == 0) {
1186 delaySlotInfo[tid].targetReady = true;
1187
1188 // Break the looping condition
1189 predicted_branch = true;
1190 }
1191
1192 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1193 " process.\n", tid, delaySlotInfo[tid].numInsts);
1194 }
1195#endif
1196 }
1197
1198 if (offset >= cacheBlkSize) {
1199 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1200 "block.\n", tid);
1201 } else if (numInst >= fetchWidth) {
1202 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1203 "for this cycle.\n", tid);
1204 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1205 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1206 "instruction encountered.\n", tid);
1207 }
1208 }
1209
1210 if (numInst > 0) {
1211 wroteToTimeBuffer = true;
1212 }
1213
1214 // Now that fetching is completed, update the PC to signify what the next
1215 // cycle will be.
1216 if (fault == NoFault) {
1217#if ISA_HAS_DELAY_SLOT
1218 if (delaySlotInfo[tid].targetReady &&
1219 delaySlotInfo[tid].numInsts == 0) {
1220 // Set PC to target
1221 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1222 nextPC[tid] = next_PC + instSize; //next_NPC
1223 nextNPC[tid] = next_PC + (2 * instSize);
1224
1225 delaySlotInfo[tid].targetReady = false;
1226 } else {
1227 PC[tid] = next_PC;
1228 nextPC[tid] = next_NPC;
1229 nextNPC[tid] = next_NPC + instSize;
1230 }
1231
1232 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1233#else
1234 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1235 PC[tid] = next_PC;
1236 nextPC[tid] = next_PC + instSize;
1237#endif
1238 } else {
1239 // We shouldn't be in an icache miss and also have a fault (an ITB
1240 // miss)
1241 if (fetchStatus[tid] == IcacheWaitResponse) {
1242 panic("Fetch should have exited prior to this!");
1243 }
1244
1245 // Send the fault to commit. This thread will not do anything
1246 // until commit handles the fault. The only other way it can
1247 // wake up is if a squash comes along and changes the PC.
1248#if FULL_SYSTEM
1249 assert(numInst != fetchWidth);
1250 // Get a sequence number.
1251 inst_seq = cpu->getAndIncrementInstSeq();
1252 // We will use a nop in order to carry the fault.
1253 ext_inst = TheISA::NoopMachInst;
1254
1255 // Create a new DynInst from the dummy nop.
1256 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1257 next_PC,
1258 inst_seq, cpu);
1259 instruction->setPredTarg(next_PC + instSize);
1260 instruction->setTid(tid);
1261
1262 instruction->setASID(tid);
1263
1264 instruction->setThreadState(cpu->thread[tid]);
1265
1266 instruction->traceData = NULL;
1267
1268 instruction->setInstListIt(cpu->addInst(instruction));
1269
1270 instruction->fault = fault;
1271
1272 toDecode->insts[numInst] = instruction;
1273 toDecode->size++;
1274
1275 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1276
1277 fetchStatus[tid] = TrapPending;
1278 status_change = true;
1279
1280// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1281#else // !FULL_SYSTEM
1282 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1283#endif // FULL_SYSTEM
1284 }
1285}
1286
1287template<class Impl>
1288void
1289DefaultFetch<Impl>::recvRetry()
1290{
1291 if (retryPkt != NULL) {
1292 assert(cacheBlocked);
1293 assert(retryTid != -1);
1294 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1295
1296 if (icachePort->sendTiming(retryPkt)) {
1297 fetchStatus[retryTid] = IcacheWaitResponse;
1298 retryPkt = NULL;
1299 retryTid = -1;
1300 cacheBlocked = false;
1301 }
1302 } else {
1303 assert(retryTid == -1);
1304 // Access has been squashed since it was sent out. Just clear
1305 // the cache being blocked.
1306 cacheBlocked = false;
1307 }
1308}
1309
1310///////////////////////////////////////
1311// //
1312// SMT FETCH POLICY MAINTAINED HERE //
1313// //
1314///////////////////////////////////////
1315template<class Impl>
1316int
1317DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1318{
1319 if (numThreads > 1) {
1320 switch (fetch_priority) {
1321
1322 case SingleThread:
1323 return 0;
1324
1325 case RoundRobin:
1326 return roundRobin();
1327
1328 case IQ:
1329 return iqCount();
1330
1331 case LSQ:
1332 return lsqCount();
1333
1334 case Branch:
1335 return branchCount();
1336
1337 default:
1338 return -1;
1339 }
1340 } else {
1341 int tid = *((*activeThreads).begin());
1342
1343 if (fetchStatus[tid] == Running ||
1344 fetchStatus[tid] == IcacheAccessComplete ||
1345 fetchStatus[tid] == Idle) {
1346 return tid;
1347 } else {
1348 return -1;
1349 }
1350 }
1351
1352}
1353
1354
1355template<class Impl>
1356int
1357DefaultFetch<Impl>::roundRobin()
1358{
1359 std::list<unsigned>::iterator pri_iter = priorityList.begin();
1360 std::list<unsigned>::iterator end = priorityList.end();
1361
1362 int high_pri;
1363
1364 while (pri_iter != end) {
1365 high_pri = *pri_iter;
1366
1367 assert(high_pri <= numThreads);
1368
1369 if (fetchStatus[high_pri] == Running ||
1370 fetchStatus[high_pri] == IcacheAccessComplete ||
1371 fetchStatus[high_pri] == Idle) {
1372
1373 priorityList.erase(pri_iter);
1374 priorityList.push_back(high_pri);
1375
1376 return high_pri;
1377 }
1378
1379 pri_iter++;
1380 }
1381
1382 return -1;
1383}
1384
1385template<class Impl>
1386int
1387DefaultFetch<Impl>::iqCount()
1388{
1389 std::priority_queue<unsigned> PQ;
1390
1391 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1392
1393 while (threads != (*activeThreads).end()) {
1394 unsigned tid = *threads++;
1395
1396 PQ.push(fromIEW->iewInfo[tid].iqCount);
1397 }
1398
1399 while (!PQ.empty()) {
1400
1401 unsigned high_pri = PQ.top();
1402
1403 if (fetchStatus[high_pri] == Running ||
1404 fetchStatus[high_pri] == IcacheAccessComplete ||
1405 fetchStatus[high_pri] == Idle)
1406 return high_pri;
1407 else
1408 PQ.pop();
1409
1410 }
1411
1412 return -1;
1413}
1414
1415template<class Impl>
1416int
1417DefaultFetch<Impl>::lsqCount()
1418{
1419 std::priority_queue<unsigned> PQ;
1420
1421
1422 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1423
1424 while (threads != (*activeThreads).end()) {
1425 unsigned tid = *threads++;
1426
1427 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1428 }
1429
1430 while (!PQ.empty()) {
1431
1432 unsigned high_pri = PQ.top();
1433
1434 if (fetchStatus[high_pri] == Running ||
1435 fetchStatus[high_pri] == IcacheAccessComplete ||
1436 fetchStatus[high_pri] == Idle)
1437 return high_pri;
1438 else
1439 PQ.pop();
1440
1441 }
1442
1443 return -1;
1444}
1445
1446template<class Impl>
1447int
1448DefaultFetch<Impl>::branchCount()
1449{
1450 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1451 panic("Branch Count Fetch policy unimplemented\n");
1452 return *threads;
1453}
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