1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "base/remote_gdb.hh"
49#include "sim/system.hh"
50#endif // FULL_SYSTEM
51
52#include <algorithm>
53
54using namespace std;
55using namespace TheISA;
56
57template<class Impl>
58Tick
59DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
60{
61 panic("DefaultFetch doesn't expect recvAtomic callback!");
62 return curTick;
63}
64
65template<class Impl>
66void
67DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
68{
69 panic("DefaultFetch doesn't expect recvFunctional callback!");
70}
71
72template<class Impl>
73void
74DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
75{
76 if (status == RangeChange)
77 return;
78
79 panic("DefaultFetch doesn't expect recvStatusChange callback!");
80}
81
82template<class Impl>
83bool
84DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
85{
86 fetch->processCacheCompletion(pkt);
87 return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94 fetch->recvRetry();
95}
96
97template<class Impl>
98DefaultFetch<Impl>::DefaultFetch(Params *params)
99 : mem(params->mem),
100 branchPred(params),
101 decodeToFetchDelay(params->decodeToFetchDelay),
102 renameToFetchDelay(params->renameToFetchDelay),
103 iewToFetchDelay(params->iewToFetchDelay),
104 commitToFetchDelay(params->commitToFetchDelay),
105 fetchWidth(params->fetchWidth),
106 cacheBlocked(false),
107 retryPkt(NULL),
108 retryTid(-1),
109 numThreads(params->numberOfThreads),
110 numFetchingThreads(params->smtNumFetchingThreads),
111 interruptPending(false),
112 drainPending(false),
113 switchedOut(false)
114{
115 if (numThreads > Impl::MaxThreads)
116 fatal("numThreads is not a valid value\n");
117
118 // Set fetch stage's status to inactive.
119 _status = Inactive;
120
121 string policy = params->smtFetchPolicy;
122
123 // Convert string to lowercase
124 std::transform(policy.begin(), policy.end(), policy.begin(),
125 (int(*)(int)) tolower);
126
127 // Figure out fetch policy
128 if (policy == "singlethread") {
129 fetchPolicy = SingleThread;
130 if (numThreads > 1)
131 panic("Invalid Fetch Policy for a SMT workload.");
132 } else if (policy == "roundrobin") {
133 fetchPolicy = RoundRobin;
134 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
135 } else if (policy == "branch") {
136 fetchPolicy = Branch;
137 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
138 } else if (policy == "iqcount") {
139 fetchPolicy = IQ;
140 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
141 } else if (policy == "lsqcount") {
142 fetchPolicy = LSQ;
143 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
144 } else {
145 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
146 " RoundRobin,LSQcount,IQcount}\n");
147 }
148
149 // Size of cache block.
150 cacheBlkSize = 64;
151
152 // Create mask to get rid of offset bits.
153 cacheBlkMask = (cacheBlkSize - 1);
154
155 for (int tid=0; tid < numThreads; tid++) {
156
157 fetchStatus[tid] = Running;
158
159 priorityList.push_back(tid);
160
161 memReq[tid] = NULL;
162
163 // Create space to store a cache line.
164 cacheData[tid] = new uint8_t[cacheBlkSize];
165
166 stalls[tid].decode = 0;
167 stalls[tid].rename = 0;
168 stalls[tid].iew = 0;
169 stalls[tid].commit = 0;
170 }
171
172 // Get the size of an instruction.
173 instSize = sizeof(MachInst);
174}
175
176template <class Impl>
177std::string
178DefaultFetch<Impl>::name() const
179{
180 return cpu->name() + ".fetch";
181}
182
183template <class Impl>
184void
185DefaultFetch<Impl>::regStats()
186{
187 icacheStallCycles
188 .name(name() + ".icacheStallCycles")
189 .desc("Number of cycles fetch is stalled on an Icache miss")
190 .prereq(icacheStallCycles);
191
192 fetchedInsts
193 .name(name() + ".Insts")
194 .desc("Number of instructions fetch has processed")
195 .prereq(fetchedInsts);
196
197 fetchedBranches
198 .name(name() + ".Branches")
199 .desc("Number of branches that fetch encountered")
200 .prereq(fetchedBranches);
201
202 predictedBranches
203 .name(name() + ".predictedBranches")
204 .desc("Number of branches that fetch has predicted taken")
205 .prereq(predictedBranches);
206
207 fetchCycles
208 .name(name() + ".Cycles")
209 .desc("Number of cycles fetch has run and was not squashing or"
210 " blocked")
211 .prereq(fetchCycles);
212
213 fetchSquashCycles
214 .name(name() + ".SquashCycles")
215 .desc("Number of cycles fetch has spent squashing")
216 .prereq(fetchSquashCycles);
217
218 fetchIdleCycles
219 .name(name() + ".IdleCycles")
220 .desc("Number of cycles fetch was idle")
221 .prereq(fetchIdleCycles);
222
223 fetchBlockedCycles
224 .name(name() + ".BlockedCycles")
225 .desc("Number of cycles fetch has spent blocked")
226 .prereq(fetchBlockedCycles);
227
228 fetchedCacheLines
229 .name(name() + ".CacheLines")
230 .desc("Number of cache lines fetched")
231 .prereq(fetchedCacheLines);
232
233 fetchMiscStallCycles
234 .name(name() + ".MiscStallCycles")
235 .desc("Number of cycles fetch has spent waiting on interrupts, or "
236 "bad addresses, or out of MSHRs")
237 .prereq(fetchMiscStallCycles);
238
239 fetchIcacheSquashes
240 .name(name() + ".IcacheSquashes")
241 .desc("Number of outstanding Icache misses that were squashed")
242 .prereq(fetchIcacheSquashes);
243
244 fetchNisnDist
245 .init(/* base value */ 0,
246 /* last value */ fetchWidth,
247 /* bucket size */ 1)
248 .name(name() + ".rateDist")
249 .desc("Number of instructions fetched each cycle (Total)")
250 .flags(Stats::pdf);
251
252 idleRate
253 .name(name() + ".idleRate")
254 .desc("Percent of cycles fetch was idle")
255 .prereq(idleRate);
256 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
257
258 branchRate
259 .name(name() + ".branchRate")
260 .desc("Number of branch fetches per cycle")
261 .flags(Stats::total);
262 branchRate = fetchedBranches / cpu->numCycles;
263
264 fetchRate
265 .name(name() + ".rate")
266 .desc("Number of inst fetches per cycle")
267 .flags(Stats::total);
268 fetchRate = fetchedInsts / cpu->numCycles;
269
270 branchPred.regStats();
271}
272
273template<class Impl>
274void
275DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
276{
277 DPRINTF(Fetch, "Setting the CPU pointer.\n");
278 cpu = cpu_ptr;
279
280 // Name is finally available, so create the port.
281 icachePort = new IcachePort(this);
282
283 Port *mem_dport = mem->getPort("");
284 icachePort->setPeer(mem_dport);
285 mem_dport->setPeer(icachePort);
286
287#if USE_CHECKER
288 if (cpu->checker) {
289 cpu->checker->setIcachePort(icachePort);
290 }
291#endif
292
293 // Fetch needs to start fetching instructions at the very beginning,
294 // so it must start up in active state.
295 switchToActive();
296}
297
298template<class Impl>
299void
300DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
301{
302 DPRINTF(Fetch, "Setting the time buffer pointer.\n");
303 timeBuffer = time_buffer;
304
305 // Create wires to get information from proper places in time buffer.
306 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
307 fromRename = timeBuffer->getWire(-renameToFetchDelay);
308 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
309 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
310}
311
312template<class Impl>
313void
314DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
315{
316 DPRINTF(Fetch, "Setting active threads list pointer.\n");
317 activeThreads = at_ptr;
318}
319
320template<class Impl>
321void
322DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
323{
324 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
325 fetchQueue = fq_ptr;
326
327 // Create wire to write information to proper place in fetch queue.
328 toDecode = fetchQueue->getWire(0);
329}
330
331template<class Impl>
332void
333DefaultFetch<Impl>::initStage()
334{
335 // Setup PC and nextPC with initial state.
336 for (int tid = 0; tid < numThreads; tid++) {
337 PC[tid] = cpu->readPC(tid);
338 nextPC[tid] = cpu->readNextPC(tid);
339#if THE_ISA != ALPHA_ISA
340 nextNPC[tid] = cpu->readNextNPC(tid);
341#endif
342 }
343}
344
345template<class Impl>
346void
347DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
348{
349 unsigned tid = pkt->req->getThreadNum();
350
351 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
352
353 // Only change the status if it's still waiting on the icache access
354 // to return.
355 if (fetchStatus[tid] != IcacheWaitResponse ||
356 pkt->req != memReq[tid] ||
357 isSwitchedOut() ||
358 drainPending) {
359 ++fetchIcacheSquashes;
360 delete pkt->req;
361 delete pkt;
362 return;
363 }
364
365 // Wake up the CPU (if it went to sleep and was waiting on this completion
366 // event).
367 cpu->wakeCPU();
368
369 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
370 tid);
371
372 switchToActive();
373
374 // Only switch to IcacheAccessComplete if we're not stalled as well.
375 if (checkStall(tid)) {
376 fetchStatus[tid] = Blocked;
377 } else {
378 fetchStatus[tid] = IcacheAccessComplete;
379 }
380
381 // Reset the mem req to NULL.
382 delete pkt->req;
383 delete pkt;
384 memReq[tid] = NULL;
385}
386
387template <class Impl>
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "base/remote_gdb.hh"
49#include "sim/system.hh"
50#endif // FULL_SYSTEM
51
52#include <algorithm>
53
54using namespace std;
55using namespace TheISA;
56
57template<class Impl>
58Tick
59DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
60{
61 panic("DefaultFetch doesn't expect recvAtomic callback!");
62 return curTick;
63}
64
65template<class Impl>
66void
67DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
68{
69 panic("DefaultFetch doesn't expect recvFunctional callback!");
70}
71
72template<class Impl>
73void
74DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
75{
76 if (status == RangeChange)
77 return;
78
79 panic("DefaultFetch doesn't expect recvStatusChange callback!");
80}
81
82template<class Impl>
83bool
84DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
85{
86 fetch->processCacheCompletion(pkt);
87 return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94 fetch->recvRetry();
95}
96
97template<class Impl>
98DefaultFetch<Impl>::DefaultFetch(Params *params)
99 : mem(params->mem),
100 branchPred(params),
101 decodeToFetchDelay(params->decodeToFetchDelay),
102 renameToFetchDelay(params->renameToFetchDelay),
103 iewToFetchDelay(params->iewToFetchDelay),
104 commitToFetchDelay(params->commitToFetchDelay),
105 fetchWidth(params->fetchWidth),
106 cacheBlocked(false),
107 retryPkt(NULL),
108 retryTid(-1),
109 numThreads(params->numberOfThreads),
110 numFetchingThreads(params->smtNumFetchingThreads),
111 interruptPending(false),
112 drainPending(false),
113 switchedOut(false)
114{
115 if (numThreads > Impl::MaxThreads)
116 fatal("numThreads is not a valid value\n");
117
118 // Set fetch stage's status to inactive.
119 _status = Inactive;
120
121 string policy = params->smtFetchPolicy;
122
123 // Convert string to lowercase
124 std::transform(policy.begin(), policy.end(), policy.begin(),
125 (int(*)(int)) tolower);
126
127 // Figure out fetch policy
128 if (policy == "singlethread") {
129 fetchPolicy = SingleThread;
130 if (numThreads > 1)
131 panic("Invalid Fetch Policy for a SMT workload.");
132 } else if (policy == "roundrobin") {
133 fetchPolicy = RoundRobin;
134 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
135 } else if (policy == "branch") {
136 fetchPolicy = Branch;
137 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
138 } else if (policy == "iqcount") {
139 fetchPolicy = IQ;
140 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
141 } else if (policy == "lsqcount") {
142 fetchPolicy = LSQ;
143 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
144 } else {
145 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
146 " RoundRobin,LSQcount,IQcount}\n");
147 }
148
149 // Size of cache block.
150 cacheBlkSize = 64;
151
152 // Create mask to get rid of offset bits.
153 cacheBlkMask = (cacheBlkSize - 1);
154
155 for (int tid=0; tid < numThreads; tid++) {
156
157 fetchStatus[tid] = Running;
158
159 priorityList.push_back(tid);
160
161 memReq[tid] = NULL;
162
163 // Create space to store a cache line.
164 cacheData[tid] = new uint8_t[cacheBlkSize];
165
166 stalls[tid].decode = 0;
167 stalls[tid].rename = 0;
168 stalls[tid].iew = 0;
169 stalls[tid].commit = 0;
170 }
171
172 // Get the size of an instruction.
173 instSize = sizeof(MachInst);
174}
175
176template <class Impl>
177std::string
178DefaultFetch<Impl>::name() const
179{
180 return cpu->name() + ".fetch";
181}
182
183template <class Impl>
184void
185DefaultFetch<Impl>::regStats()
186{
187 icacheStallCycles
188 .name(name() + ".icacheStallCycles")
189 .desc("Number of cycles fetch is stalled on an Icache miss")
190 .prereq(icacheStallCycles);
191
192 fetchedInsts
193 .name(name() + ".Insts")
194 .desc("Number of instructions fetch has processed")
195 .prereq(fetchedInsts);
196
197 fetchedBranches
198 .name(name() + ".Branches")
199 .desc("Number of branches that fetch encountered")
200 .prereq(fetchedBranches);
201
202 predictedBranches
203 .name(name() + ".predictedBranches")
204 .desc("Number of branches that fetch has predicted taken")
205 .prereq(predictedBranches);
206
207 fetchCycles
208 .name(name() + ".Cycles")
209 .desc("Number of cycles fetch has run and was not squashing or"
210 " blocked")
211 .prereq(fetchCycles);
212
213 fetchSquashCycles
214 .name(name() + ".SquashCycles")
215 .desc("Number of cycles fetch has spent squashing")
216 .prereq(fetchSquashCycles);
217
218 fetchIdleCycles
219 .name(name() + ".IdleCycles")
220 .desc("Number of cycles fetch was idle")
221 .prereq(fetchIdleCycles);
222
223 fetchBlockedCycles
224 .name(name() + ".BlockedCycles")
225 .desc("Number of cycles fetch has spent blocked")
226 .prereq(fetchBlockedCycles);
227
228 fetchedCacheLines
229 .name(name() + ".CacheLines")
230 .desc("Number of cache lines fetched")
231 .prereq(fetchedCacheLines);
232
233 fetchMiscStallCycles
234 .name(name() + ".MiscStallCycles")
235 .desc("Number of cycles fetch has spent waiting on interrupts, or "
236 "bad addresses, or out of MSHRs")
237 .prereq(fetchMiscStallCycles);
238
239 fetchIcacheSquashes
240 .name(name() + ".IcacheSquashes")
241 .desc("Number of outstanding Icache misses that were squashed")
242 .prereq(fetchIcacheSquashes);
243
244 fetchNisnDist
245 .init(/* base value */ 0,
246 /* last value */ fetchWidth,
247 /* bucket size */ 1)
248 .name(name() + ".rateDist")
249 .desc("Number of instructions fetched each cycle (Total)")
250 .flags(Stats::pdf);
251
252 idleRate
253 .name(name() + ".idleRate")
254 .desc("Percent of cycles fetch was idle")
255 .prereq(idleRate);
256 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
257
258 branchRate
259 .name(name() + ".branchRate")
260 .desc("Number of branch fetches per cycle")
261 .flags(Stats::total);
262 branchRate = fetchedBranches / cpu->numCycles;
263
264 fetchRate
265 .name(name() + ".rate")
266 .desc("Number of inst fetches per cycle")
267 .flags(Stats::total);
268 fetchRate = fetchedInsts / cpu->numCycles;
269
270 branchPred.regStats();
271}
272
273template<class Impl>
274void
275DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
276{
277 DPRINTF(Fetch, "Setting the CPU pointer.\n");
278 cpu = cpu_ptr;
279
280 // Name is finally available, so create the port.
281 icachePort = new IcachePort(this);
282
283 Port *mem_dport = mem->getPort("");
284 icachePort->setPeer(mem_dport);
285 mem_dport->setPeer(icachePort);
286
287#if USE_CHECKER
288 if (cpu->checker) {
289 cpu->checker->setIcachePort(icachePort);
290 }
291#endif
292
293 // Fetch needs to start fetching instructions at the very beginning,
294 // so it must start up in active state.
295 switchToActive();
296}
297
298template<class Impl>
299void
300DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
301{
302 DPRINTF(Fetch, "Setting the time buffer pointer.\n");
303 timeBuffer = time_buffer;
304
305 // Create wires to get information from proper places in time buffer.
306 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
307 fromRename = timeBuffer->getWire(-renameToFetchDelay);
308 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
309 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
310}
311
312template<class Impl>
313void
314DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
315{
316 DPRINTF(Fetch, "Setting active threads list pointer.\n");
317 activeThreads = at_ptr;
318}
319
320template<class Impl>
321void
322DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
323{
324 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
325 fetchQueue = fq_ptr;
326
327 // Create wire to write information to proper place in fetch queue.
328 toDecode = fetchQueue->getWire(0);
329}
330
331template<class Impl>
332void
333DefaultFetch<Impl>::initStage()
334{
335 // Setup PC and nextPC with initial state.
336 for (int tid = 0; tid < numThreads; tid++) {
337 PC[tid] = cpu->readPC(tid);
338 nextPC[tid] = cpu->readNextPC(tid);
339#if THE_ISA != ALPHA_ISA
340 nextNPC[tid] = cpu->readNextNPC(tid);
341#endif
342 }
343}
344
345template<class Impl>
346void
347DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
348{
349 unsigned tid = pkt->req->getThreadNum();
350
351 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
352
353 // Only change the status if it's still waiting on the icache access
354 // to return.
355 if (fetchStatus[tid] != IcacheWaitResponse ||
356 pkt->req != memReq[tid] ||
357 isSwitchedOut() ||
358 drainPending) {
359 ++fetchIcacheSquashes;
360 delete pkt->req;
361 delete pkt;
362 return;
363 }
364
365 // Wake up the CPU (if it went to sleep and was waiting on this completion
366 // event).
367 cpu->wakeCPU();
368
369 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
370 tid);
371
372 switchToActive();
373
374 // Only switch to IcacheAccessComplete if we're not stalled as well.
375 if (checkStall(tid)) {
376 fetchStatus[tid] = Blocked;
377 } else {
378 fetchStatus[tid] = IcacheAccessComplete;
379 }
380
381 // Reset the mem req to NULL.
382 delete pkt->req;
383 delete pkt;
384 memReq[tid] = NULL;
385}
386
387template <class Impl>
|
394}
395
396template <class Impl>
397void
398DefaultFetch<Impl>::resume()
399{
400 drainPending = false;
401}
402
403template <class Impl>
404void
405DefaultFetch<Impl>::switchOut()
406{
407 switchedOut = true;
408 // Branch predictor needs to have its state cleared.
409 branchPred.switchOut();
410}
411
412template <class Impl>
413void
414DefaultFetch<Impl>::takeOverFrom()
415{
416 // Reset all state
417 for (int i = 0; i < Impl::MaxThreads; ++i) {
418 stalls[i].decode = 0;
419 stalls[i].rename = 0;
420 stalls[i].iew = 0;
421 stalls[i].commit = 0;
422 PC[i] = cpu->readPC(i);
423 nextPC[i] = cpu->readNextPC(i);
424#if THE_ISA != ALPHA_ISA
425 nextNPC[i] = cpu->readNextNPC(i);
426#endif
427 fetchStatus[i] = Running;
428 }
429 numInst = 0;
430 wroteToTimeBuffer = false;
431 _status = Inactive;
432 switchedOut = false;
433 branchPred.takeOverFrom();
434}
435
436template <class Impl>
437void
438DefaultFetch<Impl>::wakeFromQuiesce()
439{
440 DPRINTF(Fetch, "Waking up from quiesce\n");
441 // Hopefully this is safe
442 // @todo: Allow other threads to wake from quiesce.
443 fetchStatus[0] = Running;
444}
445
446template <class Impl>
447inline void
448DefaultFetch<Impl>::switchToActive()
449{
450 if (_status == Inactive) {
451 DPRINTF(Activity, "Activating stage.\n");
452
453 cpu->activateStage(O3CPU::FetchIdx);
454
455 _status = Active;
456 }
457}
458
459template <class Impl>
460inline void
461DefaultFetch<Impl>::switchToInactive()
462{
463 if (_status == Active) {
464 DPRINTF(Activity, "Deactivating stage.\n");
465
466 cpu->deactivateStage(O3CPU::FetchIdx);
467
468 _status = Inactive;
469 }
470}
471
472template <class Impl>
473bool
474DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
475{
476 // Do branch prediction check here.
477 // A bit of a misnomer...next_PC is actually the current PC until
478 // this function updates it.
479 bool predict_taken;
480
481 if (!inst->isControl()) {
482 next_PC = next_PC + instSize;
483 inst->setPredTarg(next_PC);
484 return false;
485 }
486
487 predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
488
489 ++fetchedBranches;
490
491 if (predict_taken) {
492 ++predictedBranches;
493 }
494
495 return predict_taken;
496}
497
498template <class Impl>
499bool
500DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
501{
502 Fault fault = NoFault;
503
504#if FULL_SYSTEM
505 // Flag to say whether or not address is physical addr.
506 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
507#else
508 unsigned flags = 0;
509#endif // FULL_SYSTEM
510
511 if (cacheBlocked || (interruptPending && flags == 0) || drainPending) {
512 // Hold off fetch from getting new instructions when:
513 // Cache is blocked, or
514 // while an interrupt is pending and we're not in PAL mode, or
515 // fetch is switched out.
516 return false;
517 }
518
519 // Align the fetch PC so it's at the start of a cache block.
520 fetch_PC = icacheBlockAlignPC(fetch_PC);
521
522 // Setup the memReq to do a read of the first instruction's address.
523 // Set the appropriate read size and flags as well.
524 // Build request here.
525 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
526 fetch_PC, cpu->readCpuId(), tid);
527
528 memReq[tid] = mem_req;
529
530 // Translate the instruction request.
531 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
532
533 // In the case of faults, the fetch stage may need to stall and wait
534 // for the ITB miss to be handled.
535
536 // If translation was successful, attempt to read the first
537 // instruction.
538 if (fault == NoFault) {
539#if 0
540 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
541 memReq[tid]->flags & UNCACHEABLE) {
542 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
543 "misspeculating path)!",
544 memReq[tid]->paddr);
545 ret_fault = TheISA::genMachineCheckFault();
546 return false;
547 }
548#endif
549
550 // Build packet here.
551 PacketPtr data_pkt = new Packet(mem_req,
552 Packet::ReadReq, Packet::Broadcast);
553 data_pkt->dataStatic(cacheData[tid]);
554
555 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
556
557 fetchedCacheLines++;
558
559 // Now do the timing access to see whether or not the instruction
560 // exists within the cache.
561 if (!icachePort->sendTiming(data_pkt)) {
562 assert(retryPkt == NULL);
563 assert(retryTid == -1);
564 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
565 fetchStatus[tid] = IcacheWaitRetry;
566 retryPkt = data_pkt;
567 retryTid = tid;
568 cacheBlocked = true;
569 return false;
570 }
571
572 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
573
574 lastIcacheStall[tid] = curTick;
575
576 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
577 "response.\n", tid);
578
579 fetchStatus[tid] = IcacheWaitResponse;
580 } else {
581 delete mem_req;
582 memReq[tid] = NULL;
583 }
584
585 ret_fault = fault;
586 return true;
587}
588
589template <class Impl>
590inline void
591DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
592{
593 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
594 tid, new_PC);
595
596 PC[tid] = new_PC;
597 nextPC[tid] = new_PC + instSize;
598
599 // Clear the icache miss if it's outstanding.
600 if (fetchStatus[tid] == IcacheWaitResponse) {
601 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
602 tid);
603 memReq[tid] = NULL;
604 }
605
606 // Get rid of the retrying packet if it was from this thread.
607 if (retryTid == tid) {
608 assert(cacheBlocked);
609 cacheBlocked = false;
610 retryTid = -1;
611 retryPkt = NULL;
612 delete retryPkt->req;
613 delete retryPkt;
614 }
615
616 fetchStatus[tid] = Squashing;
617
618 ++fetchSquashCycles;
619}
620
621template<class Impl>
622void
623DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
624 const InstSeqNum &seq_num,
625 unsigned tid)
626{
627 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
628
629 doSquash(new_PC, tid);
630
631 // Tell the CPU to remove any instructions that are in flight between
632 // fetch and decode.
633 cpu->removeInstsUntil(seq_num, tid);
634}
635
636template<class Impl>
637bool
638DefaultFetch<Impl>::checkStall(unsigned tid) const
639{
640 bool ret_val = false;
641
642 if (cpu->contextSwitch) {
643 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
644 ret_val = true;
645 } else if (stalls[tid].decode) {
646 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
647 ret_val = true;
648 } else if (stalls[tid].rename) {
649 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
650 ret_val = true;
651 } else if (stalls[tid].iew) {
652 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
653 ret_val = true;
654 } else if (stalls[tid].commit) {
655 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
656 ret_val = true;
657 }
658
659 return ret_val;
660}
661
662template<class Impl>
663typename DefaultFetch<Impl>::FetchStatus
664DefaultFetch<Impl>::updateFetchStatus()
665{
666 //Check Running
667 list<unsigned>::iterator threads = (*activeThreads).begin();
668
669 while (threads != (*activeThreads).end()) {
670
671 unsigned tid = *threads++;
672
673 if (fetchStatus[tid] == Running ||
674 fetchStatus[tid] == Squashing ||
675 fetchStatus[tid] == IcacheAccessComplete) {
676
677 if (_status == Inactive) {
678 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
679
680 if (fetchStatus[tid] == IcacheAccessComplete) {
681 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
682 "completion\n",tid);
683 }
684
685 cpu->activateStage(O3CPU::FetchIdx);
686 }
687
688 return Active;
689 }
690 }
691
692 // Stage is switching from active to inactive, notify CPU of it.
693 if (_status == Active) {
694 DPRINTF(Activity, "Deactivating stage.\n");
695
696 cpu->deactivateStage(O3CPU::FetchIdx);
697 }
698
699 return Inactive;
700}
701
702template <class Impl>
703void
704DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
705{
706 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
707
708 doSquash(new_PC, tid);
709
710 // Tell the CPU to remove any instructions that are not in the ROB.
711 cpu->removeInstsNotInROB(tid);
712}
713
714template <class Impl>
715void
716DefaultFetch<Impl>::tick()
717{
718 list<unsigned>::iterator threads = (*activeThreads).begin();
719 bool status_change = false;
720
721 wroteToTimeBuffer = false;
722
723 while (threads != (*activeThreads).end()) {
724 unsigned tid = *threads++;
725
726 // Check the signals for each thread to determine the proper status
727 // for each thread.
728 bool updated_status = checkSignalsAndUpdate(tid);
729 status_change = status_change || updated_status;
730 }
731
732 DPRINTF(Fetch, "Running stage.\n");
733
734 // Reset the number of the instruction we're fetching.
735 numInst = 0;
736
737#if FULL_SYSTEM
738 if (fromCommit->commitInfo[0].interruptPending) {
739 interruptPending = true;
740 }
741
742 if (fromCommit->commitInfo[0].clearInterrupt) {
743 interruptPending = false;
744 }
745#endif
746
747 for (threadFetched = 0; threadFetched < numFetchingThreads;
748 threadFetched++) {
749 // Fetch each of the actively fetching threads.
750 fetch(status_change);
751 }
752
753 // Record number of instructions fetched this cycle for distribution.
754 fetchNisnDist.sample(numInst);
755
756 if (status_change) {
757 // Change the fetch stage status if there was a status change.
758 _status = updateFetchStatus();
759 }
760
761 // If there was activity this cycle, inform the CPU of it.
762 if (wroteToTimeBuffer || cpu->contextSwitch) {
763 DPRINTF(Activity, "Activity this cycle.\n");
764
765 cpu->activityThisCycle();
766 }
767}
768
769template <class Impl>
770bool
771DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
772{
773 // Update the per thread stall statuses.
774 if (fromDecode->decodeBlock[tid]) {
775 stalls[tid].decode = true;
776 }
777
778 if (fromDecode->decodeUnblock[tid]) {
779 assert(stalls[tid].decode);
780 assert(!fromDecode->decodeBlock[tid]);
781 stalls[tid].decode = false;
782 }
783
784 if (fromRename->renameBlock[tid]) {
785 stalls[tid].rename = true;
786 }
787
788 if (fromRename->renameUnblock[tid]) {
789 assert(stalls[tid].rename);
790 assert(!fromRename->renameBlock[tid]);
791 stalls[tid].rename = false;
792 }
793
794 if (fromIEW->iewBlock[tid]) {
795 stalls[tid].iew = true;
796 }
797
798 if (fromIEW->iewUnblock[tid]) {
799 assert(stalls[tid].iew);
800 assert(!fromIEW->iewBlock[tid]);
801 stalls[tid].iew = false;
802 }
803
804 if (fromCommit->commitBlock[tid]) {
805 stalls[tid].commit = true;
806 }
807
808 if (fromCommit->commitUnblock[tid]) {
809 assert(stalls[tid].commit);
810 assert(!fromCommit->commitBlock[tid]);
811 stalls[tid].commit = false;
812 }
813
814 // Check squash signals from commit.
815 if (fromCommit->commitInfo[tid].squash) {
816
817 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
818 "from commit.\n",tid);
819
820 // In any case, squash.
821 squash(fromCommit->commitInfo[tid].nextPC,tid);
822
823 // Also check if there's a mispredict that happened.
824 if (fromCommit->commitInfo[tid].branchMispredict) {
825 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
826 fromCommit->commitInfo[tid].nextPC,
827 fromCommit->commitInfo[tid].branchTaken,
828 tid);
829 } else {
830 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
831 tid);
832 }
833
834 return true;
835 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
836 // Update the branch predictor if it wasn't a squashed instruction
837 // that was broadcasted.
838 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
839 }
840
841 // Check ROB squash signals from commit.
842 if (fromCommit->commitInfo[tid].robSquashing) {
843 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
844
845 // Continue to squash.
846 fetchStatus[tid] = Squashing;
847
848 return true;
849 }
850
851 // Check squash signals from decode.
852 if (fromDecode->decodeInfo[tid].squash) {
853 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
854 "from decode.\n",tid);
855
856 // Update the branch predictor.
857 if (fromDecode->decodeInfo[tid].branchMispredict) {
858 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
859 fromDecode->decodeInfo[tid].nextPC,
860 fromDecode->decodeInfo[tid].branchTaken,
861 tid);
862 } else {
863 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
864 tid);
865 }
866
867 if (fetchStatus[tid] != Squashing) {
868 // Squash unless we're already squashing
869 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
870 fromDecode->decodeInfo[tid].doneSeqNum,
871 tid);
872
873 return true;
874 }
875 }
876
877 if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
878 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
879
880 fetchStatus[tid] = Blocked;
881
882 return true;
883 }
884
885 if (fetchStatus[tid] == Blocked ||
886 fetchStatus[tid] == Squashing) {
887 // Switch status to running if fetch isn't being told to block or
888 // squash this cycle.
889 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
890 tid);
891
892 fetchStatus[tid] = Running;
893
894 return true;
895 }
896
897 // If we've reached this point, we have not gotten any signals that
898 // cause fetch to change its status. Fetch remains the same as before.
899 return false;
900}
901
902template<class Impl>
903void
904DefaultFetch<Impl>::fetch(bool &status_change)
905{
906 //////////////////////////////////////////
907 // Start actual fetch
908 //////////////////////////////////////////
909 int tid = getFetchingThread(fetchPolicy);
910
911 if (tid == -1) {
912 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
913
914 // Breaks looping condition in tick()
915 threadFetched = numFetchingThreads;
916 return;
917 }
918
919 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
920
921 // The current PC.
922 Addr &fetch_PC = PC[tid];
923
924 // Fault code for memory access.
925 Fault fault = NoFault;
926
927 // If returning from the delay of a cache miss, then update the status
928 // to running, otherwise do the cache access. Possibly move this up
929 // to tick() function.
930 if (fetchStatus[tid] == IcacheAccessComplete) {
931 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
932 tid);
933
934 fetchStatus[tid] = Running;
935 status_change = true;
936 } else if (fetchStatus[tid] == Running) {
937 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
938 "instruction, starting at PC %08p.\n",
939 tid, fetch_PC);
940
941 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
942 if (!fetch_success) {
943 if (cacheBlocked) {
944 ++icacheStallCycles;
945 } else {
946 ++fetchMiscStallCycles;
947 }
948 return;
949 }
950 } else {
951 if (fetchStatus[tid] == Idle) {
952 ++fetchIdleCycles;
953 } else if (fetchStatus[tid] == Blocked) {
954 ++fetchBlockedCycles;
955 } else if (fetchStatus[tid] == Squashing) {
956 ++fetchSquashCycles;
957 } else if (fetchStatus[tid] == IcacheWaitResponse) {
958 ++icacheStallCycles;
959 }
960
961 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
962 // fetch should do nothing.
963 return;
964 }
965
966 ++fetchCycles;
967
968 // If we had a stall due to an icache miss, then return.
969 if (fetchStatus[tid] == IcacheWaitResponse) {
970 ++icacheStallCycles;
971 status_change = true;
972 return;
973 }
974
975 Addr next_PC = fetch_PC;
976 InstSeqNum inst_seq;
977 MachInst inst;
978 ExtMachInst ext_inst;
979 // @todo: Fix this hack.
980 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
981
982 if (fault == NoFault) {
983 // If the read of the first instruction was successful, then grab the
984 // instructions from the rest of the cache line and put them into the
985 // queue heading to decode.
986
987 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
988 "decode.\n",tid);
989
990 // Need to keep track of whether or not a predicted branch
991 // ended this fetch block.
992 bool predicted_branch = false;
993
994 for (;
995 offset < cacheBlkSize &&
996 numInst < fetchWidth &&
997 !predicted_branch;
998 ++numInst) {
999
1000 // Get a sequence number.
1001 inst_seq = cpu->getAndIncrementInstSeq();
1002
1003 // Make sure this is a valid index.
1004 assert(offset <= cacheBlkSize - instSize);
1005
1006 // Get the instruction from the array of the cache line.
1007 inst = gtoh(*reinterpret_cast<MachInst *>
1008 (&cacheData[tid][offset]));
1009
1010 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1011
1012 // Create a new DynInst from the instruction fetched.
1013 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1014 next_PC,
1015 inst_seq, cpu);
1016 instruction->setTid(tid);
1017
1018 instruction->setASID(tid);
1019
1020 instruction->setThreadState(cpu->thread[tid]);
1021
1022 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1023 "[sn:%lli]\n",
1024 tid, instruction->readPC(), inst_seq);
1025
1026 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1027 tid, instruction->staticInst->disassemble(fetch_PC));
1028
1029 instruction->traceData =
1030 Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
1031 instruction->staticInst,
1032 instruction->readPC(),tid);
1033
1034 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
1035
1036 // Add instruction to the CPU's list of instructions.
1037 instruction->setInstListIt(cpu->addInst(instruction));
1038
1039 // Write the instruction to the first slot in the queue
1040 // that heads to decode.
1041 toDecode->insts[numInst] = instruction;
1042
1043 toDecode->size++;
1044
1045 // Increment stat of fetched instructions.
1046 ++fetchedInsts;
1047
1048 // Move to the next instruction, unless we have a branch.
1049 fetch_PC = next_PC;
1050
1051 if (instruction->isQuiesce()) {
1052 warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
1053 curTick);
1054 fetchStatus[tid] = QuiescePending;
1055 ++numInst;
1056 status_change = true;
1057 break;
1058 }
1059
1060 offset+= instSize;
1061 }
1062 }
1063
1064 if (numInst > 0) {
1065 wroteToTimeBuffer = true;
1066 }
1067
1068 // Now that fetching is completed, update the PC to signify what the next
1069 // cycle will be.
1070 if (fault == NoFault) {
1071 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1072
1073#if THE_ISA == ALPHA_ISA
1074 PC[tid] = next_PC;
1075 nextPC[tid] = next_PC + instSize;
1076#else
1077 PC[tid] = next_PC;
1078 nextPC[tid] = next_PC + instSize;
1079 nextPC[tid] = next_PC + instSize;
1080
1081 thread->setNextPC(thread->readNextNPC());
1082 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
1083#endif
1084 } else {
1085 // We shouldn't be in an icache miss and also have a fault (an ITB
1086 // miss)
1087 if (fetchStatus[tid] == IcacheWaitResponse) {
1088 panic("Fetch should have exited prior to this!");
1089 }
1090
1091 // Send the fault to commit. This thread will not do anything
1092 // until commit handles the fault. The only other way it can
1093 // wake up is if a squash comes along and changes the PC.
1094#if FULL_SYSTEM
1095 assert(numInst != fetchWidth);
1096 // Get a sequence number.
1097 inst_seq = cpu->getAndIncrementInstSeq();
1098 // We will use a nop in order to carry the fault.
1099 ext_inst = TheISA::NoopMachInst;
1100
1101 // Create a new DynInst from the dummy nop.
1102 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1103 next_PC,
1104 inst_seq, cpu);
1105 instruction->setPredTarg(next_PC + instSize);
1106 instruction->setTid(tid);
1107
1108 instruction->setASID(tid);
1109
1110 instruction->setThreadState(cpu->thread[tid]);
1111
1112 instruction->traceData = NULL;
1113
1114 instruction->setInstListIt(cpu->addInst(instruction));
1115
1116 instruction->fault = fault;
1117
1118 toDecode->insts[numInst] = instruction;
1119 toDecode->size++;
1120
1121 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1122
1123 fetchStatus[tid] = TrapPending;
1124 status_change = true;
1125
1126 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1127#else // !FULL_SYSTEM
1128 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1129#endif // FULL_SYSTEM
1130 }
1131}
1132
1133template<class Impl>
1134void
1135DefaultFetch<Impl>::recvRetry()
1136{
1137 assert(cacheBlocked);
1138 if (retryPkt != NULL) {
1139 assert(retryTid != -1);
1140 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1141
1142 if (icachePort->sendTiming(retryPkt)) {
1143 fetchStatus[retryTid] = IcacheWaitResponse;
1144 retryPkt = NULL;
1145 retryTid = -1;
1146 cacheBlocked = false;
1147 }
1148 } else {
1149 assert(retryTid == -1);
1150 // Access has been squashed since it was sent out. Just clear
1151 // the cache being blocked.
1152 cacheBlocked = false;
1153 }
1154}
1155
1156///////////////////////////////////////
1157// //
1158// SMT FETCH POLICY MAINTAINED HERE //
1159// //
1160///////////////////////////////////////
1161template<class Impl>
1162int
1163DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1164{
1165 if (numThreads > 1) {
1166 switch (fetch_priority) {
1167
1168 case SingleThread:
1169 return 0;
1170
1171 case RoundRobin:
1172 return roundRobin();
1173
1174 case IQ:
1175 return iqCount();
1176
1177 case LSQ:
1178 return lsqCount();
1179
1180 case Branch:
1181 return branchCount();
1182
1183 default:
1184 return -1;
1185 }
1186 } else {
1187 int tid = *((*activeThreads).begin());
1188
1189 if (fetchStatus[tid] == Running ||
1190 fetchStatus[tid] == IcacheAccessComplete ||
1191 fetchStatus[tid] == Idle) {
1192 return tid;
1193 } else {
1194 return -1;
1195 }
1196 }
1197
1198}
1199
1200
1201template<class Impl>
1202int
1203DefaultFetch<Impl>::roundRobin()
1204{
1205 list<unsigned>::iterator pri_iter = priorityList.begin();
1206 list<unsigned>::iterator end = priorityList.end();
1207
1208 int high_pri;
1209
1210 while (pri_iter != end) {
1211 high_pri = *pri_iter;
1212
1213 assert(high_pri <= numThreads);
1214
1215 if (fetchStatus[high_pri] == Running ||
1216 fetchStatus[high_pri] == IcacheAccessComplete ||
1217 fetchStatus[high_pri] == Idle) {
1218
1219 priorityList.erase(pri_iter);
1220 priorityList.push_back(high_pri);
1221
1222 return high_pri;
1223 }
1224
1225 pri_iter++;
1226 }
1227
1228 return -1;
1229}
1230
1231template<class Impl>
1232int
1233DefaultFetch<Impl>::iqCount()
1234{
1235 priority_queue<unsigned> PQ;
1236
1237 list<unsigned>::iterator threads = (*activeThreads).begin();
1238
1239 while (threads != (*activeThreads).end()) {
1240 unsigned tid = *threads++;
1241
1242 PQ.push(fromIEW->iewInfo[tid].iqCount);
1243 }
1244
1245 while (!PQ.empty()) {
1246
1247 unsigned high_pri = PQ.top();
1248
1249 if (fetchStatus[high_pri] == Running ||
1250 fetchStatus[high_pri] == IcacheAccessComplete ||
1251 fetchStatus[high_pri] == Idle)
1252 return high_pri;
1253 else
1254 PQ.pop();
1255
1256 }
1257
1258 return -1;
1259}
1260
1261template<class Impl>
1262int
1263DefaultFetch<Impl>::lsqCount()
1264{
1265 priority_queue<unsigned> PQ;
1266
1267
1268 list<unsigned>::iterator threads = (*activeThreads).begin();
1269
1270 while (threads != (*activeThreads).end()) {
1271 unsigned tid = *threads++;
1272
1273 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1274 }
1275
1276 while (!PQ.empty()) {
1277
1278 unsigned high_pri = PQ.top();
1279
1280 if (fetchStatus[high_pri] == Running ||
1281 fetchStatus[high_pri] == IcacheAccessComplete ||
1282 fetchStatus[high_pri] == Idle)
1283 return high_pri;
1284 else
1285 PQ.pop();
1286
1287 }
1288
1289 return -1;
1290}
1291
1292template<class Impl>
1293int
1294DefaultFetch<Impl>::branchCount()
1295{
1296 list<unsigned>::iterator threads = (*activeThreads).begin();
1297 panic("Branch Count Fetch policy unimplemented\n");
1298 return *threads;
1299}
| 395}
396
397template <class Impl>
398void
399DefaultFetch<Impl>::resume()
400{
401 drainPending = false;
402}
403
404template <class Impl>
405void
406DefaultFetch<Impl>::switchOut()
407{
408 switchedOut = true;
409 // Branch predictor needs to have its state cleared.
410 branchPred.switchOut();
411}
412
413template <class Impl>
414void
415DefaultFetch<Impl>::takeOverFrom()
416{
417 // Reset all state
418 for (int i = 0; i < Impl::MaxThreads; ++i) {
419 stalls[i].decode = 0;
420 stalls[i].rename = 0;
421 stalls[i].iew = 0;
422 stalls[i].commit = 0;
423 PC[i] = cpu->readPC(i);
424 nextPC[i] = cpu->readNextPC(i);
425#if THE_ISA != ALPHA_ISA
426 nextNPC[i] = cpu->readNextNPC(i);
427#endif
428 fetchStatus[i] = Running;
429 }
430 numInst = 0;
431 wroteToTimeBuffer = false;
432 _status = Inactive;
433 switchedOut = false;
434 branchPred.takeOverFrom();
435}
436
437template <class Impl>
438void
439DefaultFetch<Impl>::wakeFromQuiesce()
440{
441 DPRINTF(Fetch, "Waking up from quiesce\n");
442 // Hopefully this is safe
443 // @todo: Allow other threads to wake from quiesce.
444 fetchStatus[0] = Running;
445}
446
447template <class Impl>
448inline void
449DefaultFetch<Impl>::switchToActive()
450{
451 if (_status == Inactive) {
452 DPRINTF(Activity, "Activating stage.\n");
453
454 cpu->activateStage(O3CPU::FetchIdx);
455
456 _status = Active;
457 }
458}
459
460template <class Impl>
461inline void
462DefaultFetch<Impl>::switchToInactive()
463{
464 if (_status == Active) {
465 DPRINTF(Activity, "Deactivating stage.\n");
466
467 cpu->deactivateStage(O3CPU::FetchIdx);
468
469 _status = Inactive;
470 }
471}
472
473template <class Impl>
474bool
475DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
476{
477 // Do branch prediction check here.
478 // A bit of a misnomer...next_PC is actually the current PC until
479 // this function updates it.
480 bool predict_taken;
481
482 if (!inst->isControl()) {
483 next_PC = next_PC + instSize;
484 inst->setPredTarg(next_PC);
485 return false;
486 }
487
488 predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
489
490 ++fetchedBranches;
491
492 if (predict_taken) {
493 ++predictedBranches;
494 }
495
496 return predict_taken;
497}
498
499template <class Impl>
500bool
501DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
502{
503 Fault fault = NoFault;
504
505#if FULL_SYSTEM
506 // Flag to say whether or not address is physical addr.
507 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
508#else
509 unsigned flags = 0;
510#endif // FULL_SYSTEM
511
512 if (cacheBlocked || (interruptPending && flags == 0) || drainPending) {
513 // Hold off fetch from getting new instructions when:
514 // Cache is blocked, or
515 // while an interrupt is pending and we're not in PAL mode, or
516 // fetch is switched out.
517 return false;
518 }
519
520 // Align the fetch PC so it's at the start of a cache block.
521 fetch_PC = icacheBlockAlignPC(fetch_PC);
522
523 // Setup the memReq to do a read of the first instruction's address.
524 // Set the appropriate read size and flags as well.
525 // Build request here.
526 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
527 fetch_PC, cpu->readCpuId(), tid);
528
529 memReq[tid] = mem_req;
530
531 // Translate the instruction request.
532 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
533
534 // In the case of faults, the fetch stage may need to stall and wait
535 // for the ITB miss to be handled.
536
537 // If translation was successful, attempt to read the first
538 // instruction.
539 if (fault == NoFault) {
540#if 0
541 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
542 memReq[tid]->flags & UNCACHEABLE) {
543 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
544 "misspeculating path)!",
545 memReq[tid]->paddr);
546 ret_fault = TheISA::genMachineCheckFault();
547 return false;
548 }
549#endif
550
551 // Build packet here.
552 PacketPtr data_pkt = new Packet(mem_req,
553 Packet::ReadReq, Packet::Broadcast);
554 data_pkt->dataStatic(cacheData[tid]);
555
556 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
557
558 fetchedCacheLines++;
559
560 // Now do the timing access to see whether or not the instruction
561 // exists within the cache.
562 if (!icachePort->sendTiming(data_pkt)) {
563 assert(retryPkt == NULL);
564 assert(retryTid == -1);
565 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
566 fetchStatus[tid] = IcacheWaitRetry;
567 retryPkt = data_pkt;
568 retryTid = tid;
569 cacheBlocked = true;
570 return false;
571 }
572
573 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
574
575 lastIcacheStall[tid] = curTick;
576
577 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
578 "response.\n", tid);
579
580 fetchStatus[tid] = IcacheWaitResponse;
581 } else {
582 delete mem_req;
583 memReq[tid] = NULL;
584 }
585
586 ret_fault = fault;
587 return true;
588}
589
590template <class Impl>
591inline void
592DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
593{
594 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
595 tid, new_PC);
596
597 PC[tid] = new_PC;
598 nextPC[tid] = new_PC + instSize;
599
600 // Clear the icache miss if it's outstanding.
601 if (fetchStatus[tid] == IcacheWaitResponse) {
602 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
603 tid);
604 memReq[tid] = NULL;
605 }
606
607 // Get rid of the retrying packet if it was from this thread.
608 if (retryTid == tid) {
609 assert(cacheBlocked);
610 cacheBlocked = false;
611 retryTid = -1;
612 retryPkt = NULL;
613 delete retryPkt->req;
614 delete retryPkt;
615 }
616
617 fetchStatus[tid] = Squashing;
618
619 ++fetchSquashCycles;
620}
621
622template<class Impl>
623void
624DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
625 const InstSeqNum &seq_num,
626 unsigned tid)
627{
628 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
629
630 doSquash(new_PC, tid);
631
632 // Tell the CPU to remove any instructions that are in flight between
633 // fetch and decode.
634 cpu->removeInstsUntil(seq_num, tid);
635}
636
637template<class Impl>
638bool
639DefaultFetch<Impl>::checkStall(unsigned tid) const
640{
641 bool ret_val = false;
642
643 if (cpu->contextSwitch) {
644 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
645 ret_val = true;
646 } else if (stalls[tid].decode) {
647 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
648 ret_val = true;
649 } else if (stalls[tid].rename) {
650 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
651 ret_val = true;
652 } else if (stalls[tid].iew) {
653 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
654 ret_val = true;
655 } else if (stalls[tid].commit) {
656 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
657 ret_val = true;
658 }
659
660 return ret_val;
661}
662
663template<class Impl>
664typename DefaultFetch<Impl>::FetchStatus
665DefaultFetch<Impl>::updateFetchStatus()
666{
667 //Check Running
668 list<unsigned>::iterator threads = (*activeThreads).begin();
669
670 while (threads != (*activeThreads).end()) {
671
672 unsigned tid = *threads++;
673
674 if (fetchStatus[tid] == Running ||
675 fetchStatus[tid] == Squashing ||
676 fetchStatus[tid] == IcacheAccessComplete) {
677
678 if (_status == Inactive) {
679 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
680
681 if (fetchStatus[tid] == IcacheAccessComplete) {
682 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
683 "completion\n",tid);
684 }
685
686 cpu->activateStage(O3CPU::FetchIdx);
687 }
688
689 return Active;
690 }
691 }
692
693 // Stage is switching from active to inactive, notify CPU of it.
694 if (_status == Active) {
695 DPRINTF(Activity, "Deactivating stage.\n");
696
697 cpu->deactivateStage(O3CPU::FetchIdx);
698 }
699
700 return Inactive;
701}
702
703template <class Impl>
704void
705DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
706{
707 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
708
709 doSquash(new_PC, tid);
710
711 // Tell the CPU to remove any instructions that are not in the ROB.
712 cpu->removeInstsNotInROB(tid);
713}
714
715template <class Impl>
716void
717DefaultFetch<Impl>::tick()
718{
719 list<unsigned>::iterator threads = (*activeThreads).begin();
720 bool status_change = false;
721
722 wroteToTimeBuffer = false;
723
724 while (threads != (*activeThreads).end()) {
725 unsigned tid = *threads++;
726
727 // Check the signals for each thread to determine the proper status
728 // for each thread.
729 bool updated_status = checkSignalsAndUpdate(tid);
730 status_change = status_change || updated_status;
731 }
732
733 DPRINTF(Fetch, "Running stage.\n");
734
735 // Reset the number of the instruction we're fetching.
736 numInst = 0;
737
738#if FULL_SYSTEM
739 if (fromCommit->commitInfo[0].interruptPending) {
740 interruptPending = true;
741 }
742
743 if (fromCommit->commitInfo[0].clearInterrupt) {
744 interruptPending = false;
745 }
746#endif
747
748 for (threadFetched = 0; threadFetched < numFetchingThreads;
749 threadFetched++) {
750 // Fetch each of the actively fetching threads.
751 fetch(status_change);
752 }
753
754 // Record number of instructions fetched this cycle for distribution.
755 fetchNisnDist.sample(numInst);
756
757 if (status_change) {
758 // Change the fetch stage status if there was a status change.
759 _status = updateFetchStatus();
760 }
761
762 // If there was activity this cycle, inform the CPU of it.
763 if (wroteToTimeBuffer || cpu->contextSwitch) {
764 DPRINTF(Activity, "Activity this cycle.\n");
765
766 cpu->activityThisCycle();
767 }
768}
769
770template <class Impl>
771bool
772DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
773{
774 // Update the per thread stall statuses.
775 if (fromDecode->decodeBlock[tid]) {
776 stalls[tid].decode = true;
777 }
778
779 if (fromDecode->decodeUnblock[tid]) {
780 assert(stalls[tid].decode);
781 assert(!fromDecode->decodeBlock[tid]);
782 stalls[tid].decode = false;
783 }
784
785 if (fromRename->renameBlock[tid]) {
786 stalls[tid].rename = true;
787 }
788
789 if (fromRename->renameUnblock[tid]) {
790 assert(stalls[tid].rename);
791 assert(!fromRename->renameBlock[tid]);
792 stalls[tid].rename = false;
793 }
794
795 if (fromIEW->iewBlock[tid]) {
796 stalls[tid].iew = true;
797 }
798
799 if (fromIEW->iewUnblock[tid]) {
800 assert(stalls[tid].iew);
801 assert(!fromIEW->iewBlock[tid]);
802 stalls[tid].iew = false;
803 }
804
805 if (fromCommit->commitBlock[tid]) {
806 stalls[tid].commit = true;
807 }
808
809 if (fromCommit->commitUnblock[tid]) {
810 assert(stalls[tid].commit);
811 assert(!fromCommit->commitBlock[tid]);
812 stalls[tid].commit = false;
813 }
814
815 // Check squash signals from commit.
816 if (fromCommit->commitInfo[tid].squash) {
817
818 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
819 "from commit.\n",tid);
820
821 // In any case, squash.
822 squash(fromCommit->commitInfo[tid].nextPC,tid);
823
824 // Also check if there's a mispredict that happened.
825 if (fromCommit->commitInfo[tid].branchMispredict) {
826 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
827 fromCommit->commitInfo[tid].nextPC,
828 fromCommit->commitInfo[tid].branchTaken,
829 tid);
830 } else {
831 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
832 tid);
833 }
834
835 return true;
836 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
837 // Update the branch predictor if it wasn't a squashed instruction
838 // that was broadcasted.
839 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
840 }
841
842 // Check ROB squash signals from commit.
843 if (fromCommit->commitInfo[tid].robSquashing) {
844 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
845
846 // Continue to squash.
847 fetchStatus[tid] = Squashing;
848
849 return true;
850 }
851
852 // Check squash signals from decode.
853 if (fromDecode->decodeInfo[tid].squash) {
854 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
855 "from decode.\n",tid);
856
857 // Update the branch predictor.
858 if (fromDecode->decodeInfo[tid].branchMispredict) {
859 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
860 fromDecode->decodeInfo[tid].nextPC,
861 fromDecode->decodeInfo[tid].branchTaken,
862 tid);
863 } else {
864 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
865 tid);
866 }
867
868 if (fetchStatus[tid] != Squashing) {
869 // Squash unless we're already squashing
870 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
871 fromDecode->decodeInfo[tid].doneSeqNum,
872 tid);
873
874 return true;
875 }
876 }
877
878 if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
879 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
880
881 fetchStatus[tid] = Blocked;
882
883 return true;
884 }
885
886 if (fetchStatus[tid] == Blocked ||
887 fetchStatus[tid] == Squashing) {
888 // Switch status to running if fetch isn't being told to block or
889 // squash this cycle.
890 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
891 tid);
892
893 fetchStatus[tid] = Running;
894
895 return true;
896 }
897
898 // If we've reached this point, we have not gotten any signals that
899 // cause fetch to change its status. Fetch remains the same as before.
900 return false;
901}
902
903template<class Impl>
904void
905DefaultFetch<Impl>::fetch(bool &status_change)
906{
907 //////////////////////////////////////////
908 // Start actual fetch
909 //////////////////////////////////////////
910 int tid = getFetchingThread(fetchPolicy);
911
912 if (tid == -1) {
913 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
914
915 // Breaks looping condition in tick()
916 threadFetched = numFetchingThreads;
917 return;
918 }
919
920 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
921
922 // The current PC.
923 Addr &fetch_PC = PC[tid];
924
925 // Fault code for memory access.
926 Fault fault = NoFault;
927
928 // If returning from the delay of a cache miss, then update the status
929 // to running, otherwise do the cache access. Possibly move this up
930 // to tick() function.
931 if (fetchStatus[tid] == IcacheAccessComplete) {
932 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
933 tid);
934
935 fetchStatus[tid] = Running;
936 status_change = true;
937 } else if (fetchStatus[tid] == Running) {
938 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
939 "instruction, starting at PC %08p.\n",
940 tid, fetch_PC);
941
942 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
943 if (!fetch_success) {
944 if (cacheBlocked) {
945 ++icacheStallCycles;
946 } else {
947 ++fetchMiscStallCycles;
948 }
949 return;
950 }
951 } else {
952 if (fetchStatus[tid] == Idle) {
953 ++fetchIdleCycles;
954 } else if (fetchStatus[tid] == Blocked) {
955 ++fetchBlockedCycles;
956 } else if (fetchStatus[tid] == Squashing) {
957 ++fetchSquashCycles;
958 } else if (fetchStatus[tid] == IcacheWaitResponse) {
959 ++icacheStallCycles;
960 }
961
962 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
963 // fetch should do nothing.
964 return;
965 }
966
967 ++fetchCycles;
968
969 // If we had a stall due to an icache miss, then return.
970 if (fetchStatus[tid] == IcacheWaitResponse) {
971 ++icacheStallCycles;
972 status_change = true;
973 return;
974 }
975
976 Addr next_PC = fetch_PC;
977 InstSeqNum inst_seq;
978 MachInst inst;
979 ExtMachInst ext_inst;
980 // @todo: Fix this hack.
981 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
982
983 if (fault == NoFault) {
984 // If the read of the first instruction was successful, then grab the
985 // instructions from the rest of the cache line and put them into the
986 // queue heading to decode.
987
988 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
989 "decode.\n",tid);
990
991 // Need to keep track of whether or not a predicted branch
992 // ended this fetch block.
993 bool predicted_branch = false;
994
995 for (;
996 offset < cacheBlkSize &&
997 numInst < fetchWidth &&
998 !predicted_branch;
999 ++numInst) {
1000
1001 // Get a sequence number.
1002 inst_seq = cpu->getAndIncrementInstSeq();
1003
1004 // Make sure this is a valid index.
1005 assert(offset <= cacheBlkSize - instSize);
1006
1007 // Get the instruction from the array of the cache line.
1008 inst = gtoh(*reinterpret_cast<MachInst *>
1009 (&cacheData[tid][offset]));
1010
1011 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1012
1013 // Create a new DynInst from the instruction fetched.
1014 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1015 next_PC,
1016 inst_seq, cpu);
1017 instruction->setTid(tid);
1018
1019 instruction->setASID(tid);
1020
1021 instruction->setThreadState(cpu->thread[tid]);
1022
1023 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1024 "[sn:%lli]\n",
1025 tid, instruction->readPC(), inst_seq);
1026
1027 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1028 tid, instruction->staticInst->disassemble(fetch_PC));
1029
1030 instruction->traceData =
1031 Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
1032 instruction->staticInst,
1033 instruction->readPC(),tid);
1034
1035 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
1036
1037 // Add instruction to the CPU's list of instructions.
1038 instruction->setInstListIt(cpu->addInst(instruction));
1039
1040 // Write the instruction to the first slot in the queue
1041 // that heads to decode.
1042 toDecode->insts[numInst] = instruction;
1043
1044 toDecode->size++;
1045
1046 // Increment stat of fetched instructions.
1047 ++fetchedInsts;
1048
1049 // Move to the next instruction, unless we have a branch.
1050 fetch_PC = next_PC;
1051
1052 if (instruction->isQuiesce()) {
1053 warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
1054 curTick);
1055 fetchStatus[tid] = QuiescePending;
1056 ++numInst;
1057 status_change = true;
1058 break;
1059 }
1060
1061 offset+= instSize;
1062 }
1063 }
1064
1065 if (numInst > 0) {
1066 wroteToTimeBuffer = true;
1067 }
1068
1069 // Now that fetching is completed, update the PC to signify what the next
1070 // cycle will be.
1071 if (fault == NoFault) {
1072 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1073
1074#if THE_ISA == ALPHA_ISA
1075 PC[tid] = next_PC;
1076 nextPC[tid] = next_PC + instSize;
1077#else
1078 PC[tid] = next_PC;
1079 nextPC[tid] = next_PC + instSize;
1080 nextPC[tid] = next_PC + instSize;
1081
1082 thread->setNextPC(thread->readNextNPC());
1083 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
1084#endif
1085 } else {
1086 // We shouldn't be in an icache miss and also have a fault (an ITB
1087 // miss)
1088 if (fetchStatus[tid] == IcacheWaitResponse) {
1089 panic("Fetch should have exited prior to this!");
1090 }
1091
1092 // Send the fault to commit. This thread will not do anything
1093 // until commit handles the fault. The only other way it can
1094 // wake up is if a squash comes along and changes the PC.
1095#if FULL_SYSTEM
1096 assert(numInst != fetchWidth);
1097 // Get a sequence number.
1098 inst_seq = cpu->getAndIncrementInstSeq();
1099 // We will use a nop in order to carry the fault.
1100 ext_inst = TheISA::NoopMachInst;
1101
1102 // Create a new DynInst from the dummy nop.
1103 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1104 next_PC,
1105 inst_seq, cpu);
1106 instruction->setPredTarg(next_PC + instSize);
1107 instruction->setTid(tid);
1108
1109 instruction->setASID(tid);
1110
1111 instruction->setThreadState(cpu->thread[tid]);
1112
1113 instruction->traceData = NULL;
1114
1115 instruction->setInstListIt(cpu->addInst(instruction));
1116
1117 instruction->fault = fault;
1118
1119 toDecode->insts[numInst] = instruction;
1120 toDecode->size++;
1121
1122 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1123
1124 fetchStatus[tid] = TrapPending;
1125 status_change = true;
1126
1127 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1128#else // !FULL_SYSTEM
1129 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1130#endif // FULL_SYSTEM
1131 }
1132}
1133
1134template<class Impl>
1135void
1136DefaultFetch<Impl>::recvRetry()
1137{
1138 assert(cacheBlocked);
1139 if (retryPkt != NULL) {
1140 assert(retryTid != -1);
1141 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1142
1143 if (icachePort->sendTiming(retryPkt)) {
1144 fetchStatus[retryTid] = IcacheWaitResponse;
1145 retryPkt = NULL;
1146 retryTid = -1;
1147 cacheBlocked = false;
1148 }
1149 } else {
1150 assert(retryTid == -1);
1151 // Access has been squashed since it was sent out. Just clear
1152 // the cache being blocked.
1153 cacheBlocked = false;
1154 }
1155}
1156
1157///////////////////////////////////////
1158// //
1159// SMT FETCH POLICY MAINTAINED HERE //
1160// //
1161///////////////////////////////////////
1162template<class Impl>
1163int
1164DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1165{
1166 if (numThreads > 1) {
1167 switch (fetch_priority) {
1168
1169 case SingleThread:
1170 return 0;
1171
1172 case RoundRobin:
1173 return roundRobin();
1174
1175 case IQ:
1176 return iqCount();
1177
1178 case LSQ:
1179 return lsqCount();
1180
1181 case Branch:
1182 return branchCount();
1183
1184 default:
1185 return -1;
1186 }
1187 } else {
1188 int tid = *((*activeThreads).begin());
1189
1190 if (fetchStatus[tid] == Running ||
1191 fetchStatus[tid] == IcacheAccessComplete ||
1192 fetchStatus[tid] == Idle) {
1193 return tid;
1194 } else {
1195 return -1;
1196 }
1197 }
1198
1199}
1200
1201
1202template<class Impl>
1203int
1204DefaultFetch<Impl>::roundRobin()
1205{
1206 list<unsigned>::iterator pri_iter = priorityList.begin();
1207 list<unsigned>::iterator end = priorityList.end();
1208
1209 int high_pri;
1210
1211 while (pri_iter != end) {
1212 high_pri = *pri_iter;
1213
1214 assert(high_pri <= numThreads);
1215
1216 if (fetchStatus[high_pri] == Running ||
1217 fetchStatus[high_pri] == IcacheAccessComplete ||
1218 fetchStatus[high_pri] == Idle) {
1219
1220 priorityList.erase(pri_iter);
1221 priorityList.push_back(high_pri);
1222
1223 return high_pri;
1224 }
1225
1226 pri_iter++;
1227 }
1228
1229 return -1;
1230}
1231
1232template<class Impl>
1233int
1234DefaultFetch<Impl>::iqCount()
1235{
1236 priority_queue<unsigned> PQ;
1237
1238 list<unsigned>::iterator threads = (*activeThreads).begin();
1239
1240 while (threads != (*activeThreads).end()) {
1241 unsigned tid = *threads++;
1242
1243 PQ.push(fromIEW->iewInfo[tid].iqCount);
1244 }
1245
1246 while (!PQ.empty()) {
1247
1248 unsigned high_pri = PQ.top();
1249
1250 if (fetchStatus[high_pri] == Running ||
1251 fetchStatus[high_pri] == IcacheAccessComplete ||
1252 fetchStatus[high_pri] == Idle)
1253 return high_pri;
1254 else
1255 PQ.pop();
1256
1257 }
1258
1259 return -1;
1260}
1261
1262template<class Impl>
1263int
1264DefaultFetch<Impl>::lsqCount()
1265{
1266 priority_queue<unsigned> PQ;
1267
1268
1269 list<unsigned>::iterator threads = (*activeThreads).begin();
1270
1271 while (threads != (*activeThreads).end()) {
1272 unsigned tid = *threads++;
1273
1274 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1275 }
1276
1277 while (!PQ.empty()) {
1278
1279 unsigned high_pri = PQ.top();
1280
1281 if (fetchStatus[high_pri] == Running ||
1282 fetchStatus[high_pri] == IcacheAccessComplete ||
1283 fetchStatus[high_pri] == Idle)
1284 return high_pri;
1285 else
1286 PQ.pop();
1287
1288 }
1289
1290 return -1;
1291}
1292
1293template<class Impl>
1294int
1295DefaultFetch<Impl>::branchCount()
1296{
1297 list<unsigned>::iterator threads = (*activeThreads).begin();
1298 panic("Branch Count Fetch policy unimplemented\n");
1299 return *threads;
1300}
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