155 // Create space to buffer the cache line data, 156 // which may not hold the entire cache line. 157 fetchBuffer[tid] = new uint8_t[fetchBufferSize]; 158 } 159} 160 161template <class Impl> 162std::string 163DefaultFetch<Impl>::name() const 164{ 165 return cpu->name() + ".fetch"; 166} 167 168template <class Impl> 169void 170DefaultFetch<Impl>::regProbePoints() 171{ 172 ppFetch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Fetch"); 173} 174 175template <class Impl> 176void 177DefaultFetch<Impl>::regStats() 178{ 179 icacheStallCycles 180 .name(name() + ".icacheStallCycles") 181 .desc("Number of cycles fetch is stalled on an Icache miss") 182 .prereq(icacheStallCycles); 183 184 fetchedInsts 185 .name(name() + ".Insts") 186 .desc("Number of instructions fetch has processed") 187 .prereq(fetchedInsts); 188 189 fetchedBranches 190 .name(name() + ".Branches") 191 .desc("Number of branches that fetch encountered") 192 .prereq(fetchedBranches); 193 194 predictedBranches 195 .name(name() + ".predictedBranches") 196 .desc("Number of branches that fetch has predicted taken") 197 .prereq(predictedBranches); 198 199 fetchCycles 200 .name(name() + ".Cycles") 201 .desc("Number of cycles fetch has run and was not squashing or" 202 " blocked") 203 .prereq(fetchCycles); 204 205 fetchSquashCycles 206 .name(name() + ".SquashCycles") 207 .desc("Number of cycles fetch has spent squashing") 208 .prereq(fetchSquashCycles); 209 210 fetchTlbCycles 211 .name(name() + ".TlbCycles") 212 .desc("Number of cycles fetch has spent waiting for tlb") 213 .prereq(fetchTlbCycles); 214 215 fetchIdleCycles 216 .name(name() + ".IdleCycles") 217 .desc("Number of cycles fetch was idle") 218 .prereq(fetchIdleCycles); 219 220 fetchBlockedCycles 221 .name(name() + ".BlockedCycles") 222 .desc("Number of cycles fetch has spent blocked") 223 .prereq(fetchBlockedCycles); 224 225 fetchedCacheLines 226 .name(name() + ".CacheLines") 227 .desc("Number of cache lines fetched") 228 .prereq(fetchedCacheLines); 229 230 fetchMiscStallCycles 231 .name(name() + ".MiscStallCycles") 232 .desc("Number of cycles fetch has spent waiting on interrupts, or " 233 "bad addresses, or out of MSHRs") 234 .prereq(fetchMiscStallCycles); 235 236 fetchPendingDrainCycles 237 .name(name() + ".PendingDrainCycles") 238 .desc("Number of cycles fetch has spent waiting on pipes to drain") 239 .prereq(fetchPendingDrainCycles); 240 241 fetchNoActiveThreadStallCycles 242 .name(name() + ".NoActiveThreadStallCycles") 243 .desc("Number of stall cycles due to no active thread to fetch from") 244 .prereq(fetchNoActiveThreadStallCycles); 245 246 fetchPendingTrapStallCycles 247 .name(name() + ".PendingTrapStallCycles") 248 .desc("Number of stall cycles due to pending traps") 249 .prereq(fetchPendingTrapStallCycles); 250 251 fetchPendingQuiesceStallCycles 252 .name(name() + ".PendingQuiesceStallCycles") 253 .desc("Number of stall cycles due to pending quiesce instructions") 254 .prereq(fetchPendingQuiesceStallCycles); 255 256 fetchIcacheWaitRetryStallCycles 257 .name(name() + ".IcacheWaitRetryStallCycles") 258 .desc("Number of stall cycles due to full MSHR") 259 .prereq(fetchIcacheWaitRetryStallCycles); 260 261 fetchIcacheSquashes 262 .name(name() + ".IcacheSquashes") 263 .desc("Number of outstanding Icache misses that were squashed") 264 .prereq(fetchIcacheSquashes); 265 266 fetchTlbSquashes 267 .name(name() + ".ItlbSquashes") 268 .desc("Number of outstanding ITLB misses that were squashed") 269 .prereq(fetchTlbSquashes); 270 271 fetchNisnDist 272 .init(/* base value */ 0, 273 /* last value */ fetchWidth, 274 /* bucket size */ 1) 275 .name(name() + ".rateDist") 276 .desc("Number of instructions fetched each cycle (Total)") 277 .flags(Stats::pdf); 278 279 idleRate 280 .name(name() + ".idleRate") 281 .desc("Percent of cycles fetch was idle") 282 .prereq(idleRate); 283 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 284 285 branchRate 286 .name(name() + ".branchRate") 287 .desc("Number of branch fetches per cycle") 288 .flags(Stats::total); 289 branchRate = fetchedBranches / cpu->numCycles; 290 291 fetchRate 292 .name(name() + ".rate") 293 .desc("Number of inst fetches per cycle") 294 .flags(Stats::total); 295 fetchRate = fetchedInsts / cpu->numCycles; 296} 297 298template<class Impl> 299void 300DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 301{ 302 timeBuffer = time_buffer; 303 304 // Create wires to get information from proper places in time buffer. 305 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 306 fromRename = timeBuffer->getWire(-renameToFetchDelay); 307 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 308 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 309} 310 311template<class Impl> 312void 313DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 314{ 315 activeThreads = at_ptr; 316} 317 318template<class Impl> 319void 320DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *ftb_ptr) 321{ 322 // Create wire to write information to proper place in fetch time buf. 323 toDecode = ftb_ptr->getWire(0); 324} 325 326template<class Impl> 327void 328DefaultFetch<Impl>::startupStage() 329{ 330 assert(priorityList.empty()); 331 resetStage(); 332 333 // Fetch needs to start fetching instructions at the very beginning, 334 // so it must start up in active state. 335 switchToActive(); 336} 337 338template<class Impl> 339void 340DefaultFetch<Impl>::resetStage() 341{ 342 numInst = 0; 343 interruptPending = false; 344 cacheBlocked = false; 345 346 priorityList.clear(); 347 348 // Setup PC and nextPC with initial state. 349 for (ThreadID tid = 0; tid < numThreads; ++tid) { 350 fetchStatus[tid] = Running; 351 pc[tid] = cpu->pcState(tid); 352 fetchOffset[tid] = 0; 353 macroop[tid] = NULL; 354 355 delayedCommit[tid] = false; 356 memReq[tid] = NULL; 357 358 stalls[tid].decode = false; 359 stalls[tid].drain = false; 360 361 fetchBufferPC[tid] = 0; 362 fetchBufferValid[tid] = false; 363 364 fetchQueue[tid].clear(); 365 366 priorityList.push_back(tid); 367 } 368 369 wroteToTimeBuffer = false; 370 _status = Inactive; 371} 372 373template<class Impl> 374void 375DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 376{ 377 ThreadID tid = pkt->req->threadId(); 378 379 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 380 assert(!cpu->switchedOut()); 381 382 // Only change the status if it's still waiting on the icache access 383 // to return. 384 if (fetchStatus[tid] != IcacheWaitResponse || 385 pkt->req != memReq[tid]) { 386 ++fetchIcacheSquashes; 387 delete pkt->req; 388 delete pkt; 389 return; 390 } 391 392 memcpy(fetchBuffer[tid], pkt->getConstPtr<uint8_t>(), fetchBufferSize); 393 fetchBufferValid[tid] = true; 394 395 // Wake up the CPU (if it went to sleep and was waiting on 396 // this completion event). 397 cpu->wakeCPU(); 398 399 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 400 tid); 401 402 switchToActive(); 403 404 // Only switch to IcacheAccessComplete if we're not stalled as well. 405 if (checkStall(tid)) { 406 fetchStatus[tid] = Blocked; 407 } else { 408 fetchStatus[tid] = IcacheAccessComplete; 409 } 410 411 pkt->req->setAccessLatency(); 412 cpu->ppInstAccessComplete->notify(pkt); 413 // Reset the mem req to NULL. 414 delete pkt->req; 415 delete pkt; 416 memReq[tid] = NULL; 417} 418 419template <class Impl> 420void 421DefaultFetch<Impl>::drainResume() 422{ 423 for (ThreadID i = 0; i < numThreads; ++i) 424 stalls[i].drain = false; 425} 426 427template <class Impl> 428void 429DefaultFetch<Impl>::drainSanityCheck() const 430{ 431 assert(isDrained()); 432 assert(retryPkt == NULL); 433 assert(retryTid == InvalidThreadID); 434 assert(!cacheBlocked); 435 assert(!interruptPending); 436 437 for (ThreadID i = 0; i < numThreads; ++i) { 438 assert(!memReq[i]); 439 assert(fetchStatus[i] == Idle || stalls[i].drain); 440 } 441 442 branchPred->drainSanityCheck(); 443} 444 445template <class Impl> 446bool 447DefaultFetch<Impl>::isDrained() const 448{ 449 /* Make sure that threads are either idle of that the commit stage 450 * has signaled that draining has completed by setting the drain 451 * stall flag. This effectively forces the pipeline to be disabled 452 * until the whole system is drained (simulation may continue to 453 * drain other components). 454 */ 455 for (ThreadID i = 0; i < numThreads; ++i) { 456 // Verify fetch queues are drained 457 if (!fetchQueue[i].empty()) 458 return false; 459 460 // Return false if not idle or drain stalled 461 if (fetchStatus[i] != Idle) { 462 if (fetchStatus[i] == Blocked && stalls[i].drain) 463 continue; 464 else 465 return false; 466 } 467 } 468 469 /* The pipeline might start up again in the middle of the drain 470 * cycle if the finish translation event is scheduled, so make 471 * sure that's not the case. 472 */ 473 return !finishTranslationEvent.scheduled(); 474} 475 476template <class Impl> 477void 478DefaultFetch<Impl>::takeOverFrom() 479{ 480 assert(cpu->getInstPort().isConnected()); 481 resetStage(); 482 483} 484 485template <class Impl> 486void 487DefaultFetch<Impl>::drainStall(ThreadID tid) 488{ 489 assert(cpu->isDraining()); 490 assert(!stalls[tid].drain); 491 DPRINTF(Drain, "%i: Thread drained.\n", tid); 492 stalls[tid].drain = true; 493} 494 495template <class Impl> 496void 497DefaultFetch<Impl>::wakeFromQuiesce() 498{ 499 DPRINTF(Fetch, "Waking up from quiesce\n"); 500 // Hopefully this is safe 501 // @todo: Allow other threads to wake from quiesce. 502 fetchStatus[0] = Running; 503} 504 505template <class Impl> 506inline void 507DefaultFetch<Impl>::switchToActive() 508{ 509 if (_status == Inactive) { 510 DPRINTF(Activity, "Activating stage.\n"); 511 512 cpu->activateStage(O3CPU::FetchIdx); 513 514 _status = Active; 515 } 516} 517 518template <class Impl> 519inline void 520DefaultFetch<Impl>::switchToInactive() 521{ 522 if (_status == Active) { 523 DPRINTF(Activity, "Deactivating stage.\n"); 524 525 cpu->deactivateStage(O3CPU::FetchIdx); 526 527 _status = Inactive; 528 } 529} 530 531template <class Impl> 532void 533DefaultFetch<Impl>::deactivateThread(ThreadID tid) 534{ 535 // Update priority list 536 auto thread_it = std::find(priorityList.begin(), priorityList.end(), tid); 537 if (thread_it != priorityList.end()) { 538 priorityList.erase(thread_it); 539 } 540} 541 542template <class Impl> 543bool 544DefaultFetch<Impl>::lookupAndUpdateNextPC( 545 DynInstPtr &inst, TheISA::PCState &nextPC) 546{ 547 // Do branch prediction check here. 548 // A bit of a misnomer...next_PC is actually the current PC until 549 // this function updates it. 550 bool predict_taken; 551 552 if (!inst->isControl()) { 553 TheISA::advancePC(nextPC, inst->staticInst); 554 inst->setPredTarg(nextPC); 555 inst->setPredTaken(false); 556 return false; 557 } 558 559 ThreadID tid = inst->threadNumber; 560 predict_taken = branchPred->predict(inst->staticInst, inst->seqNum, 561 nextPC, tid); 562 563 if (predict_taken) { 564 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 565 tid, inst->seqNum, nextPC); 566 } else { 567 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 568 tid, inst->seqNum); 569 } 570 571 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 572 tid, inst->seqNum, nextPC); 573 inst->setPredTarg(nextPC); 574 inst->setPredTaken(predict_taken); 575 576 ++fetchedBranches; 577 578 if (predict_taken) { 579 ++predictedBranches; 580 } 581 582 return predict_taken; 583} 584 585template <class Impl> 586bool 587DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) 588{ 589 Fault fault = NoFault; 590 591 assert(!cpu->switchedOut()); 592 593 // @todo: not sure if these should block translation. 594 //AlphaDep 595 if (cacheBlocked) { 596 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 597 tid); 598 return false; 599 } else if (checkInterrupt(pc) && !delayedCommit[tid]) { 600 // Hold off fetch from getting new instructions when: 601 // Cache is blocked, or 602 // while an interrupt is pending and we're not in PAL mode, or 603 // fetch is switched out. 604 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 605 tid); 606 return false; 607 } 608 609 // Align the fetch address to the start of a fetch buffer segment. 610 Addr fetchBufferBlockPC = fetchBufferAlignPC(vaddr); 611 612 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n", 613 tid, fetchBufferBlockPC, vaddr); 614 615 // Setup the memReq to do a read of the first instruction's address. 616 // Set the appropriate read size and flags as well. 617 // Build request here. 618 RequestPtr mem_req = 619 new Request(tid, fetchBufferBlockPC, fetchBufferSize, 620 Request::INST_FETCH, cpu->instMasterId(), pc, 621 cpu->thread[tid]->contextId(), tid); 622 623 mem_req->taskId(cpu->taskId()); 624 625 memReq[tid] = mem_req; 626 627 // Initiate translation of the icache block 628 fetchStatus[tid] = ItlbWait; 629 FetchTranslation *trans = new FetchTranslation(this); 630 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(), 631 trans, BaseTLB::Execute); 632 return true; 633} 634 635template <class Impl> 636void 637DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req) 638{ 639 ThreadID tid = mem_req->threadId(); 640 Addr fetchBufferBlockPC = mem_req->getVaddr(); 641 642 assert(!cpu->switchedOut()); 643 644 // Wake up CPU if it was idle 645 cpu->wakeCPU(); 646 647 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] || 648 mem_req->getVaddr() != memReq[tid]->getVaddr()) { 649 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n", 650 tid); 651 ++fetchTlbSquashes; 652 delete mem_req; 653 return; 654 } 655 656 657 // If translation was successful, attempt to read the icache block. 658 if (fault == NoFault) { 659 // Check that we're not going off into random memory 660 // If we have, just wait around for commit to squash something and put 661 // us on the right track 662 if (!cpu->system->isMemAddr(mem_req->getPaddr())) { 663 warn("Address %#x is outside of physical memory, stopping fetch\n", 664 mem_req->getPaddr()); 665 fetchStatus[tid] = NoGoodAddr; 666 delete mem_req; 667 memReq[tid] = NULL; 668 return; 669 } 670 671 // Build packet here. 672 PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq); 673 data_pkt->dataDynamic(new uint8_t[fetchBufferSize]); 674 675 fetchBufferPC[tid] = fetchBufferBlockPC; 676 fetchBufferValid[tid] = false; 677 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 678 679 fetchedCacheLines++; 680 681 // Access the cache. 682 if (!cpu->getInstPort().sendTimingReq(data_pkt)) { 683 assert(retryPkt == NULL); 684 assert(retryTid == InvalidThreadID); 685 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 686 687 fetchStatus[tid] = IcacheWaitRetry; 688 retryPkt = data_pkt; 689 retryTid = tid; 690 cacheBlocked = true; 691 } else { 692 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid); 693 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 694 "response.\n", tid); 695 lastIcacheStall[tid] = curTick(); 696 fetchStatus[tid] = IcacheWaitResponse; 697 } 698 } else { 699 // Don't send an instruction to decode if we can't handle it. 700 if (!(numInst < fetchWidth) || !(fetchQueue[tid].size() < fetchQueueSize)) { 701 assert(!finishTranslationEvent.scheduled()); 702 finishTranslationEvent.setFault(fault); 703 finishTranslationEvent.setReq(mem_req); 704 cpu->schedule(finishTranslationEvent, 705 cpu->clockEdge(Cycles(1))); 706 return; 707 } 708 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n", 709 tid, mem_req->getVaddr(), memReq[tid]->getVaddr()); 710 // Translation faulted, icache request won't be sent. 711 delete mem_req; 712 memReq[tid] = NULL; 713 714 // Send the fault to commit. This thread will not do anything 715 // until commit handles the fault. The only other way it can 716 // wake up is if a squash comes along and changes the PC. 717 TheISA::PCState fetchPC = pc[tid]; 718 719 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid); 720 // We will use a nop in ordier to carry the fault. 721 DynInstPtr instruction = buildInst(tid, 722 decoder[tid]->decode(TheISA::NoopMachInst, fetchPC.instAddr()), 723 NULL, fetchPC, fetchPC, false); 724 725 instruction->setPredTarg(fetchPC); 726 instruction->fault = fault; 727 wroteToTimeBuffer = true; 728 729 DPRINTF(Activity, "Activity this cycle.\n"); 730 cpu->activityThisCycle(); 731 732 fetchStatus[tid] = TrapPending; 733 734 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); 735 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n", 736 tid, fault->name(), pc[tid]); 737 } 738 _status = updateFetchStatus(); 739} 740 741template <class Impl> 742inline void 743DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, 744 const DynInstPtr squashInst, ThreadID tid) 745{ 746 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 747 tid, newPC); 748 749 pc[tid] = newPC; 750 fetchOffset[tid] = 0; 751 if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr()) 752 macroop[tid] = squashInst->macroop; 753 else 754 macroop[tid] = NULL; 755 decoder[tid]->reset(); 756 757 // Clear the icache miss if it's outstanding. 758 if (fetchStatus[tid] == IcacheWaitResponse) { 759 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 760 tid); 761 memReq[tid] = NULL; 762 } else if (fetchStatus[tid] == ItlbWait) { 763 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n", 764 tid); 765 memReq[tid] = NULL; 766 } 767 768 // Get rid of the retrying packet if it was from this thread. 769 if (retryTid == tid) { 770 assert(cacheBlocked); 771 if (retryPkt) { 772 delete retryPkt->req; 773 delete retryPkt; 774 } 775 retryPkt = NULL; 776 retryTid = InvalidThreadID; 777 } 778 779 fetchStatus[tid] = Squashing; 780 781 // Empty fetch queue 782 fetchQueue[tid].clear(); 783 784 // microops are being squashed, it is not known wheather the 785 // youngest non-squashed microop was marked delayed commit 786 // or not. Setting the flag to true ensures that the 787 // interrupts are not handled when they cannot be, though 788 // some opportunities to handle interrupts may be missed. 789 delayedCommit[tid] = true; 790 791 ++fetchSquashCycles; 792} 793 794template<class Impl> 795void 796DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 797 const DynInstPtr squashInst, 798 const InstSeqNum seq_num, ThreadID tid) 799{ 800 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); 801 802 doSquash(newPC, squashInst, tid); 803 804 // Tell the CPU to remove any instructions that are in flight between 805 // fetch and decode. 806 cpu->removeInstsUntil(seq_num, tid); 807} 808 809template<class Impl> 810bool 811DefaultFetch<Impl>::checkStall(ThreadID tid) const 812{ 813 bool ret_val = false; 814 815 if (stalls[tid].drain) { 816 assert(cpu->isDraining()); 817 DPRINTF(Fetch,"[tid:%i]: Drain stall detected.\n",tid); 818 ret_val = true; 819 } 820 821 return ret_val; 822} 823 824template<class Impl> 825typename DefaultFetch<Impl>::FetchStatus 826DefaultFetch<Impl>::updateFetchStatus() 827{ 828 //Check Running 829 list<ThreadID>::iterator threads = activeThreads->begin(); 830 list<ThreadID>::iterator end = activeThreads->end(); 831 832 while (threads != end) { 833 ThreadID tid = *threads++; 834 835 if (fetchStatus[tid] == Running || 836 fetchStatus[tid] == Squashing || 837 fetchStatus[tid] == IcacheAccessComplete) { 838 839 if (_status == Inactive) { 840 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 841 842 if (fetchStatus[tid] == IcacheAccessComplete) { 843 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 844 "completion\n",tid); 845 } 846 847 cpu->activateStage(O3CPU::FetchIdx); 848 } 849 850 return Active; 851 } 852 } 853 854 // Stage is switching from active to inactive, notify CPU of it. 855 if (_status == Active) { 856 DPRINTF(Activity, "Deactivating stage.\n"); 857 858 cpu->deactivateStage(O3CPU::FetchIdx); 859 } 860 861 return Inactive; 862} 863 864template <class Impl> 865void 866DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 867 const InstSeqNum seq_num, DynInstPtr squashInst, 868 ThreadID tid) 869{ 870 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); 871 872 doSquash(newPC, squashInst, tid); 873 874 // Tell the CPU to remove any instructions that are not in the ROB. 875 cpu->removeInstsNotInROB(tid); 876} 877 878template <class Impl> 879void 880DefaultFetch<Impl>::tick() 881{ 882 list<ThreadID>::iterator threads = activeThreads->begin(); 883 list<ThreadID>::iterator end = activeThreads->end(); 884 bool status_change = false; 885 886 wroteToTimeBuffer = false; 887 888 for (ThreadID i = 0; i < numThreads; ++i) { 889 issuePipelinedIfetch[i] = false; 890 } 891 892 while (threads != end) { 893 ThreadID tid = *threads++; 894 895 // Check the signals for each thread to determine the proper status 896 // for each thread. 897 bool updated_status = checkSignalsAndUpdate(tid); 898 status_change = status_change || updated_status; 899 } 900 901 DPRINTF(Fetch, "Running stage.\n"); 902 903 if (FullSystem) { 904 if (fromCommit->commitInfo[0].interruptPending) { 905 interruptPending = true; 906 } 907 908 if (fromCommit->commitInfo[0].clearInterrupt) { 909 interruptPending = false; 910 } 911 } 912 913 for (threadFetched = 0; threadFetched < numFetchingThreads; 914 threadFetched++) { 915 // Fetch each of the actively fetching threads. 916 fetch(status_change); 917 } 918 919 // Record number of instructions fetched this cycle for distribution. 920 fetchNisnDist.sample(numInst); 921 922 if (status_change) { 923 // Change the fetch stage status if there was a status change. 924 _status = updateFetchStatus(); 925 } 926 927 // Issue the next I-cache request if possible. 928 for (ThreadID i = 0; i < numThreads; ++i) { 929 if (issuePipelinedIfetch[i]) { 930 pipelineIcacheAccesses(i); 931 } 932 } 933 934 // Send instructions enqueued into the fetch queue to decode. 935 // Limit rate by fetchWidth. Stall if decode is stalled. 936 unsigned insts_to_decode = 0; 937 unsigned available_insts = 0; 938 939 for (auto tid : *activeThreads) { 940 if (!stalls[tid].decode) { 941 available_insts += fetchQueue[tid].size(); 942 } 943 } 944 945 // Pick a random thread to start trying to grab instructions from 946 auto tid_itr = activeThreads->begin(); 947 std::advance(tid_itr, random_mt.random<uint8_t>(0, activeThreads->size() - 1)); 948 949 while (available_insts != 0 && insts_to_decode < decodeWidth) { 950 ThreadID tid = *tid_itr; 951 if (!stalls[tid].decode && !fetchQueue[tid].empty()) { 952 auto inst = fetchQueue[tid].front(); 953 toDecode->insts[toDecode->size++] = inst; 954 DPRINTF(Fetch, "[tid:%i][sn:%i]: Sending instruction to decode from " 955 "fetch queue. Fetch queue size: %i.\n", 956 tid, inst->seqNum, fetchQueue[tid].size()); 957 958 wroteToTimeBuffer = true; 959 fetchQueue[tid].pop_front(); 960 insts_to_decode++; 961 available_insts--; 962 } 963 964 tid_itr++; 965 // Wrap around if at end of active threads list 966 if (tid_itr == activeThreads->end()) 967 tid_itr = activeThreads->begin(); 968 } 969 970 // If there was activity this cycle, inform the CPU of it. 971 if (wroteToTimeBuffer) { 972 DPRINTF(Activity, "Activity this cycle.\n"); 973 cpu->activityThisCycle(); 974 } 975 976 // Reset the number of the instruction we've fetched. 977 numInst = 0; 978} 979 980template <class Impl> 981bool 982DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 983{ 984 // Update the per thread stall statuses. 985 if (fromDecode->decodeBlock[tid]) { 986 stalls[tid].decode = true; 987 } 988 989 if (fromDecode->decodeUnblock[tid]) { 990 assert(stalls[tid].decode); 991 assert(!fromDecode->decodeBlock[tid]); 992 stalls[tid].decode = false; 993 } 994 995 // Check squash signals from commit. 996 if (fromCommit->commitInfo[tid].squash) { 997 998 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 999 "from commit.\n",tid); 1000 // In any case, squash. 1001 squash(fromCommit->commitInfo[tid].pc, 1002 fromCommit->commitInfo[tid].doneSeqNum, 1003 fromCommit->commitInfo[tid].squashInst, tid); 1004 1005 // If it was a branch mispredict on a control instruction, update the 1006 // branch predictor with that instruction, otherwise just kill the 1007 // invalid state we generated in after sequence number 1008 if (fromCommit->commitInfo[tid].mispredictInst && 1009 fromCommit->commitInfo[tid].mispredictInst->isControl()) { 1010 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum, 1011 fromCommit->commitInfo[tid].pc, 1012 fromCommit->commitInfo[tid].branchTaken, 1013 tid); 1014 } else { 1015 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum, 1016 tid); 1017 } 1018 1019 return true; 1020 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 1021 // Update the branch predictor if it wasn't a squashed instruction 1022 // that was broadcasted. 1023 branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid); 1024 } 1025 1026 // Check squash signals from decode. 1027 if (fromDecode->decodeInfo[tid].squash) { 1028 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 1029 "from decode.\n",tid); 1030 1031 // Update the branch predictor. 1032 if (fromDecode->decodeInfo[tid].branchMispredict) { 1033 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum, 1034 fromDecode->decodeInfo[tid].nextPC, 1035 fromDecode->decodeInfo[tid].branchTaken, 1036 tid); 1037 } else { 1038 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum, 1039 tid); 1040 } 1041 1042 if (fetchStatus[tid] != Squashing) { 1043 1044 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", 1045 fromDecode->decodeInfo[tid].nextPC); 1046 // Squash unless we're already squashing 1047 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 1048 fromDecode->decodeInfo[tid].squashInst, 1049 fromDecode->decodeInfo[tid].doneSeqNum, 1050 tid); 1051 1052 return true; 1053 } 1054 } 1055 1056 if (checkStall(tid) && 1057 fetchStatus[tid] != IcacheWaitResponse && 1058 fetchStatus[tid] != IcacheWaitRetry && 1059 fetchStatus[tid] != ItlbWait && 1060 fetchStatus[tid] != QuiescePending) { 1061 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 1062 1063 fetchStatus[tid] = Blocked; 1064 1065 return true; 1066 } 1067 1068 if (fetchStatus[tid] == Blocked || 1069 fetchStatus[tid] == Squashing) { 1070 // Switch status to running if fetch isn't being told to block or 1071 // squash this cycle. 1072 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 1073 tid); 1074 1075 fetchStatus[tid] = Running; 1076 1077 return true; 1078 } 1079 1080 // If we've reached this point, we have not gotten any signals that 1081 // cause fetch to change its status. Fetch remains the same as before. 1082 return false; 1083} 1084 1085template<class Impl> 1086typename Impl::DynInstPtr 1087DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 1088 StaticInstPtr curMacroop, TheISA::PCState thisPC, 1089 TheISA::PCState nextPC, bool trace) 1090{ 1091 // Get a sequence number. 1092 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 1093 1094 // Create a new DynInst from the instruction fetched. 1095 DynInstPtr instruction = 1096 new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu); 1097 instruction->setTid(tid); 1098 1099 instruction->setASID(tid); 1100 1101 instruction->setThreadState(cpu->thread[tid]); 1102 1103 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " 1104 "[sn:%lli].\n", tid, thisPC.instAddr(), 1105 thisPC.microPC(), seq); 1106 1107 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 1108 instruction->staticInst-> 1109 disassemble(thisPC.instAddr())); 1110 1111#if TRACING_ON 1112 if (trace) { 1113 instruction->traceData = 1114 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1115 instruction->staticInst, thisPC, curMacroop); 1116 } 1117#else 1118 instruction->traceData = NULL; 1119#endif 1120 1121 // Add instruction to the CPU's list of instructions. 1122 instruction->setInstListIt(cpu->addInst(instruction)); 1123 1124 // Write the instruction to the first slot in the queue 1125 // that heads to decode. 1126 assert(numInst < fetchWidth); 1127 fetchQueue[tid].push_back(instruction); 1128 assert(fetchQueue[tid].size() <= fetchQueueSize); 1129 DPRINTF(Fetch, "[tid:%i]: Fetch queue entry created (%i/%i).\n", 1130 tid, fetchQueue[tid].size(), fetchQueueSize); 1131 //toDecode->insts[toDecode->size++] = instruction; 1132 1133 // Keep track of if we can take an interrupt at this boundary 1134 delayedCommit[tid] = instruction->isDelayedCommit(); 1135 1136 return instruction; 1137} 1138 1139template<class Impl> 1140void 1141DefaultFetch<Impl>::fetch(bool &status_change) 1142{ 1143 ////////////////////////////////////////// 1144 // Start actual fetch 1145 ////////////////////////////////////////// 1146 ThreadID tid = getFetchingThread(fetchPolicy); 1147 1148 assert(!cpu->switchedOut()); 1149 1150 if (tid == InvalidThreadID) { 1151 // Breaks looping condition in tick() 1152 threadFetched = numFetchingThreads; 1153 1154 if (numThreads == 1) { // @todo Per-thread stats 1155 profileStall(0); 1156 } 1157 1158 return; 1159 } 1160 1161 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1162 1163 // The current PC. 1164 TheISA::PCState thisPC = pc[tid]; 1165 1166 Addr pcOffset = fetchOffset[tid]; 1167 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1168 1169 bool inRom = isRomMicroPC(thisPC.microPC()); 1170 1171 // If returning from the delay of a cache miss, then update the status 1172 // to running, otherwise do the cache access. Possibly move this up 1173 // to tick() function. 1174 if (fetchStatus[tid] == IcacheAccessComplete) { 1175 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid); 1176 1177 fetchStatus[tid] = Running; 1178 status_change = true; 1179 } else if (fetchStatus[tid] == Running) { 1180 // Align the fetch PC so its at the start of a fetch buffer segment. 1181 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1182 1183 // If buffer is no longer valid or fetchAddr has moved to point 1184 // to the next cache block, AND we have no remaining ucode 1185 // from a macro-op, then start fetch from icache. 1186 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid]) 1187 && !inRom && !macroop[tid]) { 1188 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1189 "instruction, starting at PC %s.\n", tid, thisPC); 1190 1191 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1192 1193 if (fetchStatus[tid] == IcacheWaitResponse) 1194 ++icacheStallCycles; 1195 else if (fetchStatus[tid] == ItlbWait) 1196 ++fetchTlbCycles; 1197 else 1198 ++fetchMiscStallCycles; 1199 return; 1200 } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])) { 1201 // Stall CPU if an interrupt is posted and we're not issuing 1202 // an delayed commit micro-op currently (delayed commit instructions 1203 // are not interruptable by interrupts, only faults) 1204 ++fetchMiscStallCycles; 1205 DPRINTF(Fetch, "[tid:%i]: Fetch is stalled!\n", tid); 1206 return; 1207 } 1208 } else { 1209 if (fetchStatus[tid] == Idle) { 1210 ++fetchIdleCycles; 1211 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1212 } 1213 1214 // Status is Idle, so fetch should do nothing. 1215 return; 1216 } 1217 1218 ++fetchCycles; 1219 1220 TheISA::PCState nextPC = thisPC; 1221 1222 StaticInstPtr staticInst = NULL; 1223 StaticInstPtr curMacroop = macroop[tid]; 1224 1225 // If the read of the first instruction was successful, then grab the 1226 // instructions from the rest of the cache line and put them into the 1227 // queue heading to decode. 1228 1229 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1230 "decode.\n", tid); 1231 1232 // Need to keep track of whether or not a predicted branch 1233 // ended this fetch block. 1234 bool predictedBranch = false; 1235 1236 // Need to halt fetch if quiesce instruction detected 1237 bool quiesce = false; 1238 1239 TheISA::MachInst *cacheInsts = 1240 reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]); 1241 1242 const unsigned numInsts = fetchBufferSize / instSize; 1243 unsigned blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize; 1244 1245 // Loop through instruction memory from the cache. 1246 // Keep issuing while fetchWidth is available and branch is not 1247 // predicted taken 1248 while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize 1249 && !predictedBranch && !quiesce) { 1250 // We need to process more memory if we aren't going to get a 1251 // StaticInst from the rom, the current macroop, or what's already 1252 // in the decoder. 1253 bool needMem = !inRom && !curMacroop && 1254 !decoder[tid]->instReady(); 1255 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1256 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1257 1258 if (needMem) { 1259 // If buffer is no longer valid or fetchAddr has moved to point 1260 // to the next cache block then start fetch from icache. 1261 if (!fetchBufferValid[tid] || 1262 fetchBufferBlockPC != fetchBufferPC[tid]) 1263 break; 1264 1265 if (blkOffset >= numInsts) { 1266 // We need to process more memory, but we've run out of the 1267 // current block. 1268 break; 1269 } 1270 1271 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { 1272 // Walk past any annulled delay slot instructions. 1273 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; 1274 while (fetchAddr != pcAddr && blkOffset < numInsts) { 1275 blkOffset++; 1276 fetchAddr += instSize; 1277 } 1278 if (blkOffset >= numInsts) 1279 break; 1280 } 1281 1282 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1283 decoder[tid]->moreBytes(thisPC, fetchAddr, inst); 1284 1285 if (decoder[tid]->needMoreBytes()) { 1286 blkOffset++; 1287 fetchAddr += instSize; 1288 pcOffset += instSize; 1289 } 1290 } 1291 1292 // Extract as many instructions and/or microops as we can from 1293 // the memory we've processed so far. 1294 do { 1295 if (!(curMacroop || inRom)) { 1296 if (decoder[tid]->instReady()) { 1297 staticInst = decoder[tid]->decode(thisPC); 1298 1299 // Increment stat of fetched instructions. 1300 ++fetchedInsts; 1301 1302 if (staticInst->isMacroop()) { 1303 curMacroop = staticInst; 1304 } else { 1305 pcOffset = 0; 1306 } 1307 } else { 1308 // We need more bytes for this instruction so blkOffset and 1309 // pcOffset will be updated 1310 break; 1311 } 1312 } 1313 // Whether we're moving to a new macroop because we're at the 1314 // end of the current one, or the branch predictor incorrectly 1315 // thinks we are... 1316 bool newMacro = false; 1317 if (curMacroop || inRom) { 1318 if (inRom) { 1319 staticInst = cpu->microcodeRom.fetchMicroop( 1320 thisPC.microPC(), curMacroop); 1321 } else { 1322 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1323 } 1324 newMacro |= staticInst->isLastMicroop(); 1325 } 1326 1327 DynInstPtr instruction = 1328 buildInst(tid, staticInst, curMacroop, 1329 thisPC, nextPC, true); 1330 1331 ppFetch->notify(instruction); 1332 numInst++; 1333 1334#if TRACING_ON 1335 if (DTRACE(O3PipeView)) { 1336 instruction->fetchTick = curTick(); 1337 } 1338#endif 1339 1340 nextPC = thisPC; 1341 1342 // If we're branching after this instruction, quit fetching 1343 // from the same block. 1344 predictedBranch |= thisPC.branching(); 1345 predictedBranch |= 1346 lookupAndUpdateNextPC(instruction, nextPC); 1347 if (predictedBranch) { 1348 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1349 } 1350 1351 newMacro |= thisPC.instAddr() != nextPC.instAddr(); 1352 1353 // Move to the next instruction, unless we have a branch. 1354 thisPC = nextPC; 1355 inRom = isRomMicroPC(thisPC.microPC()); 1356 1357 if (newMacro) { 1358 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask; 1359 blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize; 1360 pcOffset = 0; 1361 curMacroop = NULL; 1362 } 1363 1364 if (instruction->isQuiesce()) { 1365 DPRINTF(Fetch, 1366 "Quiesce instruction encountered, halting fetch!\n"); 1367 fetchStatus[tid] = QuiescePending; 1368 status_change = true; 1369 quiesce = true; 1370 break; 1371 } 1372 } while ((curMacroop || decoder[tid]->instReady()) && 1373 numInst < fetchWidth && 1374 fetchQueue[tid].size() < fetchQueueSize); 1375 1376 // Re-evaluate whether the next instruction to fetch is in micro-op ROM 1377 // or not. 1378 inRom = isRomMicroPC(thisPC.microPC()); 1379 } 1380 1381 if (predictedBranch) { 1382 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1383 "instruction encountered.\n", tid); 1384 } else if (numInst >= fetchWidth) { 1385 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1386 "for this cycle.\n", tid); 1387 } else if (blkOffset >= fetchBufferSize) { 1388 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of the" 1389 "fetch buffer.\n", tid); 1390 } 1391 1392 macroop[tid] = curMacroop; 1393 fetchOffset[tid] = pcOffset; 1394 1395 if (numInst > 0) { 1396 wroteToTimeBuffer = true; 1397 } 1398 1399 pc[tid] = thisPC; 1400 1401 // pipeline a fetch if we're crossing a fetch buffer boundary and not in 1402 // a state that would preclude fetching 1403 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1404 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1405 issuePipelinedIfetch[tid] = fetchBufferBlockPC != fetchBufferPC[tid] && 1406 fetchStatus[tid] != IcacheWaitResponse && 1407 fetchStatus[tid] != ItlbWait && 1408 fetchStatus[tid] != IcacheWaitRetry && 1409 fetchStatus[tid] != QuiescePending && 1410 !curMacroop; 1411} 1412 1413template<class Impl> 1414void 1415DefaultFetch<Impl>::recvReqRetry() 1416{ 1417 if (retryPkt != NULL) { 1418 assert(cacheBlocked); 1419 assert(retryTid != InvalidThreadID); 1420 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1421 1422 if (cpu->getInstPort().sendTimingReq(retryPkt)) { 1423 fetchStatus[retryTid] = IcacheWaitResponse; 1424 retryPkt = NULL; 1425 retryTid = InvalidThreadID; 1426 cacheBlocked = false; 1427 } 1428 } else { 1429 assert(retryTid == InvalidThreadID); 1430 // Access has been squashed since it was sent out. Just clear 1431 // the cache being blocked. 1432 cacheBlocked = false; 1433 } 1434} 1435 1436/////////////////////////////////////// 1437// // 1438// SMT FETCH POLICY MAINTAINED HERE // 1439// // 1440/////////////////////////////////////// 1441template<class Impl> 1442ThreadID 1443DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1444{ 1445 if (numThreads > 1) { 1446 switch (fetch_priority) { 1447 1448 case SingleThread: 1449 return 0; 1450 1451 case RoundRobin: 1452 return roundRobin(); 1453 1454 case IQ: 1455 return iqCount(); 1456 1457 case LSQ: 1458 return lsqCount(); 1459 1460 case Branch: 1461 return branchCount(); 1462 1463 default: 1464 return InvalidThreadID; 1465 } 1466 } else { 1467 list<ThreadID>::iterator thread = activeThreads->begin(); 1468 if (thread == activeThreads->end()) { 1469 return InvalidThreadID; 1470 } 1471 1472 ThreadID tid = *thread; 1473 1474 if (fetchStatus[tid] == Running || 1475 fetchStatus[tid] == IcacheAccessComplete || 1476 fetchStatus[tid] == Idle) { 1477 return tid; 1478 } else { 1479 return InvalidThreadID; 1480 } 1481 } 1482} 1483 1484 1485template<class Impl> 1486ThreadID 1487DefaultFetch<Impl>::roundRobin() 1488{ 1489 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1490 list<ThreadID>::iterator end = priorityList.end(); 1491 1492 ThreadID high_pri; 1493 1494 while (pri_iter != end) { 1495 high_pri = *pri_iter; 1496 1497 assert(high_pri <= numThreads); 1498 1499 if (fetchStatus[high_pri] == Running || 1500 fetchStatus[high_pri] == IcacheAccessComplete || 1501 fetchStatus[high_pri] == Idle) { 1502 1503 priorityList.erase(pri_iter); 1504 priorityList.push_back(high_pri); 1505 1506 return high_pri; 1507 } 1508 1509 pri_iter++; 1510 } 1511 1512 return InvalidThreadID; 1513} 1514 1515template<class Impl> 1516ThreadID 1517DefaultFetch<Impl>::iqCount() 1518{ 1519 //sorted from lowest->highest 1520 std::priority_queue<unsigned,vector<unsigned>, 1521 std::greater<unsigned> > PQ; 1522 std::map<unsigned, ThreadID> threadMap; 1523 1524 list<ThreadID>::iterator threads = activeThreads->begin(); 1525 list<ThreadID>::iterator end = activeThreads->end(); 1526 1527 while (threads != end) { 1528 ThreadID tid = *threads++; 1529 unsigned iqCount = fromIEW->iewInfo[tid].iqCount; 1530 1531 //we can potentially get tid collisions if two threads 1532 //have the same iqCount, but this should be rare. 1533 PQ.push(iqCount); 1534 threadMap[iqCount] = tid; 1535 } 1536 1537 while (!PQ.empty()) { 1538 ThreadID high_pri = threadMap[PQ.top()]; 1539 1540 if (fetchStatus[high_pri] == Running || 1541 fetchStatus[high_pri] == IcacheAccessComplete || 1542 fetchStatus[high_pri] == Idle) 1543 return high_pri; 1544 else 1545 PQ.pop(); 1546 1547 } 1548 1549 return InvalidThreadID; 1550} 1551 1552template<class Impl> 1553ThreadID 1554DefaultFetch<Impl>::lsqCount() 1555{ 1556 //sorted from lowest->highest 1557 std::priority_queue<unsigned,vector<unsigned>, 1558 std::greater<unsigned> > PQ; 1559 std::map<unsigned, ThreadID> threadMap; 1560 1561 list<ThreadID>::iterator threads = activeThreads->begin(); 1562 list<ThreadID>::iterator end = activeThreads->end(); 1563 1564 while (threads != end) { 1565 ThreadID tid = *threads++; 1566 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount; 1567 1568 //we can potentially get tid collisions if two threads 1569 //have the same iqCount, but this should be rare. 1570 PQ.push(ldstqCount); 1571 threadMap[ldstqCount] = tid; 1572 } 1573 1574 while (!PQ.empty()) { 1575 ThreadID high_pri = threadMap[PQ.top()]; 1576 1577 if (fetchStatus[high_pri] == Running || 1578 fetchStatus[high_pri] == IcacheAccessComplete || 1579 fetchStatus[high_pri] == Idle) 1580 return high_pri; 1581 else 1582 PQ.pop(); 1583 } 1584 1585 return InvalidThreadID; 1586} 1587 1588template<class Impl> 1589ThreadID 1590DefaultFetch<Impl>::branchCount() 1591{ 1592#if 0 1593 list<ThreadID>::iterator thread = activeThreads->begin(); 1594 assert(thread != activeThreads->end()); 1595 ThreadID tid = *thread; 1596#endif 1597 1598 panic("Branch Count Fetch policy unimplemented\n"); 1599 return InvalidThreadID; 1600} 1601 1602template<class Impl> 1603void 1604DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid) 1605{ 1606 if (!issuePipelinedIfetch[tid]) { 1607 return; 1608 } 1609 1610 // The next PC to access. 1611 TheISA::PCState thisPC = pc[tid]; 1612 1613 if (isRomMicroPC(thisPC.microPC())) { 1614 return; 1615 } 1616 1617 Addr pcOffset = fetchOffset[tid]; 1618 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1619 1620 // Align the fetch PC so its at the start of a fetch buffer segment. 1621 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1622 1623 // Unless buffer already got the block, fetch it from icache. 1624 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid])) { 1625 DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, " 1626 "starting at PC %s.\n", tid, thisPC); 1627 1628 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1629 } 1630} 1631 1632template<class Impl> 1633void 1634DefaultFetch<Impl>::profileStall(ThreadID tid) { 1635 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1636 1637 // @todo Per-thread stats 1638 1639 if (stalls[tid].drain) { 1640 ++fetchPendingDrainCycles; 1641 DPRINTF(Fetch, "Fetch is waiting for a drain!\n"); 1642 } else if (activeThreads->empty()) { 1643 ++fetchNoActiveThreadStallCycles; 1644 DPRINTF(Fetch, "Fetch has no active thread!\n"); 1645 } else if (fetchStatus[tid] == Blocked) { 1646 ++fetchBlockedCycles; 1647 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1648 } else if (fetchStatus[tid] == Squashing) { 1649 ++fetchSquashCycles; 1650 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1651 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1652 ++icacheStallCycles; 1653 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", 1654 tid); 1655 } else if (fetchStatus[tid] == ItlbWait) { 1656 ++fetchTlbCycles; 1657 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to " 1658 "finish!\n", tid); 1659 } else if (fetchStatus[tid] == TrapPending) { 1660 ++fetchPendingTrapStallCycles; 1661 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n", 1662 tid); 1663 } else if (fetchStatus[tid] == QuiescePending) { 1664 ++fetchPendingQuiesceStallCycles; 1665 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce " 1666 "instruction!\n", tid); 1667 } else if (fetchStatus[tid] == IcacheWaitRetry) { 1668 ++fetchIcacheWaitRetryStallCycles; 1669 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache retry!\n", 1670 tid); 1671 } else if (fetchStatus[tid] == NoGoodAddr) { 1672 DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n", 1673 tid); 1674 } else { 1675 DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason (Status: %i).\n", 1676 tid, fetchStatus[tid]); 1677 } 1678} 1679 1680#endif//__CPU_O3_FETCH_IMPL_HH__
| 156 // Create space to buffer the cache line data, 157 // which may not hold the entire cache line. 158 fetchBuffer[tid] = new uint8_t[fetchBufferSize]; 159 } 160} 161 162template <class Impl> 163std::string 164DefaultFetch<Impl>::name() const 165{ 166 return cpu->name() + ".fetch"; 167} 168 169template <class Impl> 170void 171DefaultFetch<Impl>::regProbePoints() 172{ 173 ppFetch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Fetch"); 174} 175 176template <class Impl> 177void 178DefaultFetch<Impl>::regStats() 179{ 180 icacheStallCycles 181 .name(name() + ".icacheStallCycles") 182 .desc("Number of cycles fetch is stalled on an Icache miss") 183 .prereq(icacheStallCycles); 184 185 fetchedInsts 186 .name(name() + ".Insts") 187 .desc("Number of instructions fetch has processed") 188 .prereq(fetchedInsts); 189 190 fetchedBranches 191 .name(name() + ".Branches") 192 .desc("Number of branches that fetch encountered") 193 .prereq(fetchedBranches); 194 195 predictedBranches 196 .name(name() + ".predictedBranches") 197 .desc("Number of branches that fetch has predicted taken") 198 .prereq(predictedBranches); 199 200 fetchCycles 201 .name(name() + ".Cycles") 202 .desc("Number of cycles fetch has run and was not squashing or" 203 " blocked") 204 .prereq(fetchCycles); 205 206 fetchSquashCycles 207 .name(name() + ".SquashCycles") 208 .desc("Number of cycles fetch has spent squashing") 209 .prereq(fetchSquashCycles); 210 211 fetchTlbCycles 212 .name(name() + ".TlbCycles") 213 .desc("Number of cycles fetch has spent waiting for tlb") 214 .prereq(fetchTlbCycles); 215 216 fetchIdleCycles 217 .name(name() + ".IdleCycles") 218 .desc("Number of cycles fetch was idle") 219 .prereq(fetchIdleCycles); 220 221 fetchBlockedCycles 222 .name(name() + ".BlockedCycles") 223 .desc("Number of cycles fetch has spent blocked") 224 .prereq(fetchBlockedCycles); 225 226 fetchedCacheLines 227 .name(name() + ".CacheLines") 228 .desc("Number of cache lines fetched") 229 .prereq(fetchedCacheLines); 230 231 fetchMiscStallCycles 232 .name(name() + ".MiscStallCycles") 233 .desc("Number of cycles fetch has spent waiting on interrupts, or " 234 "bad addresses, or out of MSHRs") 235 .prereq(fetchMiscStallCycles); 236 237 fetchPendingDrainCycles 238 .name(name() + ".PendingDrainCycles") 239 .desc("Number of cycles fetch has spent waiting on pipes to drain") 240 .prereq(fetchPendingDrainCycles); 241 242 fetchNoActiveThreadStallCycles 243 .name(name() + ".NoActiveThreadStallCycles") 244 .desc("Number of stall cycles due to no active thread to fetch from") 245 .prereq(fetchNoActiveThreadStallCycles); 246 247 fetchPendingTrapStallCycles 248 .name(name() + ".PendingTrapStallCycles") 249 .desc("Number of stall cycles due to pending traps") 250 .prereq(fetchPendingTrapStallCycles); 251 252 fetchPendingQuiesceStallCycles 253 .name(name() + ".PendingQuiesceStallCycles") 254 .desc("Number of stall cycles due to pending quiesce instructions") 255 .prereq(fetchPendingQuiesceStallCycles); 256 257 fetchIcacheWaitRetryStallCycles 258 .name(name() + ".IcacheWaitRetryStallCycles") 259 .desc("Number of stall cycles due to full MSHR") 260 .prereq(fetchIcacheWaitRetryStallCycles); 261 262 fetchIcacheSquashes 263 .name(name() + ".IcacheSquashes") 264 .desc("Number of outstanding Icache misses that were squashed") 265 .prereq(fetchIcacheSquashes); 266 267 fetchTlbSquashes 268 .name(name() + ".ItlbSquashes") 269 .desc("Number of outstanding ITLB misses that were squashed") 270 .prereq(fetchTlbSquashes); 271 272 fetchNisnDist 273 .init(/* base value */ 0, 274 /* last value */ fetchWidth, 275 /* bucket size */ 1) 276 .name(name() + ".rateDist") 277 .desc("Number of instructions fetched each cycle (Total)") 278 .flags(Stats::pdf); 279 280 idleRate 281 .name(name() + ".idleRate") 282 .desc("Percent of cycles fetch was idle") 283 .prereq(idleRate); 284 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 285 286 branchRate 287 .name(name() + ".branchRate") 288 .desc("Number of branch fetches per cycle") 289 .flags(Stats::total); 290 branchRate = fetchedBranches / cpu->numCycles; 291 292 fetchRate 293 .name(name() + ".rate") 294 .desc("Number of inst fetches per cycle") 295 .flags(Stats::total); 296 fetchRate = fetchedInsts / cpu->numCycles; 297} 298 299template<class Impl> 300void 301DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 302{ 303 timeBuffer = time_buffer; 304 305 // Create wires to get information from proper places in time buffer. 306 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 307 fromRename = timeBuffer->getWire(-renameToFetchDelay); 308 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 309 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 310} 311 312template<class Impl> 313void 314DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 315{ 316 activeThreads = at_ptr; 317} 318 319template<class Impl> 320void 321DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *ftb_ptr) 322{ 323 // Create wire to write information to proper place in fetch time buf. 324 toDecode = ftb_ptr->getWire(0); 325} 326 327template<class Impl> 328void 329DefaultFetch<Impl>::startupStage() 330{ 331 assert(priorityList.empty()); 332 resetStage(); 333 334 // Fetch needs to start fetching instructions at the very beginning, 335 // so it must start up in active state. 336 switchToActive(); 337} 338 339template<class Impl> 340void 341DefaultFetch<Impl>::resetStage() 342{ 343 numInst = 0; 344 interruptPending = false; 345 cacheBlocked = false; 346 347 priorityList.clear(); 348 349 // Setup PC and nextPC with initial state. 350 for (ThreadID tid = 0; tid < numThreads; ++tid) { 351 fetchStatus[tid] = Running; 352 pc[tid] = cpu->pcState(tid); 353 fetchOffset[tid] = 0; 354 macroop[tid] = NULL; 355 356 delayedCommit[tid] = false; 357 memReq[tid] = NULL; 358 359 stalls[tid].decode = false; 360 stalls[tid].drain = false; 361 362 fetchBufferPC[tid] = 0; 363 fetchBufferValid[tid] = false; 364 365 fetchQueue[tid].clear(); 366 367 priorityList.push_back(tid); 368 } 369 370 wroteToTimeBuffer = false; 371 _status = Inactive; 372} 373 374template<class Impl> 375void 376DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 377{ 378 ThreadID tid = pkt->req->threadId(); 379 380 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 381 assert(!cpu->switchedOut()); 382 383 // Only change the status if it's still waiting on the icache access 384 // to return. 385 if (fetchStatus[tid] != IcacheWaitResponse || 386 pkt->req != memReq[tid]) { 387 ++fetchIcacheSquashes; 388 delete pkt->req; 389 delete pkt; 390 return; 391 } 392 393 memcpy(fetchBuffer[tid], pkt->getConstPtr<uint8_t>(), fetchBufferSize); 394 fetchBufferValid[tid] = true; 395 396 // Wake up the CPU (if it went to sleep and was waiting on 397 // this completion event). 398 cpu->wakeCPU(); 399 400 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 401 tid); 402 403 switchToActive(); 404 405 // Only switch to IcacheAccessComplete if we're not stalled as well. 406 if (checkStall(tid)) { 407 fetchStatus[tid] = Blocked; 408 } else { 409 fetchStatus[tid] = IcacheAccessComplete; 410 } 411 412 pkt->req->setAccessLatency(); 413 cpu->ppInstAccessComplete->notify(pkt); 414 // Reset the mem req to NULL. 415 delete pkt->req; 416 delete pkt; 417 memReq[tid] = NULL; 418} 419 420template <class Impl> 421void 422DefaultFetch<Impl>::drainResume() 423{ 424 for (ThreadID i = 0; i < numThreads; ++i) 425 stalls[i].drain = false; 426} 427 428template <class Impl> 429void 430DefaultFetch<Impl>::drainSanityCheck() const 431{ 432 assert(isDrained()); 433 assert(retryPkt == NULL); 434 assert(retryTid == InvalidThreadID); 435 assert(!cacheBlocked); 436 assert(!interruptPending); 437 438 for (ThreadID i = 0; i < numThreads; ++i) { 439 assert(!memReq[i]); 440 assert(fetchStatus[i] == Idle || stalls[i].drain); 441 } 442 443 branchPred->drainSanityCheck(); 444} 445 446template <class Impl> 447bool 448DefaultFetch<Impl>::isDrained() const 449{ 450 /* Make sure that threads are either idle of that the commit stage 451 * has signaled that draining has completed by setting the drain 452 * stall flag. This effectively forces the pipeline to be disabled 453 * until the whole system is drained (simulation may continue to 454 * drain other components). 455 */ 456 for (ThreadID i = 0; i < numThreads; ++i) { 457 // Verify fetch queues are drained 458 if (!fetchQueue[i].empty()) 459 return false; 460 461 // Return false if not idle or drain stalled 462 if (fetchStatus[i] != Idle) { 463 if (fetchStatus[i] == Blocked && stalls[i].drain) 464 continue; 465 else 466 return false; 467 } 468 } 469 470 /* The pipeline might start up again in the middle of the drain 471 * cycle if the finish translation event is scheduled, so make 472 * sure that's not the case. 473 */ 474 return !finishTranslationEvent.scheduled(); 475} 476 477template <class Impl> 478void 479DefaultFetch<Impl>::takeOverFrom() 480{ 481 assert(cpu->getInstPort().isConnected()); 482 resetStage(); 483 484} 485 486template <class Impl> 487void 488DefaultFetch<Impl>::drainStall(ThreadID tid) 489{ 490 assert(cpu->isDraining()); 491 assert(!stalls[tid].drain); 492 DPRINTF(Drain, "%i: Thread drained.\n", tid); 493 stalls[tid].drain = true; 494} 495 496template <class Impl> 497void 498DefaultFetch<Impl>::wakeFromQuiesce() 499{ 500 DPRINTF(Fetch, "Waking up from quiesce\n"); 501 // Hopefully this is safe 502 // @todo: Allow other threads to wake from quiesce. 503 fetchStatus[0] = Running; 504} 505 506template <class Impl> 507inline void 508DefaultFetch<Impl>::switchToActive() 509{ 510 if (_status == Inactive) { 511 DPRINTF(Activity, "Activating stage.\n"); 512 513 cpu->activateStage(O3CPU::FetchIdx); 514 515 _status = Active; 516 } 517} 518 519template <class Impl> 520inline void 521DefaultFetch<Impl>::switchToInactive() 522{ 523 if (_status == Active) { 524 DPRINTF(Activity, "Deactivating stage.\n"); 525 526 cpu->deactivateStage(O3CPU::FetchIdx); 527 528 _status = Inactive; 529 } 530} 531 532template <class Impl> 533void 534DefaultFetch<Impl>::deactivateThread(ThreadID tid) 535{ 536 // Update priority list 537 auto thread_it = std::find(priorityList.begin(), priorityList.end(), tid); 538 if (thread_it != priorityList.end()) { 539 priorityList.erase(thread_it); 540 } 541} 542 543template <class Impl> 544bool 545DefaultFetch<Impl>::lookupAndUpdateNextPC( 546 DynInstPtr &inst, TheISA::PCState &nextPC) 547{ 548 // Do branch prediction check here. 549 // A bit of a misnomer...next_PC is actually the current PC until 550 // this function updates it. 551 bool predict_taken; 552 553 if (!inst->isControl()) { 554 TheISA::advancePC(nextPC, inst->staticInst); 555 inst->setPredTarg(nextPC); 556 inst->setPredTaken(false); 557 return false; 558 } 559 560 ThreadID tid = inst->threadNumber; 561 predict_taken = branchPred->predict(inst->staticInst, inst->seqNum, 562 nextPC, tid); 563 564 if (predict_taken) { 565 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 566 tid, inst->seqNum, nextPC); 567 } else { 568 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 569 tid, inst->seqNum); 570 } 571 572 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 573 tid, inst->seqNum, nextPC); 574 inst->setPredTarg(nextPC); 575 inst->setPredTaken(predict_taken); 576 577 ++fetchedBranches; 578 579 if (predict_taken) { 580 ++predictedBranches; 581 } 582 583 return predict_taken; 584} 585 586template <class Impl> 587bool 588DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) 589{ 590 Fault fault = NoFault; 591 592 assert(!cpu->switchedOut()); 593 594 // @todo: not sure if these should block translation. 595 //AlphaDep 596 if (cacheBlocked) { 597 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 598 tid); 599 return false; 600 } else if (checkInterrupt(pc) && !delayedCommit[tid]) { 601 // Hold off fetch from getting new instructions when: 602 // Cache is blocked, or 603 // while an interrupt is pending and we're not in PAL mode, or 604 // fetch is switched out. 605 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 606 tid); 607 return false; 608 } 609 610 // Align the fetch address to the start of a fetch buffer segment. 611 Addr fetchBufferBlockPC = fetchBufferAlignPC(vaddr); 612 613 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n", 614 tid, fetchBufferBlockPC, vaddr); 615 616 // Setup the memReq to do a read of the first instruction's address. 617 // Set the appropriate read size and flags as well. 618 // Build request here. 619 RequestPtr mem_req = 620 new Request(tid, fetchBufferBlockPC, fetchBufferSize, 621 Request::INST_FETCH, cpu->instMasterId(), pc, 622 cpu->thread[tid]->contextId(), tid); 623 624 mem_req->taskId(cpu->taskId()); 625 626 memReq[tid] = mem_req; 627 628 // Initiate translation of the icache block 629 fetchStatus[tid] = ItlbWait; 630 FetchTranslation *trans = new FetchTranslation(this); 631 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(), 632 trans, BaseTLB::Execute); 633 return true; 634} 635 636template <class Impl> 637void 638DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req) 639{ 640 ThreadID tid = mem_req->threadId(); 641 Addr fetchBufferBlockPC = mem_req->getVaddr(); 642 643 assert(!cpu->switchedOut()); 644 645 // Wake up CPU if it was idle 646 cpu->wakeCPU(); 647 648 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] || 649 mem_req->getVaddr() != memReq[tid]->getVaddr()) { 650 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n", 651 tid); 652 ++fetchTlbSquashes; 653 delete mem_req; 654 return; 655 } 656 657 658 // If translation was successful, attempt to read the icache block. 659 if (fault == NoFault) { 660 // Check that we're not going off into random memory 661 // If we have, just wait around for commit to squash something and put 662 // us on the right track 663 if (!cpu->system->isMemAddr(mem_req->getPaddr())) { 664 warn("Address %#x is outside of physical memory, stopping fetch\n", 665 mem_req->getPaddr()); 666 fetchStatus[tid] = NoGoodAddr; 667 delete mem_req; 668 memReq[tid] = NULL; 669 return; 670 } 671 672 // Build packet here. 673 PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq); 674 data_pkt->dataDynamic(new uint8_t[fetchBufferSize]); 675 676 fetchBufferPC[tid] = fetchBufferBlockPC; 677 fetchBufferValid[tid] = false; 678 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 679 680 fetchedCacheLines++; 681 682 // Access the cache. 683 if (!cpu->getInstPort().sendTimingReq(data_pkt)) { 684 assert(retryPkt == NULL); 685 assert(retryTid == InvalidThreadID); 686 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 687 688 fetchStatus[tid] = IcacheWaitRetry; 689 retryPkt = data_pkt; 690 retryTid = tid; 691 cacheBlocked = true; 692 } else { 693 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid); 694 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 695 "response.\n", tid); 696 lastIcacheStall[tid] = curTick(); 697 fetchStatus[tid] = IcacheWaitResponse; 698 } 699 } else { 700 // Don't send an instruction to decode if we can't handle it. 701 if (!(numInst < fetchWidth) || !(fetchQueue[tid].size() < fetchQueueSize)) { 702 assert(!finishTranslationEvent.scheduled()); 703 finishTranslationEvent.setFault(fault); 704 finishTranslationEvent.setReq(mem_req); 705 cpu->schedule(finishTranslationEvent, 706 cpu->clockEdge(Cycles(1))); 707 return; 708 } 709 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n", 710 tid, mem_req->getVaddr(), memReq[tid]->getVaddr()); 711 // Translation faulted, icache request won't be sent. 712 delete mem_req; 713 memReq[tid] = NULL; 714 715 // Send the fault to commit. This thread will not do anything 716 // until commit handles the fault. The only other way it can 717 // wake up is if a squash comes along and changes the PC. 718 TheISA::PCState fetchPC = pc[tid]; 719 720 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid); 721 // We will use a nop in ordier to carry the fault. 722 DynInstPtr instruction = buildInst(tid, 723 decoder[tid]->decode(TheISA::NoopMachInst, fetchPC.instAddr()), 724 NULL, fetchPC, fetchPC, false); 725 726 instruction->setPredTarg(fetchPC); 727 instruction->fault = fault; 728 wroteToTimeBuffer = true; 729 730 DPRINTF(Activity, "Activity this cycle.\n"); 731 cpu->activityThisCycle(); 732 733 fetchStatus[tid] = TrapPending; 734 735 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); 736 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n", 737 tid, fault->name(), pc[tid]); 738 } 739 _status = updateFetchStatus(); 740} 741 742template <class Impl> 743inline void 744DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, 745 const DynInstPtr squashInst, ThreadID tid) 746{ 747 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 748 tid, newPC); 749 750 pc[tid] = newPC; 751 fetchOffset[tid] = 0; 752 if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr()) 753 macroop[tid] = squashInst->macroop; 754 else 755 macroop[tid] = NULL; 756 decoder[tid]->reset(); 757 758 // Clear the icache miss if it's outstanding. 759 if (fetchStatus[tid] == IcacheWaitResponse) { 760 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 761 tid); 762 memReq[tid] = NULL; 763 } else if (fetchStatus[tid] == ItlbWait) { 764 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n", 765 tid); 766 memReq[tid] = NULL; 767 } 768 769 // Get rid of the retrying packet if it was from this thread. 770 if (retryTid == tid) { 771 assert(cacheBlocked); 772 if (retryPkt) { 773 delete retryPkt->req; 774 delete retryPkt; 775 } 776 retryPkt = NULL; 777 retryTid = InvalidThreadID; 778 } 779 780 fetchStatus[tid] = Squashing; 781 782 // Empty fetch queue 783 fetchQueue[tid].clear(); 784 785 // microops are being squashed, it is not known wheather the 786 // youngest non-squashed microop was marked delayed commit 787 // or not. Setting the flag to true ensures that the 788 // interrupts are not handled when they cannot be, though 789 // some opportunities to handle interrupts may be missed. 790 delayedCommit[tid] = true; 791 792 ++fetchSquashCycles; 793} 794 795template<class Impl> 796void 797DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 798 const DynInstPtr squashInst, 799 const InstSeqNum seq_num, ThreadID tid) 800{ 801 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); 802 803 doSquash(newPC, squashInst, tid); 804 805 // Tell the CPU to remove any instructions that are in flight between 806 // fetch and decode. 807 cpu->removeInstsUntil(seq_num, tid); 808} 809 810template<class Impl> 811bool 812DefaultFetch<Impl>::checkStall(ThreadID tid) const 813{ 814 bool ret_val = false; 815 816 if (stalls[tid].drain) { 817 assert(cpu->isDraining()); 818 DPRINTF(Fetch,"[tid:%i]: Drain stall detected.\n",tid); 819 ret_val = true; 820 } 821 822 return ret_val; 823} 824 825template<class Impl> 826typename DefaultFetch<Impl>::FetchStatus 827DefaultFetch<Impl>::updateFetchStatus() 828{ 829 //Check Running 830 list<ThreadID>::iterator threads = activeThreads->begin(); 831 list<ThreadID>::iterator end = activeThreads->end(); 832 833 while (threads != end) { 834 ThreadID tid = *threads++; 835 836 if (fetchStatus[tid] == Running || 837 fetchStatus[tid] == Squashing || 838 fetchStatus[tid] == IcacheAccessComplete) { 839 840 if (_status == Inactive) { 841 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 842 843 if (fetchStatus[tid] == IcacheAccessComplete) { 844 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 845 "completion\n",tid); 846 } 847 848 cpu->activateStage(O3CPU::FetchIdx); 849 } 850 851 return Active; 852 } 853 } 854 855 // Stage is switching from active to inactive, notify CPU of it. 856 if (_status == Active) { 857 DPRINTF(Activity, "Deactivating stage.\n"); 858 859 cpu->deactivateStage(O3CPU::FetchIdx); 860 } 861 862 return Inactive; 863} 864 865template <class Impl> 866void 867DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 868 const InstSeqNum seq_num, DynInstPtr squashInst, 869 ThreadID tid) 870{ 871 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); 872 873 doSquash(newPC, squashInst, tid); 874 875 // Tell the CPU to remove any instructions that are not in the ROB. 876 cpu->removeInstsNotInROB(tid); 877} 878 879template <class Impl> 880void 881DefaultFetch<Impl>::tick() 882{ 883 list<ThreadID>::iterator threads = activeThreads->begin(); 884 list<ThreadID>::iterator end = activeThreads->end(); 885 bool status_change = false; 886 887 wroteToTimeBuffer = false; 888 889 for (ThreadID i = 0; i < numThreads; ++i) { 890 issuePipelinedIfetch[i] = false; 891 } 892 893 while (threads != end) { 894 ThreadID tid = *threads++; 895 896 // Check the signals for each thread to determine the proper status 897 // for each thread. 898 bool updated_status = checkSignalsAndUpdate(tid); 899 status_change = status_change || updated_status; 900 } 901 902 DPRINTF(Fetch, "Running stage.\n"); 903 904 if (FullSystem) { 905 if (fromCommit->commitInfo[0].interruptPending) { 906 interruptPending = true; 907 } 908 909 if (fromCommit->commitInfo[0].clearInterrupt) { 910 interruptPending = false; 911 } 912 } 913 914 for (threadFetched = 0; threadFetched < numFetchingThreads; 915 threadFetched++) { 916 // Fetch each of the actively fetching threads. 917 fetch(status_change); 918 } 919 920 // Record number of instructions fetched this cycle for distribution. 921 fetchNisnDist.sample(numInst); 922 923 if (status_change) { 924 // Change the fetch stage status if there was a status change. 925 _status = updateFetchStatus(); 926 } 927 928 // Issue the next I-cache request if possible. 929 for (ThreadID i = 0; i < numThreads; ++i) { 930 if (issuePipelinedIfetch[i]) { 931 pipelineIcacheAccesses(i); 932 } 933 } 934 935 // Send instructions enqueued into the fetch queue to decode. 936 // Limit rate by fetchWidth. Stall if decode is stalled. 937 unsigned insts_to_decode = 0; 938 unsigned available_insts = 0; 939 940 for (auto tid : *activeThreads) { 941 if (!stalls[tid].decode) { 942 available_insts += fetchQueue[tid].size(); 943 } 944 } 945 946 // Pick a random thread to start trying to grab instructions from 947 auto tid_itr = activeThreads->begin(); 948 std::advance(tid_itr, random_mt.random<uint8_t>(0, activeThreads->size() - 1)); 949 950 while (available_insts != 0 && insts_to_decode < decodeWidth) { 951 ThreadID tid = *tid_itr; 952 if (!stalls[tid].decode && !fetchQueue[tid].empty()) { 953 auto inst = fetchQueue[tid].front(); 954 toDecode->insts[toDecode->size++] = inst; 955 DPRINTF(Fetch, "[tid:%i][sn:%i]: Sending instruction to decode from " 956 "fetch queue. Fetch queue size: %i.\n", 957 tid, inst->seqNum, fetchQueue[tid].size()); 958 959 wroteToTimeBuffer = true; 960 fetchQueue[tid].pop_front(); 961 insts_to_decode++; 962 available_insts--; 963 } 964 965 tid_itr++; 966 // Wrap around if at end of active threads list 967 if (tid_itr == activeThreads->end()) 968 tid_itr = activeThreads->begin(); 969 } 970 971 // If there was activity this cycle, inform the CPU of it. 972 if (wroteToTimeBuffer) { 973 DPRINTF(Activity, "Activity this cycle.\n"); 974 cpu->activityThisCycle(); 975 } 976 977 // Reset the number of the instruction we've fetched. 978 numInst = 0; 979} 980 981template <class Impl> 982bool 983DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 984{ 985 // Update the per thread stall statuses. 986 if (fromDecode->decodeBlock[tid]) { 987 stalls[tid].decode = true; 988 } 989 990 if (fromDecode->decodeUnblock[tid]) { 991 assert(stalls[tid].decode); 992 assert(!fromDecode->decodeBlock[tid]); 993 stalls[tid].decode = false; 994 } 995 996 // Check squash signals from commit. 997 if (fromCommit->commitInfo[tid].squash) { 998 999 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 1000 "from commit.\n",tid); 1001 // In any case, squash. 1002 squash(fromCommit->commitInfo[tid].pc, 1003 fromCommit->commitInfo[tid].doneSeqNum, 1004 fromCommit->commitInfo[tid].squashInst, tid); 1005 1006 // If it was a branch mispredict on a control instruction, update the 1007 // branch predictor with that instruction, otherwise just kill the 1008 // invalid state we generated in after sequence number 1009 if (fromCommit->commitInfo[tid].mispredictInst && 1010 fromCommit->commitInfo[tid].mispredictInst->isControl()) { 1011 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum, 1012 fromCommit->commitInfo[tid].pc, 1013 fromCommit->commitInfo[tid].branchTaken, 1014 tid); 1015 } else { 1016 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum, 1017 tid); 1018 } 1019 1020 return true; 1021 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 1022 // Update the branch predictor if it wasn't a squashed instruction 1023 // that was broadcasted. 1024 branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid); 1025 } 1026 1027 // Check squash signals from decode. 1028 if (fromDecode->decodeInfo[tid].squash) { 1029 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 1030 "from decode.\n",tid); 1031 1032 // Update the branch predictor. 1033 if (fromDecode->decodeInfo[tid].branchMispredict) { 1034 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum, 1035 fromDecode->decodeInfo[tid].nextPC, 1036 fromDecode->decodeInfo[tid].branchTaken, 1037 tid); 1038 } else { 1039 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum, 1040 tid); 1041 } 1042 1043 if (fetchStatus[tid] != Squashing) { 1044 1045 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", 1046 fromDecode->decodeInfo[tid].nextPC); 1047 // Squash unless we're already squashing 1048 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 1049 fromDecode->decodeInfo[tid].squashInst, 1050 fromDecode->decodeInfo[tid].doneSeqNum, 1051 tid); 1052 1053 return true; 1054 } 1055 } 1056 1057 if (checkStall(tid) && 1058 fetchStatus[tid] != IcacheWaitResponse && 1059 fetchStatus[tid] != IcacheWaitRetry && 1060 fetchStatus[tid] != ItlbWait && 1061 fetchStatus[tid] != QuiescePending) { 1062 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 1063 1064 fetchStatus[tid] = Blocked; 1065 1066 return true; 1067 } 1068 1069 if (fetchStatus[tid] == Blocked || 1070 fetchStatus[tid] == Squashing) { 1071 // Switch status to running if fetch isn't being told to block or 1072 // squash this cycle. 1073 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 1074 tid); 1075 1076 fetchStatus[tid] = Running; 1077 1078 return true; 1079 } 1080 1081 // If we've reached this point, we have not gotten any signals that 1082 // cause fetch to change its status. Fetch remains the same as before. 1083 return false; 1084} 1085 1086template<class Impl> 1087typename Impl::DynInstPtr 1088DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 1089 StaticInstPtr curMacroop, TheISA::PCState thisPC, 1090 TheISA::PCState nextPC, bool trace) 1091{ 1092 // Get a sequence number. 1093 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 1094 1095 // Create a new DynInst from the instruction fetched. 1096 DynInstPtr instruction = 1097 new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu); 1098 instruction->setTid(tid); 1099 1100 instruction->setASID(tid); 1101 1102 instruction->setThreadState(cpu->thread[tid]); 1103 1104 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " 1105 "[sn:%lli].\n", tid, thisPC.instAddr(), 1106 thisPC.microPC(), seq); 1107 1108 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 1109 instruction->staticInst-> 1110 disassemble(thisPC.instAddr())); 1111 1112#if TRACING_ON 1113 if (trace) { 1114 instruction->traceData = 1115 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1116 instruction->staticInst, thisPC, curMacroop); 1117 } 1118#else 1119 instruction->traceData = NULL; 1120#endif 1121 1122 // Add instruction to the CPU's list of instructions. 1123 instruction->setInstListIt(cpu->addInst(instruction)); 1124 1125 // Write the instruction to the first slot in the queue 1126 // that heads to decode. 1127 assert(numInst < fetchWidth); 1128 fetchQueue[tid].push_back(instruction); 1129 assert(fetchQueue[tid].size() <= fetchQueueSize); 1130 DPRINTF(Fetch, "[tid:%i]: Fetch queue entry created (%i/%i).\n", 1131 tid, fetchQueue[tid].size(), fetchQueueSize); 1132 //toDecode->insts[toDecode->size++] = instruction; 1133 1134 // Keep track of if we can take an interrupt at this boundary 1135 delayedCommit[tid] = instruction->isDelayedCommit(); 1136 1137 return instruction; 1138} 1139 1140template<class Impl> 1141void 1142DefaultFetch<Impl>::fetch(bool &status_change) 1143{ 1144 ////////////////////////////////////////// 1145 // Start actual fetch 1146 ////////////////////////////////////////// 1147 ThreadID tid = getFetchingThread(fetchPolicy); 1148 1149 assert(!cpu->switchedOut()); 1150 1151 if (tid == InvalidThreadID) { 1152 // Breaks looping condition in tick() 1153 threadFetched = numFetchingThreads; 1154 1155 if (numThreads == 1) { // @todo Per-thread stats 1156 profileStall(0); 1157 } 1158 1159 return; 1160 } 1161 1162 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1163 1164 // The current PC. 1165 TheISA::PCState thisPC = pc[tid]; 1166 1167 Addr pcOffset = fetchOffset[tid]; 1168 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1169 1170 bool inRom = isRomMicroPC(thisPC.microPC()); 1171 1172 // If returning from the delay of a cache miss, then update the status 1173 // to running, otherwise do the cache access. Possibly move this up 1174 // to tick() function. 1175 if (fetchStatus[tid] == IcacheAccessComplete) { 1176 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid); 1177 1178 fetchStatus[tid] = Running; 1179 status_change = true; 1180 } else if (fetchStatus[tid] == Running) { 1181 // Align the fetch PC so its at the start of a fetch buffer segment. 1182 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1183 1184 // If buffer is no longer valid or fetchAddr has moved to point 1185 // to the next cache block, AND we have no remaining ucode 1186 // from a macro-op, then start fetch from icache. 1187 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid]) 1188 && !inRom && !macroop[tid]) { 1189 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1190 "instruction, starting at PC %s.\n", tid, thisPC); 1191 1192 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1193 1194 if (fetchStatus[tid] == IcacheWaitResponse) 1195 ++icacheStallCycles; 1196 else if (fetchStatus[tid] == ItlbWait) 1197 ++fetchTlbCycles; 1198 else 1199 ++fetchMiscStallCycles; 1200 return; 1201 } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])) { 1202 // Stall CPU if an interrupt is posted and we're not issuing 1203 // an delayed commit micro-op currently (delayed commit instructions 1204 // are not interruptable by interrupts, only faults) 1205 ++fetchMiscStallCycles; 1206 DPRINTF(Fetch, "[tid:%i]: Fetch is stalled!\n", tid); 1207 return; 1208 } 1209 } else { 1210 if (fetchStatus[tid] == Idle) { 1211 ++fetchIdleCycles; 1212 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1213 } 1214 1215 // Status is Idle, so fetch should do nothing. 1216 return; 1217 } 1218 1219 ++fetchCycles; 1220 1221 TheISA::PCState nextPC = thisPC; 1222 1223 StaticInstPtr staticInst = NULL; 1224 StaticInstPtr curMacroop = macroop[tid]; 1225 1226 // If the read of the first instruction was successful, then grab the 1227 // instructions from the rest of the cache line and put them into the 1228 // queue heading to decode. 1229 1230 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1231 "decode.\n", tid); 1232 1233 // Need to keep track of whether or not a predicted branch 1234 // ended this fetch block. 1235 bool predictedBranch = false; 1236 1237 // Need to halt fetch if quiesce instruction detected 1238 bool quiesce = false; 1239 1240 TheISA::MachInst *cacheInsts = 1241 reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]); 1242 1243 const unsigned numInsts = fetchBufferSize / instSize; 1244 unsigned blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize; 1245 1246 // Loop through instruction memory from the cache. 1247 // Keep issuing while fetchWidth is available and branch is not 1248 // predicted taken 1249 while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize 1250 && !predictedBranch && !quiesce) { 1251 // We need to process more memory if we aren't going to get a 1252 // StaticInst from the rom, the current macroop, or what's already 1253 // in the decoder. 1254 bool needMem = !inRom && !curMacroop && 1255 !decoder[tid]->instReady(); 1256 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1257 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1258 1259 if (needMem) { 1260 // If buffer is no longer valid or fetchAddr has moved to point 1261 // to the next cache block then start fetch from icache. 1262 if (!fetchBufferValid[tid] || 1263 fetchBufferBlockPC != fetchBufferPC[tid]) 1264 break; 1265 1266 if (blkOffset >= numInsts) { 1267 // We need to process more memory, but we've run out of the 1268 // current block. 1269 break; 1270 } 1271 1272 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { 1273 // Walk past any annulled delay slot instructions. 1274 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; 1275 while (fetchAddr != pcAddr && blkOffset < numInsts) { 1276 blkOffset++; 1277 fetchAddr += instSize; 1278 } 1279 if (blkOffset >= numInsts) 1280 break; 1281 } 1282 1283 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1284 decoder[tid]->moreBytes(thisPC, fetchAddr, inst); 1285 1286 if (decoder[tid]->needMoreBytes()) { 1287 blkOffset++; 1288 fetchAddr += instSize; 1289 pcOffset += instSize; 1290 } 1291 } 1292 1293 // Extract as many instructions and/or microops as we can from 1294 // the memory we've processed so far. 1295 do { 1296 if (!(curMacroop || inRom)) { 1297 if (decoder[tid]->instReady()) { 1298 staticInst = decoder[tid]->decode(thisPC); 1299 1300 // Increment stat of fetched instructions. 1301 ++fetchedInsts; 1302 1303 if (staticInst->isMacroop()) { 1304 curMacroop = staticInst; 1305 } else { 1306 pcOffset = 0; 1307 } 1308 } else { 1309 // We need more bytes for this instruction so blkOffset and 1310 // pcOffset will be updated 1311 break; 1312 } 1313 } 1314 // Whether we're moving to a new macroop because we're at the 1315 // end of the current one, or the branch predictor incorrectly 1316 // thinks we are... 1317 bool newMacro = false; 1318 if (curMacroop || inRom) { 1319 if (inRom) { 1320 staticInst = cpu->microcodeRom.fetchMicroop( 1321 thisPC.microPC(), curMacroop); 1322 } else { 1323 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1324 } 1325 newMacro |= staticInst->isLastMicroop(); 1326 } 1327 1328 DynInstPtr instruction = 1329 buildInst(tid, staticInst, curMacroop, 1330 thisPC, nextPC, true); 1331 1332 ppFetch->notify(instruction); 1333 numInst++; 1334 1335#if TRACING_ON 1336 if (DTRACE(O3PipeView)) { 1337 instruction->fetchTick = curTick(); 1338 } 1339#endif 1340 1341 nextPC = thisPC; 1342 1343 // If we're branching after this instruction, quit fetching 1344 // from the same block. 1345 predictedBranch |= thisPC.branching(); 1346 predictedBranch |= 1347 lookupAndUpdateNextPC(instruction, nextPC); 1348 if (predictedBranch) { 1349 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1350 } 1351 1352 newMacro |= thisPC.instAddr() != nextPC.instAddr(); 1353 1354 // Move to the next instruction, unless we have a branch. 1355 thisPC = nextPC; 1356 inRom = isRomMicroPC(thisPC.microPC()); 1357 1358 if (newMacro) { 1359 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask; 1360 blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize; 1361 pcOffset = 0; 1362 curMacroop = NULL; 1363 } 1364 1365 if (instruction->isQuiesce()) { 1366 DPRINTF(Fetch, 1367 "Quiesce instruction encountered, halting fetch!\n"); 1368 fetchStatus[tid] = QuiescePending; 1369 status_change = true; 1370 quiesce = true; 1371 break; 1372 } 1373 } while ((curMacroop || decoder[tid]->instReady()) && 1374 numInst < fetchWidth && 1375 fetchQueue[tid].size() < fetchQueueSize); 1376 1377 // Re-evaluate whether the next instruction to fetch is in micro-op ROM 1378 // or not. 1379 inRom = isRomMicroPC(thisPC.microPC()); 1380 } 1381 1382 if (predictedBranch) { 1383 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1384 "instruction encountered.\n", tid); 1385 } else if (numInst >= fetchWidth) { 1386 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1387 "for this cycle.\n", tid); 1388 } else if (blkOffset >= fetchBufferSize) { 1389 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of the" 1390 "fetch buffer.\n", tid); 1391 } 1392 1393 macroop[tid] = curMacroop; 1394 fetchOffset[tid] = pcOffset; 1395 1396 if (numInst > 0) { 1397 wroteToTimeBuffer = true; 1398 } 1399 1400 pc[tid] = thisPC; 1401 1402 // pipeline a fetch if we're crossing a fetch buffer boundary and not in 1403 // a state that would preclude fetching 1404 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1405 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1406 issuePipelinedIfetch[tid] = fetchBufferBlockPC != fetchBufferPC[tid] && 1407 fetchStatus[tid] != IcacheWaitResponse && 1408 fetchStatus[tid] != ItlbWait && 1409 fetchStatus[tid] != IcacheWaitRetry && 1410 fetchStatus[tid] != QuiescePending && 1411 !curMacroop; 1412} 1413 1414template<class Impl> 1415void 1416DefaultFetch<Impl>::recvReqRetry() 1417{ 1418 if (retryPkt != NULL) { 1419 assert(cacheBlocked); 1420 assert(retryTid != InvalidThreadID); 1421 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1422 1423 if (cpu->getInstPort().sendTimingReq(retryPkt)) { 1424 fetchStatus[retryTid] = IcacheWaitResponse; 1425 retryPkt = NULL; 1426 retryTid = InvalidThreadID; 1427 cacheBlocked = false; 1428 } 1429 } else { 1430 assert(retryTid == InvalidThreadID); 1431 // Access has been squashed since it was sent out. Just clear 1432 // the cache being blocked. 1433 cacheBlocked = false; 1434 } 1435} 1436 1437/////////////////////////////////////// 1438// // 1439// SMT FETCH POLICY MAINTAINED HERE // 1440// // 1441/////////////////////////////////////// 1442template<class Impl> 1443ThreadID 1444DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1445{ 1446 if (numThreads > 1) { 1447 switch (fetch_priority) { 1448 1449 case SingleThread: 1450 return 0; 1451 1452 case RoundRobin: 1453 return roundRobin(); 1454 1455 case IQ: 1456 return iqCount(); 1457 1458 case LSQ: 1459 return lsqCount(); 1460 1461 case Branch: 1462 return branchCount(); 1463 1464 default: 1465 return InvalidThreadID; 1466 } 1467 } else { 1468 list<ThreadID>::iterator thread = activeThreads->begin(); 1469 if (thread == activeThreads->end()) { 1470 return InvalidThreadID; 1471 } 1472 1473 ThreadID tid = *thread; 1474 1475 if (fetchStatus[tid] == Running || 1476 fetchStatus[tid] == IcacheAccessComplete || 1477 fetchStatus[tid] == Idle) { 1478 return tid; 1479 } else { 1480 return InvalidThreadID; 1481 } 1482 } 1483} 1484 1485 1486template<class Impl> 1487ThreadID 1488DefaultFetch<Impl>::roundRobin() 1489{ 1490 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1491 list<ThreadID>::iterator end = priorityList.end(); 1492 1493 ThreadID high_pri; 1494 1495 while (pri_iter != end) { 1496 high_pri = *pri_iter; 1497 1498 assert(high_pri <= numThreads); 1499 1500 if (fetchStatus[high_pri] == Running || 1501 fetchStatus[high_pri] == IcacheAccessComplete || 1502 fetchStatus[high_pri] == Idle) { 1503 1504 priorityList.erase(pri_iter); 1505 priorityList.push_back(high_pri); 1506 1507 return high_pri; 1508 } 1509 1510 pri_iter++; 1511 } 1512 1513 return InvalidThreadID; 1514} 1515 1516template<class Impl> 1517ThreadID 1518DefaultFetch<Impl>::iqCount() 1519{ 1520 //sorted from lowest->highest 1521 std::priority_queue<unsigned,vector<unsigned>, 1522 std::greater<unsigned> > PQ; 1523 std::map<unsigned, ThreadID> threadMap; 1524 1525 list<ThreadID>::iterator threads = activeThreads->begin(); 1526 list<ThreadID>::iterator end = activeThreads->end(); 1527 1528 while (threads != end) { 1529 ThreadID tid = *threads++; 1530 unsigned iqCount = fromIEW->iewInfo[tid].iqCount; 1531 1532 //we can potentially get tid collisions if two threads 1533 //have the same iqCount, but this should be rare. 1534 PQ.push(iqCount); 1535 threadMap[iqCount] = tid; 1536 } 1537 1538 while (!PQ.empty()) { 1539 ThreadID high_pri = threadMap[PQ.top()]; 1540 1541 if (fetchStatus[high_pri] == Running || 1542 fetchStatus[high_pri] == IcacheAccessComplete || 1543 fetchStatus[high_pri] == Idle) 1544 return high_pri; 1545 else 1546 PQ.pop(); 1547 1548 } 1549 1550 return InvalidThreadID; 1551} 1552 1553template<class Impl> 1554ThreadID 1555DefaultFetch<Impl>::lsqCount() 1556{ 1557 //sorted from lowest->highest 1558 std::priority_queue<unsigned,vector<unsigned>, 1559 std::greater<unsigned> > PQ; 1560 std::map<unsigned, ThreadID> threadMap; 1561 1562 list<ThreadID>::iterator threads = activeThreads->begin(); 1563 list<ThreadID>::iterator end = activeThreads->end(); 1564 1565 while (threads != end) { 1566 ThreadID tid = *threads++; 1567 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount; 1568 1569 //we can potentially get tid collisions if two threads 1570 //have the same iqCount, but this should be rare. 1571 PQ.push(ldstqCount); 1572 threadMap[ldstqCount] = tid; 1573 } 1574 1575 while (!PQ.empty()) { 1576 ThreadID high_pri = threadMap[PQ.top()]; 1577 1578 if (fetchStatus[high_pri] == Running || 1579 fetchStatus[high_pri] == IcacheAccessComplete || 1580 fetchStatus[high_pri] == Idle) 1581 return high_pri; 1582 else 1583 PQ.pop(); 1584 } 1585 1586 return InvalidThreadID; 1587} 1588 1589template<class Impl> 1590ThreadID 1591DefaultFetch<Impl>::branchCount() 1592{ 1593#if 0 1594 list<ThreadID>::iterator thread = activeThreads->begin(); 1595 assert(thread != activeThreads->end()); 1596 ThreadID tid = *thread; 1597#endif 1598 1599 panic("Branch Count Fetch policy unimplemented\n"); 1600 return InvalidThreadID; 1601} 1602 1603template<class Impl> 1604void 1605DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid) 1606{ 1607 if (!issuePipelinedIfetch[tid]) { 1608 return; 1609 } 1610 1611 // The next PC to access. 1612 TheISA::PCState thisPC = pc[tid]; 1613 1614 if (isRomMicroPC(thisPC.microPC())) { 1615 return; 1616 } 1617 1618 Addr pcOffset = fetchOffset[tid]; 1619 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1620 1621 // Align the fetch PC so its at the start of a fetch buffer segment. 1622 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1623 1624 // Unless buffer already got the block, fetch it from icache. 1625 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid])) { 1626 DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, " 1627 "starting at PC %s.\n", tid, thisPC); 1628 1629 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1630 } 1631} 1632 1633template<class Impl> 1634void 1635DefaultFetch<Impl>::profileStall(ThreadID tid) { 1636 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1637 1638 // @todo Per-thread stats 1639 1640 if (stalls[tid].drain) { 1641 ++fetchPendingDrainCycles; 1642 DPRINTF(Fetch, "Fetch is waiting for a drain!\n"); 1643 } else if (activeThreads->empty()) { 1644 ++fetchNoActiveThreadStallCycles; 1645 DPRINTF(Fetch, "Fetch has no active thread!\n"); 1646 } else if (fetchStatus[tid] == Blocked) { 1647 ++fetchBlockedCycles; 1648 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1649 } else if (fetchStatus[tid] == Squashing) { 1650 ++fetchSquashCycles; 1651 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1652 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1653 ++icacheStallCycles; 1654 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", 1655 tid); 1656 } else if (fetchStatus[tid] == ItlbWait) { 1657 ++fetchTlbCycles; 1658 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to " 1659 "finish!\n", tid); 1660 } else if (fetchStatus[tid] == TrapPending) { 1661 ++fetchPendingTrapStallCycles; 1662 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n", 1663 tid); 1664 } else if (fetchStatus[tid] == QuiescePending) { 1665 ++fetchPendingQuiesceStallCycles; 1666 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce " 1667 "instruction!\n", tid); 1668 } else if (fetchStatus[tid] == IcacheWaitRetry) { 1669 ++fetchIcacheWaitRetryStallCycles; 1670 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache retry!\n", 1671 tid); 1672 } else if (fetchStatus[tid] == NoGoodAddr) { 1673 DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n", 1674 tid); 1675 } else { 1676 DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason (Status: %i).\n", 1677 tid, fetchStatus[tid]); 1678 } 1679} 1680 1681#endif//__CPU_O3_FETCH_IMPL_HH__
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