fetch_impl.hh (6033:f1a9f7f6e7c6) | fetch_impl.hh (6036:f0841ee466a5) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 510 unchanged lines hidden (view full) --- 519 //Assume for now that all control flow is to a different macroop which 520 //would reset the micro pc to 0. 521 next_MicroPC = 0; 522 523 int tid = inst->threadNumber; 524 Addr pred_PC = next_PC; 525 predict_taken = branchPred.predict(inst, pred_PC, tid); 526 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 510 unchanged lines hidden (view full) --- 519 //Assume for now that all control flow is to a different macroop which 520 //would reset the micro pc to 0. 521 next_MicroPC = 0; 522 523 int tid = inst->threadNumber; 524 Addr pred_PC = next_PC; 525 predict_taken = branchPred.predict(inst, pred_PC, tid); 526 |
527/* if (predict_taken) { 528 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n", 529 tid, pred_PC); | 527 if (predict_taken) { 528 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %#x.\n", 529 tid, inst->seqNum, pred_PC); |
530 } else { | 530 } else { |
531 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); 532 }*/ | 531 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 532 tid, inst->seqNum); 533 } |
533 534#if ISA_HAS_DELAY_SLOT 535 next_PC = next_NPC; 536 if (predict_taken) 537 next_NPC = pred_PC; 538 else 539 next_NPC += instSize; 540#else 541 if (predict_taken) 542 next_PC = pred_PC; 543 else 544 next_PC += instSize; 545 next_NPC = next_PC + instSize; 546#endif | 534 535#if ISA_HAS_DELAY_SLOT 536 next_PC = next_NPC; 537 if (predict_taken) 538 next_NPC = pred_PC; 539 else 540 next_NPC += instSize; 541#else 542 if (predict_taken) 543 next_PC = pred_PC; 544 else 545 next_PC += instSize; 546 next_NPC = next_PC + instSize; 547#endif |
547/* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", 548 tid, next_PC, next_NPC);*/ | 548 549 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %#x and then %#x.\n", 550 tid, inst->seqNum, next_PC, next_NPC); |
549 inst->setPredTarg(next_PC, next_NPC, next_MicroPC); 550 inst->setPredTaken(predict_taken); 551 552 ++fetchedBranches; 553 554 if (predict_taken) { 555 ++predictedBranches; 556 } --- 893 unchanged lines hidden --- | 551 inst->setPredTarg(next_PC, next_NPC, next_MicroPC); 552 inst->setPredTaken(predict_taken); 553 554 ++fetchedBranches; 555 556 if (predict_taken) { 557 ++predictedBranches; 558 } --- 893 unchanged lines hidden --- |