1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44#include <algorithm>
45#include <cstring>
46
47#include "arch/isa_traits.hh"
48#include "arch/utility.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "config/use_checker.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/o3/fetch.hh"
54#include "cpu/exetrace.hh"
55#include "debug/Activity.hh"
56#include "debug/Fetch.hh"
57#include "mem/packet.hh"
58#include "mem/request.hh"
59#include "params/DerivO3CPU.hh"
60#include "sim/byteswap.hh"
61#include "sim/core.hh"
62
63#if FULL_SYSTEM
64#include "arch/tlb.hh"
65#include "arch/vtophys.hh"
66#include "sim/system.hh"
67#endif // FULL_SYSTEM
68
69using namespace std;

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130 fetch->recvRetry();
131}
132
133template<class Impl>
134DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
135 : cpu(_cpu),
136 branchPred(params),
137 predecoder(NULL),
138 decodeToFetchDelay(params->decodeToFetchDelay),
139 renameToFetchDelay(params->renameToFetchDelay),
140 iewToFetchDelay(params->iewToFetchDelay),
141 commitToFetchDelay(params->commitToFetchDelay),
142 fetchWidth(params->fetchWidth),
143 cacheBlocked(false),
144 retryPkt(NULL),
145 retryTid(InvalidThreadID),
146 numThreads(params->numThreads),
147 numFetchingThreads(params->smtNumFetchingThreads),
148 interruptPending(false),
149 drainPending(false),
150 switchedOut(false)
151{
152 if (numThreads > Impl::MaxThreads)
153 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
154 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
155 numThreads, static_cast<int>(Impl::MaxThreads));
156
157 // Set fetch stage's status to inactive.
158 _status = Inactive;

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263 .prereq(fetchedCacheLines);
264
265 fetchMiscStallCycles
266 .name(name() + ".MiscStallCycles")
267 .desc("Number of cycles fetch has spent waiting on interrupts, or "
268 "bad addresses, or out of MSHRs")
269 .prereq(fetchMiscStallCycles);
270
271 fetchIcacheSquashes
272 .name(name() + ".IcacheSquashes")
273 .desc("Number of outstanding Icache misses that were squashed")
274 .prereq(fetchIcacheSquashes);
275
276 fetchTlbSquashes
277 .name(name() + ".ItlbSquashes")
278 .desc("Number of outstanding ITLB misses that were squashed")

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670 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
671 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
672 "response.\n", tid);
673
674 lastIcacheStall[tid] = curTick();
675 fetchStatus[tid] = IcacheWaitResponse;
676 }
677 } else {
678 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
679 mem_req->getVaddr(), memReq[tid]->getVaddr());
680 // Translation faulted, icache request won't be sent.
681 delete mem_req;
682 memReq[tid] = NULL;
683
684 // Send the fault to commit. This thread will not do anything
685 // until commit handles the fault. The only other way it can
686 // wake up is if a squash comes along and changes the PC.
687 TheISA::PCState fetchPC = pc[tid];

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846DefaultFetch<Impl>::tick()
847{
848 list<ThreadID>::iterator threads = activeThreads->begin();
849 list<ThreadID>::iterator end = activeThreads->end();
850 bool status_change = false;
851
852 wroteToTimeBuffer = false;
853
854 while (threads != end) {
855 ThreadID tid = *threads++;
856
857 // Check the signals for each thread to determine the proper status
858 // for each thread.
859 bool updated_status = checkSignalsAndUpdate(tid);
860 status_change = status_change || updated_status;
861 }
862
863 DPRINTF(Fetch, "Running stage.\n");
864
865 // Reset the number of the instruction we're fetching.
866 numInst = 0;
867
868#if FULL_SYSTEM
869 if (fromCommit->commitInfo[0].interruptPending) {
870 interruptPending = true;
871 }
872
873 if (fromCommit->commitInfo[0].clearInterrupt) {
874 interruptPending = false;
875 }
876#endif

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890 }
891
892 // If there was activity this cycle, inform the CPU of it.
893 if (wroteToTimeBuffer || cpu->contextSwitch) {
894 DPRINTF(Activity, "Activity this cycle.\n");
895
896 cpu->activityThisCycle();
897 }
898}
899
900template <class Impl>
901bool
902DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
903{
904 // Update the per thread stall statuses.
905 if (fromDecode->decodeBlock[tid]) {

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1094DefaultFetch<Impl>::fetch(bool &status_change)
1095{
1096 //////////////////////////////////////////
1097 // Start actual fetch
1098 //////////////////////////////////////////
1099 ThreadID tid = getFetchingThread(fetchPolicy);
1100
1101 if (tid == InvalidThreadID || drainPending) {
1102 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1103
1104 // Breaks looping condition in tick()
1105 threadFetched = numFetchingThreads;
1106 return;
1107 }
1108
1109 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1110
1111 // The current PC.
1112 TheISA::PCState thisPC = pc[tid];
1113

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1152 // are not interruptable by interrupts, only faults)
1153 ++fetchMiscStallCycles;
1154 return;
1155 }
1156 } else {
1157 if (fetchStatus[tid] == Idle) {
1158 ++fetchIdleCycles;
1159 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1160 } else if (fetchStatus[tid] == Blocked) {
1161 ++fetchBlockedCycles;
1162 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1163 } else if (fetchStatus[tid] == Squashing) {
1164 ++fetchSquashCycles;
1165 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1166 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1167 ++icacheStallCycles;
1168 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1169 tid);
1170 } else if (fetchStatus[tid] == ItlbWait) {
1171 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1172 "finish! \n", tid);
1173 ++fetchTlbCycles;
1174 } else if (fetchStatus[tid] == TrapPending) {
1175 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n",
1176 tid);
1177 } else if (fetchStatus[tid] == NoGoodAddr) {
1178 DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n",
1179 tid);
1180 }
1181
1182
1183
1184 // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse
1185 // so fetch should do nothing.
1186 return;
1187 }
1188
1189 ++fetchCycles;
1190
1191 TheISA::PCState nextPC = thisPC;
1192
1193 StaticInstPtr staticInst = NULL;

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1324 macroop[tid] = curMacroop;
1325 fetchOffset[tid] = pcOffset;
1326
1327 if (numInst > 0) {
1328 wroteToTimeBuffer = true;
1329 }
1330
1331 pc[tid] = thisPC;
1332}
1333
1334template<class Impl>
1335void
1336DefaultFetch<Impl>::recvRetry()
1337{
1338 if (retryPkt != NULL) {
1339 assert(cacheBlocked);

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1506 list<ThreadID>::iterator thread = activeThreads->begin();
1507 assert(thread != activeThreads->end());
1508 ThreadID tid = *thread;
1509#endif
1510
1511 panic("Branch Count Fetch policy unimplemented\n");
1512 return InvalidThreadID;
1513}