1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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311}
312
313template<class Impl>
314void
315DefaultFetch<Impl>::initStage()
316{
317 // Setup PC and nextPC with initial state.
318 for (ThreadID tid = 0; tid < numThreads; tid++) {
319 PC[tid] = cpu->readPC(tid);
320 nextPC[tid] = cpu->readNextPC(tid);
321 microPC[tid] = cpu->readMicroPC(tid);
322 }
323
324 for (ThreadID tid = 0; tid < numThreads; tid++) {
325
326 fetchStatus[tid] = Running;
327
328 priorityList.push_back(tid);
329

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440DefaultFetch<Impl>::takeOverFrom()
441{
442 // Reset all state
443 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
444 stalls[i].decode = 0;
445 stalls[i].rename = 0;
446 stalls[i].iew = 0;
447 stalls[i].commit = 0;
448 PC[i] = cpu->readPC(i);
449 nextPC[i] = cpu->readNextPC(i);
450 microPC[i] = cpu->readMicroPC(i);
451 fetchStatus[i] = Running;
452 }
453 numInst = 0;
454 wroteToTimeBuffer = false;
455 _status = Inactive;
456 switchedOut = false;
457 interruptPending = false;
458 branchPred.takeOverFrom();

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491 cpu->deactivateStage(O3CPU::FetchIdx);
492
493 _status = Inactive;
494 }
495}
496
497template <class Impl>
498bool
499DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
500 Addr &next_NPC, Addr &next_MicroPC)
501{
502 // Do branch prediction check here.
503 // A bit of a misnomer...next_PC is actually the current PC until
504 // this function updates it.
505 bool predict_taken;
506
507 if (!inst->isControl()) {
508 if (inst->isMicroop() && !inst->isLastMicroop()) {
509 next_MicroPC++;
510 } else {
511 next_PC = next_NPC;
512 next_NPC = next_NPC + instSize;
513 next_MicroPC = 0;
514 }
515 inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
516 inst->setPredTaken(false);
517 return false;
518 }
519
520 //Assume for now that all control flow is to a different macroop which
521 //would reset the micro pc to 0.
522 next_MicroPC = 0;
523
524 ThreadID tid = inst->threadNumber;
525 Addr pred_PC = next_PC;
526 predict_taken = branchPred.predict(inst, pred_PC, tid);
527
528 if (predict_taken) {
529 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %#x.\n",
530 tid, inst->seqNum, pred_PC);
531 } else {
532 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
533 tid, inst->seqNum);
534 }
535
536#if ISA_HAS_DELAY_SLOT
537 next_PC = next_NPC;
538 if (predict_taken)
539 next_NPC = pred_PC;
540 else
541 next_NPC += instSize;
542#else
543 if (predict_taken)
544 next_PC = pred_PC;
545 else
546 next_PC += instSize;
547 next_NPC = next_PC + instSize;
548#endif
549
550 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %#x and then %#x.\n",
551 tid, inst->seqNum, next_PC, next_NPC);
552 inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
553 inst->setPredTaken(predict_taken);
554
555 ++fetchedBranches;
556
557 if (predict_taken) {
558 ++predictedBranches;
559 }
560

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663 }
664
665 ret_fault = fault;
666 return true;
667}
668
669template <class Impl>
670inline void
671DefaultFetch<Impl>::doSquash(const Addr &new_PC,
672 const Addr &new_NPC, const Addr &new_microPC, ThreadID tid)
673{
674 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
675 tid, new_PC, new_NPC);
676
677 PC[tid] = new_PC;
678 nextPC[tid] = new_NPC;
679 microPC[tid] = new_microPC;
680
681 // Clear the icache miss if it's outstanding.
682 if (fetchStatus[tid] == IcacheWaitResponse) {
683 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
684 tid);
685 memReq[tid] = NULL;
686 }
687

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698
699 fetchStatus[tid] = Squashing;
700
701 ++fetchSquashCycles;
702}
703
704template<class Impl>
705void
706DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
707 const Addr &new_MicroPC,
708 const InstSeqNum &seq_num, ThreadID tid)
709{
710 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
711
712 doSquash(new_PC, new_NPC, new_MicroPC, tid);
713
714 // Tell the CPU to remove any instructions that are in flight between
715 // fetch and decode.
716 cpu->removeInstsUntil(seq_num, tid);
717}
718
719template<class Impl>
720bool

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779 cpu->deactivateStage(O3CPU::FetchIdx);
780 }
781
782 return Inactive;
783}
784
785template <class Impl>
786void
787DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
788 const Addr &new_MicroPC,
789 const InstSeqNum &seq_num, ThreadID tid)
790{
791 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
792
793 doSquash(new_PC, new_NPC, new_MicroPC, tid);
794
795 // Tell the CPU to remove any instructions that are not in the ROB.
796 cpu->removeInstsNotInROB(tid);
797}
798
799template <class Impl>
800void
801DefaultFetch<Impl>::tick()

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898 }
899
900 // Check squash signals from commit.
901 if (fromCommit->commitInfo[tid].squash) {
902
903 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
904 "from commit.\n",tid);
905 // In any case, squash.
906 squash(fromCommit->commitInfo[tid].nextPC,
907 fromCommit->commitInfo[tid].nextNPC,
908 fromCommit->commitInfo[tid].nextMicroPC,
909 fromCommit->commitInfo[tid].doneSeqNum,
910 tid);
911
912 // Also check if there's a mispredict that happened.
913 if (fromCommit->commitInfo[tid].branchMispredict) {
914 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
915 fromCommit->commitInfo[tid].nextPC,
916 fromCommit->commitInfo[tid].branchTaken,
917 tid);
918 } else {
919 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
920 tid);
921 }
922
923 return true;

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950 tid);
951 } else {
952 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
953 tid);
954 }
955
956 if (fetchStatus[tid] != Squashing) {
957
958 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
959 fromDecode->decodeInfo[tid].nextPC,
960 fromDecode->decodeInfo[tid].nextNPC);
961 // Squash unless we're already squashing
962 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
963 fromDecode->decodeInfo[tid].nextNPC,
964 fromDecode->decodeInfo[tid].nextMicroPC,
965 fromDecode->decodeInfo[tid].doneSeqNum,
966 tid);
967
968 return true;
969 }
970 }
971
972 if (checkStall(tid) &&

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1011 // Breaks looping condition in tick()
1012 threadFetched = numFetchingThreads;
1013 return;
1014 }
1015
1016 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1017
1018 // The current PC.
1019 Addr fetch_PC = PC[tid];
1020 Addr fetch_NPC = nextPC[tid];
1021 Addr fetch_MicroPC = microPC[tid];
1022
1023 // Fault code for memory access.
1024 Fault fault = NoFault;
1025
1026 // If returning from the delay of a cache miss, then update the status
1027 // to running, otherwise do the cache access. Possibly move this up
1028 // to tick() function.
1029 if (fetchStatus[tid] == IcacheAccessComplete) {
1030 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1031 tid);
1032
1033 fetchStatus[tid] = Running;
1034 status_change = true;
1035 } else if (fetchStatus[tid] == Running) {
1036 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1037 "instruction, starting at PC %08p.\n",
1038 tid, fetch_PC);
1039
1040 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1041 if (!fetch_success) {
1042 if (cacheBlocked) {
1043 ++icacheStallCycles;
1044 } else {
1045 ++fetchMiscStallCycles;
1046 }
1047 return;
1048 }

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1070
1071 // If we had a stall due to an icache miss, then return.
1072 if (fetchStatus[tid] == IcacheWaitResponse) {
1073 ++icacheStallCycles;
1074 status_change = true;
1075 return;
1076 }
1077
1078 Addr next_PC = fetch_PC;
1079 Addr next_NPC = fetch_NPC;
1080 Addr next_MicroPC = fetch_MicroPC;
1081
1082 InstSeqNum inst_seq;
1083 MachInst inst;
1084 ExtMachInst ext_inst;
1085 // @todo: Fix this hack.
1086 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1087
1088 StaticInstPtr staticInst = NULL;
1089 StaticInstPtr macroop = NULL;
1090
1091 if (fault == NoFault) {
1092 // If the read of the first instruction was successful, then grab the
1093 // instructions from the rest of the cache line and put them into the
1094 // queue heading to decode.
1095
1096 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1097 "decode.\n",tid);
1098
1099 // Need to keep track of whether or not a predicted branch
1100 // ended this fetch block.
1101 bool predicted_branch = false;
1102
1103 while (offset < cacheBlkSize &&
1104 numInst < fetchWidth &&
1105 !predicted_branch) {
1106
1107 // If we're branching after this instruction, quite fetching
1108 // from the same block then.
1109 predicted_branch =
1110 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
1111 if (predicted_branch) {
1112 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
1113 fetch_PC, fetch_NPC);
1114 }
1115
1116 // Make sure this is a valid index.
1117 assert(offset <= cacheBlkSize - instSize);
1118
1119 if (!macroop) {
1120 // Get the instruction from the array of the cache line.
1121 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1122 (&cacheData[tid][offset]));
1123
1124 predecoder.setTC(cpu->thread[tid]->getTC());
1125 predecoder.moreBytes(fetch_PC, fetch_PC, inst);
1126
1127 ext_inst = predecoder.getExtMachInst();
1128 staticInst = StaticInstPtr(ext_inst, fetch_PC);
1129 if (staticInst->isMacroop())
1130 macroop = staticInst;
1131 }
1132 do {
1133 if (macroop) {
1134 staticInst = macroop->fetchMicroop(fetch_MicroPC);
1135 if (staticInst->isLastMicroop())
1136 macroop = NULL;
1137 }
1138
1139 // Get a sequence number.
1140 inst_seq = cpu->getAndIncrementInstSeq();
1141
1142 // Create a new DynInst from the instruction fetched.
1143 DynInstPtr instruction = new DynInst(staticInst,
1144 fetch_PC, fetch_NPC, fetch_MicroPC,
1145 next_PC, next_NPC, next_MicroPC,
1146 inst_seq, cpu);
1147 instruction->setTid(tid);
1148
1149 instruction->setASID(tid);
1150
1151 instruction->setThreadState(cpu->thread[tid]);
1152
1153 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1154 "[sn:%lli]\n", tid, instruction->readPC(),
1155 instruction->readMicroPC(), inst_seq);
1156
1157 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1158
1159 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1160 tid, instruction->staticInst->disassemble(fetch_PC));
1161
1162#if TRACING_ON
1163 instruction->traceData =
1164 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
1165 instruction->staticInst, instruction->readPC(),
1166 macroop, instruction->readMicroPC());
1167#else
1168 instruction->traceData = NULL;
1169#endif
1170
1171 ///FIXME This needs to be more robust in dealing with delay slots
1172 predicted_branch |=
1173 lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
1174
1175 // Add instruction to the CPU's list of instructions.
1176 instruction->setInstListIt(cpu->addInst(instruction));
1177
1178 // Write the instruction to the first slot in the queue
1179 // that heads to decode.
1180 toDecode->insts[numInst] = instruction;
1181
1182 toDecode->size++;
1183
1184 // Increment stat of fetched instructions.
1185 ++fetchedInsts;
1186
1187 // Move to the next instruction, unless we have a branch.
1188 fetch_PC = next_PC;
1189 fetch_NPC = next_NPC;
1190 fetch_MicroPC = next_MicroPC;
1191
1192 if (instruction->isQuiesce()) {
1193 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1194 curTick);
1195 fetchStatus[tid] = QuiescePending;
1196 ++numInst;
1197 status_change = true;
1198 break;
1199 }
1200
1201 ++numInst;
1202 } while (staticInst->isMicroop() &&
1203 !staticInst->isLastMicroop() &&
1204 numInst < fetchWidth);
1205 offset += instSize;
1206 }
1207
1208 if (predicted_branch) {
1209 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1210 "instruction encountered.\n", tid);
1211 } else if (numInst >= fetchWidth) {
1212 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1213 "for this cycle.\n", tid);

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1219
1220 if (numInst > 0) {
1221 wroteToTimeBuffer = true;
1222 }
1223
1224 // Now that fetching is completed, update the PC to signify what the next
1225 // cycle will be.
1226 if (fault == NoFault) {
1227 PC[tid] = next_PC;
1228 nextPC[tid] = next_NPC;
1229 microPC[tid] = next_MicroPC;
1230 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1231 } else {
1232 // We shouldn't be in an icache miss and also have a fault (an ITB
1233 // miss)
1234 if (fetchStatus[tid] == IcacheWaitResponse) {
1235 panic("Fetch should have exited prior to this!");
1236 }
1237
1238 // Send the fault to commit. This thread will not do anything
1239 // until commit handles the fault. The only other way it can
1240 // wake up is if a squash comes along and changes the PC.
1241 assert(numInst < fetchWidth);
1242 // Get a sequence number.
1243 inst_seq = cpu->getAndIncrementInstSeq();
1244 // We will use a nop in order to carry the fault.
1245 ext_inst = TheISA::NoopMachInst;
1246
1247 // Create a new DynInst from the dummy nop.
1248 DynInstPtr instruction = new DynInst(ext_inst,
1249 fetch_PC, fetch_NPC, fetch_MicroPC,
1250 next_PC, next_NPC, next_MicroPC,
1251 inst_seq, cpu);
1252 instruction->setPredTarg(next_NPC, next_NPC + instSize, 0);
1253 instruction->setTid(tid);
1254
1255 instruction->setASID(tid);
1256
1257 instruction->setThreadState(cpu->thread[tid]);
1258
1259 instruction->traceData = NULL;
1260

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1267
1268 wroteToTimeBuffer = true;
1269
1270 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1271
1272 fetchStatus[tid] = TrapPending;
1273 status_change = true;
1274
1275 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1276 tid, fault->name(), PC[tid]);
1277 }
1278}
1279
1280template<class Impl>
1281void
1282DefaultFetch<Impl>::recvRetry()
1283{
1284 if (retryPkt != NULL) {

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