1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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519 //Assume for now that all control flow is to a different macroop which
520 //would reset the micro pc to 0.
521 next_MicroPC = 0;
522
523 int tid = inst->threadNumber;
524 Addr pred_PC = next_PC;
525 predict_taken = branchPred.predict(inst, pred_PC, tid);
526
527/* if (predict_taken) {
528 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n",
529 tid, pred_PC);
530 } else {
531 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid);
532 }*/
533
534#if ISA_HAS_DELAY_SLOT
535 next_PC = next_NPC;
536 if (predict_taken)
537 next_NPC = pred_PC;
538 else
539 next_NPC += instSize;
540#else
541 if (predict_taken)
542 next_PC = pred_PC;
543 else
544 next_PC += instSize;
545 next_NPC = next_PC + instSize;
546#endif
547/* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n",
548 tid, next_PC, next_NPC);*/
549 inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
550 inst->setPredTaken(predict_taken);
551
552 ++fetchedBranches;
553
554 if (predict_taken) {
555 ++predictedBranches;
556 }

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