1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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98DefaultFetch<Impl>::IcachePort::recvRetry()
99{
100 fetch->recvRetry();
101}
102
103template<class Impl>
104DefaultFetch<Impl>::DefaultFetch(Params *params)
105 : branchPred(params),
106 decodeToFetchDelay(params->decodeToFetchDelay),
107 renameToFetchDelay(params->renameToFetchDelay),
108 iewToFetchDelay(params->iewToFetchDelay),
109 commitToFetchDelay(params->commitToFetchDelay),
110 fetchWidth(params->fetchWidth),
111 cacheBlocked(false),
112 retryPkt(NULL),
113 retryTid(-1),

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1112
1113 // Make sure this is a valid index.
1114 assert(offset <= cacheBlkSize - instSize);
1115
1116 // Get the instruction from the array of the cache line.
1117 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1118 (&cacheData[tid][offset]));
1119
1120 //unsigned int result =
1121 TheISA::predecode(ext_inst, fetch_PC, inst,
1122 cpu->thread[tid]->getTC());
1123
1124 // Create a new DynInst from the instruction fetched.
1125 DynInstPtr instruction = new DynInst(ext_inst,
1126 fetch_PC, fetch_NPC,
1127 next_PC, next_NPC,
1128 inst_seq, cpu);
1129 instruction->setTid(tid);
1130
1131 instruction->setASID(tid);

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