1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1109
1110 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1111 "decode.\n",tid);
1112
1113 // Need to keep track of whether or not a predicted branch
1114 // ended this fetch block.
1115 bool predicted_branch = false;
1116
1117 // Need to keep track of whether or not a delay slot
1118 // instruction has been fetched
1119
1120 for (;
1121 offset < cacheBlkSize &&
1122 numInst < fetchWidth &&
1123 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1124 ++numInst) {
1125
1126 // Get a sequence number.
1127 inst_seq = cpu->getAndIncrementInstSeq();
1128
1129 // Make sure this is a valid index.
1130 assert(offset <= cacheBlkSize - instSize);
1131
1132 // Get the instruction from the array of the cache line.
1133 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>

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1161 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1162 tid, instruction->staticInst->disassemble(fetch_PC));
1163
1164 instruction->traceData =
1165 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1166 instruction->staticInst,
1167 instruction->readPC());
1168
1169 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1170 next_NPC);
1171
1172 // Add instruction to the CPU's list of instructions.
1173 instruction->setInstListIt(cpu->addInst(instruction));
1174
1175 // Write the instruction to the first slot in the queue
1176 // that heads to decode.
1177 toDecode->insts[numInst] = instruction;
1178
1179 toDecode->size++;
1180
1181 // Increment stat of fetched instructions.
1182 ++fetchedInsts;
1183
1184 // Move to the next instruction, unless we have a branch.
1185 fetch_PC = next_PC;
1186
1187 if (instruction->isQuiesce()) {
1188 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1189 curTick);
1190 fetchStatus[tid] = QuiescePending;
1191 ++numInst;
1192 status_change = true;
1193 break;
1194 }
1195
1196 offset += instSize;
1197
1198#if ISA_HAS_DELAY_SLOT
1199 if (predicted_branch) {
1200 delaySlotInfo[tid].branchSeqNum = inst_seq;
1201
1202 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1203 tid, inst_seq);
1204 continue;
1205 } else if (delaySlotInfo[tid].numInsts > 0) {
1206 --delaySlotInfo[tid].numInsts;
1207
1208 // It's OK to set PC to target of branch
1209 if (delaySlotInfo[tid].numInsts == 0) {
1210 delaySlotInfo[tid].targetReady = true;
1211
1212 // Break the looping condition
1213 predicted_branch = true;
1214 }
1215
1216 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1217 " process.\n", tid, delaySlotInfo[tid].numInsts);
1218 }
1219#endif
1220 }
1221
1222 if (offset >= cacheBlkSize) {
1223 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1224 "block.\n", tid);
1225 } else if (numInst >= fetchWidth) {
1226 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1227 "for this cycle.\n", tid);
1228 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1229 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1230 "instruction encountered.\n", tid);
1231 }
1232 }
1233
1234 if (numInst > 0) {
1235 wroteToTimeBuffer = true;
1236 }

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