1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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58 panic("DefaultFetch doesn't expect recvAtomic callback!");
59 return curTick;
60}
61
62template<class Impl>
63void
64DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
65{
66 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
67 "functional call.");
68}
69
70template<class Impl>
71void
72DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
73{
74 if (status == RangeChange)
75 return;
76
77 panic("DefaultFetch doesn't expect recvStatusChange callback!");
78}
79
80template<class Impl>
81bool
82DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
83{
84 DPRINTF(Fetch, "Received timing\n");
85 if (pkt->isResponse()) {
86 fetch->processCacheCompletion(pkt);
87 }
88 //else Snooped a coherence request, just return
89 return true;
90}
91
92template<class Impl>
93void
94DefaultFetch<Impl>::IcachePort::recvRetry()
95{
96 fetch->recvRetry();
97}
98
99template<class Impl>
100DefaultFetch<Impl>::DefaultFetch(Params *params)
101 : mem(params->mem),
102 branchPred(params),
103 decodeToFetchDelay(params->decodeToFetchDelay),
104 renameToFetchDelay(params->renameToFetchDelay),
105 iewToFetchDelay(params->iewToFetchDelay),
106 commitToFetchDelay(params->commitToFetchDelay),
107 fetchWidth(params->fetchWidth),
108 cacheBlocked(false),
109 retryPkt(NULL),
110 retryTid(-1),

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1115
1116 // Make sure this is a valid index.
1117 assert(offset <= cacheBlkSize - instSize);
1118
1119 // Get the instruction from the array of the cache line.
1120 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1121 (&cacheData[tid][offset]));
1122
1123 ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid));
1124
1125 // Create a new DynInst from the instruction fetched.
1126 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1127 next_PC,
1128 inst_seq, cpu);
1129 instruction->setTid(tid);
1130
1131 instruction->setASID(tid);

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1158
1159 // Increment stat of fetched instructions.
1160 ++fetchedInsts;
1161
1162 // Move to the next instruction, unless we have a branch.
1163 fetch_PC = next_PC;
1164
1165 if (instruction->isQuiesce()) {
1166 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1167 curTick);
1168 fetchStatus[tid] = QuiescePending;
1169 ++numInst;
1170 status_change = true;
1171 break;
1172 }
1173
1174 offset += instSize;
1175

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1273
1274 toDecode->insts[numInst] = instruction;
1275 toDecode->size++;
1276
1277 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1278
1279 fetchStatus[tid] = TrapPending;
1280 status_change = true;
1281#else // !FULL_SYSTEM
1282 fetchStatus[tid] = TrapPending;
1283 status_change = true;
1284
1285#endif // FULL_SYSTEM
1286 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1287 tid, fault->name(), PC[tid]);
1288 }
1289}
1290
1291template<class Impl>
1292void
1293DefaultFetch<Impl>::recvRetry()
1294{
1295 if (retryPkt != NULL) {

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