1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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73 if (status == RangeChange)
74 return;
75
76 panic("DefaultFetch doesn't expect recvStatusChange callback!");
77}
78
79template<class Impl>
80bool
81DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
82{
83 if (pkt->isResponse()) {
84 fetch->processCacheCompletion(pkt);
85 }
86 //else Snooped a coherence request, just return
87 return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94 fetch->recvRetry();

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1113
1114 // Make sure this is a valid index.
1115 assert(offset <= cacheBlkSize - instSize);
1116
1117 // Get the instruction from the array of the cache line.
1118 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1119 (&cacheData[tid][offset]));
1120
1121 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1122
1123 // Create a new DynInst from the instruction fetched.
1124 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1125 next_PC,
1126 inst_seq, cpu);
1127 instruction->setTid(tid);
1128
1129 instruction->setASID(tid);

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