1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * Copyright (c) 2012-2013 AMD
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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55#include "arch/isa_traits.hh"
56#include "arch/utility.hh"
57#include "arch/vtophys.hh"
58#include "base/random.hh"
59#include "base/types.hh"
60#include "config/the_isa.hh"
61#include "cpu/base.hh"
62//#include "cpu/checker/cpu.hh"
63#include "cpu/o3/fetch.hh"
64#include "cpu/exetrace.hh"
65#include "debug/Activity.hh"
66#include "debug/Drain.hh"
67#include "debug/Fetch.hh"
68#include "debug/O3PipeView.hh"
69#include "mem/packet.hh"
70#include "params/DerivO3CPU.hh"
71#include "sim/byteswap.hh"
72#include "sim/core.hh"
73#include "sim/eventq.hh"
74#include "sim/full_system.hh"
75#include "sim/system.hh"

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91 retryPkt(NULL),
92 retryTid(InvalidThreadID),
93 cacheBlkSize(cpu->cacheLineSize()),
94 fetchBufferSize(params->fetchBufferSize),
95 fetchBufferMask(fetchBufferSize - 1),
96 fetchQueueSize(params->fetchQueueSize),
97 numThreads(params->numThreads),
98 numFetchingThreads(params->smtNumFetchingThreads),
99 finishTranslationEvent(this)
100{
101 if (numThreads > Impl::MaxThreads)
102 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
103 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
104 numThreads, static_cast<int>(Impl::MaxThreads));
105 if (fetchWidth > Impl::MaxWidth)
106 fatal("fetchWidth (%d) is larger than compiled limit (%d),\n"

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687
688 fetchBufferPC[tid] = fetchBufferBlockPC;
689 fetchBufferValid[tid] = false;
690 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
691
692 fetchedCacheLines++;
693
694 // Access the cache.
695 if (!cpu->getInstPort().sendTimingReq(data_pkt)) {
696 assert(retryPkt == NULL);
697 assert(retryTid == InvalidThreadID);
698 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
699
700 fetchStatus[tid] = IcacheWaitRetry;
701 retryPkt = data_pkt;
702 retryTid = tid;
703 cacheBlocked = true;

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1417void
1418DefaultFetch<Impl>::recvReqRetry()
1419{
1420 if (retryPkt != NULL) {
1421 assert(cacheBlocked);
1422 assert(retryTid != InvalidThreadID);
1423 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1424
1425 if (cpu->getInstPort().sendTimingReq(retryPkt)) {
1426 fetchStatus[retryTid] = IcacheWaitResponse;
1427 // Notify Fetch Request probe when a retryPkt is successfully sent.
1428 // Note that notify must be called before retryPkt is set to NULL.
1429 ppFetchRequestSent->notify(retryPkt->req);
1430 retryPkt = NULL;
1431 retryTid = InvalidThreadID;
1432 cacheBlocked = false;
1433 }

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1665 tid);
1666 } else {
1667 DPRINTF(Fetch, "[tid:%i] Unexpected fetch stall reason "
1668 "(Status: %i)\n",
1669 tid, fetchStatus[tid]);
1670 }
1671}
1672
1673#endif//__CPU_O3_FETCH_IMPL_HH__