1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <cstring>
46
47#include "arch/isa_traits.hh"
48#include "arch/utility.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "config/use_checker.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/o3/fetch.hh"
54#include "cpu/exetrace.hh"
55#include "debug/Activity.hh"
56#include "debug/Fetch.hh"
57#include "mem/packet.hh"
58#include "mem/request.hh"
59#include "params/DerivO3CPU.hh"
60#include "sim/byteswap.hh"
61#include "sim/core.hh"
62
63#if FULL_SYSTEM
64#include "arch/tlb.hh"
65#include "arch/vtophys.hh"
66#include "sim/system.hh"
67#endif // FULL_SYSTEM
68
69using namespace std;
70
71template<class Impl>
72void
73DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
74{
75 Port::setPeer(port);
76
77 fetch->setIcache();
78}
79
80template<class Impl>
81Tick
82DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
83{
84 panic("DefaultFetch doesn't expect recvAtomic callback!");
85 return curTick();
86}
87
88template<class Impl>
89void
90DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
91{
92 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
93 "functional call.");
94}
95
96template<class Impl>
97void
98DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
99{
100 if (status == RangeChange) {
101 if (!snoopRangeSent) {
102 snoopRangeSent = true;
103 sendStatusChange(Port::RangeChange);
104 }
105 return;
106 }
107
108 panic("DefaultFetch doesn't expect recvStatusChange callback!");
109}
110
111template<class Impl>
112bool
113DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
114{
115 DPRINTF(Fetch, "Received timing\n");
116 if (pkt->isResponse()) {
117 // We shouldn't ever get a block in ownership state
118 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
119
120 fetch->processCacheCompletion(pkt);
121 }
122 //else Snooped a coherence request, just return
123 return true;
124}
125
126template<class Impl>
127void
128DefaultFetch<Impl>::IcachePort::recvRetry()
129{
130 fetch->recvRetry();
131}
132
133template<class Impl>
134DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
135 : cpu(_cpu),
136 branchPred(params),
137 predecoder(NULL),
138 decodeToFetchDelay(params->decodeToFetchDelay),
139 renameToFetchDelay(params->renameToFetchDelay),
140 iewToFetchDelay(params->iewToFetchDelay),
141 commitToFetchDelay(params->commitToFetchDelay),
142 fetchWidth(params->fetchWidth),
143 cacheBlocked(false),
144 retryPkt(NULL),
145 retryTid(InvalidThreadID),
146 numThreads(params->numThreads),
147 numFetchingThreads(params->smtNumFetchingThreads),
148 interruptPending(false),
149 drainPending(false),
150 switchedOut(false)
151{
152 if (numThreads > Impl::MaxThreads)
153 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
154 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
155 numThreads, static_cast<int>(Impl::MaxThreads));
156
157 // Set fetch stage's status to inactive.
158 _status = Inactive;
159
160 std::string policy = params->smtFetchPolicy;
161
162 // Convert string to lowercase
163 std::transform(policy.begin(), policy.end(), policy.begin(),
164 (int(*)(int)) tolower);
165
166 // Figure out fetch policy
167 if (policy == "singlethread") {
168 fetchPolicy = SingleThread;
169 if (numThreads > 1)
170 panic("Invalid Fetch Policy for a SMT workload.");
171 } else if (policy == "roundrobin") {
172 fetchPolicy = RoundRobin;
173 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
174 } else if (policy == "branch") {
175 fetchPolicy = Branch;
176 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
177 } else if (policy == "iqcount") {
178 fetchPolicy = IQ;
179 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
180 } else if (policy == "lsqcount") {
181 fetchPolicy = LSQ;
182 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
183 } else {
184 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
185 " RoundRobin,LSQcount,IQcount}\n");
186 }
187
188 // Get the size of an instruction.
189 instSize = sizeof(TheISA::MachInst);
190
191 // Name is finally available, so create the port.
192 icachePort = new IcachePort(this);
193
194 icachePort->snoopRangeSent = false;
195
196#if USE_CHECKER
197 if (cpu->checker) {
198 cpu->checker->setIcachePort(icachePort);
199 }
200#endif
201}
202
203template <class Impl>
204std::string
205DefaultFetch<Impl>::name() const
206{
207 return cpu->name() + ".fetch";
208}
209
210template <class Impl>
211void
212DefaultFetch<Impl>::regStats()
213{
214 icacheStallCycles
215 .name(name() + ".icacheStallCycles")
216 .desc("Number of cycles fetch is stalled on an Icache miss")
217 .prereq(icacheStallCycles);
218
219 fetchedInsts
220 .name(name() + ".Insts")
221 .desc("Number of instructions fetch has processed")
222 .prereq(fetchedInsts);
223
224 fetchedBranches
225 .name(name() + ".Branches")
226 .desc("Number of branches that fetch encountered")
227 .prereq(fetchedBranches);
228
229 predictedBranches
230 .name(name() + ".predictedBranches")
231 .desc("Number of branches that fetch has predicted taken")
232 .prereq(predictedBranches);
233
234 fetchCycles
235 .name(name() + ".Cycles")
236 .desc("Number of cycles fetch has run and was not squashing or"
237 " blocked")
238 .prereq(fetchCycles);
239
240 fetchSquashCycles
241 .name(name() + ".SquashCycles")
242 .desc("Number of cycles fetch has spent squashing")
243 .prereq(fetchSquashCycles);
244
245 fetchTlbCycles
246 .name(name() + ".TlbCycles")
247 .desc("Number of cycles fetch has spent waiting for tlb")
248 .prereq(fetchTlbCycles);
249
250 fetchIdleCycles
251 .name(name() + ".IdleCycles")
252 .desc("Number of cycles fetch was idle")
253 .prereq(fetchIdleCycles);
254
255 fetchBlockedCycles
256 .name(name() + ".BlockedCycles")
257 .desc("Number of cycles fetch has spent blocked")
258 .prereq(fetchBlockedCycles);
259
260 fetchedCacheLines
261 .name(name() + ".CacheLines")
262 .desc("Number of cache lines fetched")
263 .prereq(fetchedCacheLines);
264
265 fetchMiscStallCycles
266 .name(name() + ".MiscStallCycles")
267 .desc("Number of cycles fetch has spent waiting on interrupts, or "
268 "bad addresses, or out of MSHRs")
269 .prereq(fetchMiscStallCycles);
270
271 fetchIcacheSquashes
272 .name(name() + ".IcacheSquashes")
273 .desc("Number of outstanding Icache misses that were squashed")
274 .prereq(fetchIcacheSquashes);
275
276 fetchTlbSquashes
277 .name(name() + ".ItlbSquashes")
278 .desc("Number of outstanding ITLB misses that were squashed")
279 .prereq(fetchTlbSquashes);
280
281 fetchNisnDist
282 .init(/* base value */ 0,
283 /* last value */ fetchWidth,
284 /* bucket size */ 1)
285 .name(name() + ".rateDist")
286 .desc("Number of instructions fetched each cycle (Total)")
287 .flags(Stats::pdf);
288
289 idleRate
290 .name(name() + ".idleRate")
291 .desc("Percent of cycles fetch was idle")
292 .prereq(idleRate);
293 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
294
295 branchRate
296 .name(name() + ".branchRate")
297 .desc("Number of branch fetches per cycle")
298 .flags(Stats::total);
299 branchRate = fetchedBranches / cpu->numCycles;
300
301 fetchRate
302 .name(name() + ".rate")
303 .desc("Number of inst fetches per cycle")
304 .flags(Stats::total);
305 fetchRate = fetchedInsts / cpu->numCycles;
306
307 branchPred.regStats();
308}
309
310template<class Impl>
311void
312DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
313{
314 timeBuffer = time_buffer;
315
316 // Create wires to get information from proper places in time buffer.
317 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
318 fromRename = timeBuffer->getWire(-renameToFetchDelay);
319 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
320 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
321}
322
323template<class Impl>
324void
325DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
326{
327 activeThreads = at_ptr;
328}
329
330template<class Impl>
331void
332DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
333{
334 fetchQueue = fq_ptr;
335
336 // Create wire to write information to proper place in fetch queue.
337 toDecode = fetchQueue->getWire(0);
338}
339
340template<class Impl>
341void
342DefaultFetch<Impl>::initStage()
343{
344 // Setup PC and nextPC with initial state.
345 for (ThreadID tid = 0; tid < numThreads; tid++) {
346 pc[tid] = cpu->pcState(tid);
347 fetchOffset[tid] = 0;
348 macroop[tid] = NULL;
349 }
350
351 for (ThreadID tid = 0; tid < numThreads; tid++) {
352
353 fetchStatus[tid] = Running;
354
355 priorityList.push_back(tid);
356
357 memReq[tid] = NULL;
358
359 stalls[tid].decode = false;
360 stalls[tid].rename = false;
361 stalls[tid].iew = false;
362 stalls[tid].commit = false;
363 }
364
365 // Schedule fetch to get the correct PC from the CPU
366 // scheduleFetchStartupEvent(1);
367
368 // Fetch needs to start fetching instructions at the very beginning,
369 // so it must start up in active state.
370 switchToActive();
371}
372
373template<class Impl>
374void
375DefaultFetch<Impl>::setIcache()
376{
377 // Size of cache block.
378 cacheBlkSize = icachePort->peerBlockSize();
379
380 // Create mask to get rid of offset bits.
381 cacheBlkMask = (cacheBlkSize - 1);
382
383 for (ThreadID tid = 0; tid < numThreads; tid++) {
384 // Create space to store a cache line.
385 cacheData[tid] = new uint8_t[cacheBlkSize];
386 cacheDataPC[tid] = 0;
387 cacheDataValid[tid] = false;
388 }
389}
390
391template<class Impl>
392void
393DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
394{
395 ThreadID tid = pkt->req->threadId();
396
397 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
398
399 assert(!pkt->wasNacked());
400
401 // Only change the status if it's still waiting on the icache access
402 // to return.
403 if (fetchStatus[tid] != IcacheWaitResponse ||
404 pkt->req != memReq[tid] ||
405 isSwitchedOut()) {
406 ++fetchIcacheSquashes;
407 delete pkt->req;
408 delete pkt;
409 return;
410 }
411
412 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
413 cacheDataValid[tid] = true;
414
415 if (!drainPending) {
416 // Wake up the CPU (if it went to sleep and was waiting on
417 // this completion event).
418 cpu->wakeCPU();
419
420 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
421 tid);
422
423 switchToActive();
424 }
425
426 // Only switch to IcacheAccessComplete if we're not stalled as well.
427 if (checkStall(tid)) {
428 fetchStatus[tid] = Blocked;
429 } else {
430 fetchStatus[tid] = IcacheAccessComplete;
431 }
432
433 // Reset the mem req to NULL.
434 delete pkt->req;
435 delete pkt;
436 memReq[tid] = NULL;
437}
438
439template <class Impl>
440bool
441DefaultFetch<Impl>::drain()
442{
443 // Fetch is ready to drain at any time.
444 cpu->signalDrained();
445 drainPending = true;
446 return true;
447}
448
449template <class Impl>
450void
451DefaultFetch<Impl>::resume()
452{
453 drainPending = false;
454}
455
456template <class Impl>
457void
458DefaultFetch<Impl>::switchOut()
459{
460 switchedOut = true;
461 // Branch predictor needs to have its state cleared.
462 branchPred.switchOut();
463}
464
465template <class Impl>
466void
467DefaultFetch<Impl>::takeOverFrom()
468{
469 // Reset all state
470 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
471 stalls[i].decode = 0;
472 stalls[i].rename = 0;
473 stalls[i].iew = 0;
474 stalls[i].commit = 0;
475 pc[i] = cpu->pcState(i);
476 fetchStatus[i] = Running;
477 }
478 numInst = 0;
479 wroteToTimeBuffer = false;
480 _status = Inactive;
481 switchedOut = false;
482 interruptPending = false;
483 branchPred.takeOverFrom();
484}
485
486template <class Impl>
487void
488DefaultFetch<Impl>::wakeFromQuiesce()
489{
490 DPRINTF(Fetch, "Waking up from quiesce\n");
491 // Hopefully this is safe
492 // @todo: Allow other threads to wake from quiesce.
493 fetchStatus[0] = Running;
494}
495
496template <class Impl>
497inline void
498DefaultFetch<Impl>::switchToActive()
499{
500 if (_status == Inactive) {
501 DPRINTF(Activity, "Activating stage.\n");
502
503 cpu->activateStage(O3CPU::FetchIdx);
504
505 _status = Active;
506 }
507}
508
509template <class Impl>
510inline void
511DefaultFetch<Impl>::switchToInactive()
512{
513 if (_status == Active) {
514 DPRINTF(Activity, "Deactivating stage.\n");
515
516 cpu->deactivateStage(O3CPU::FetchIdx);
517
518 _status = Inactive;
519 }
520}
521
522template <class Impl>
523bool
524DefaultFetch<Impl>::lookupAndUpdateNextPC(
525 DynInstPtr &inst, TheISA::PCState &nextPC)
526{
527 // Do branch prediction check here.
528 // A bit of a misnomer...next_PC is actually the current PC until
529 // this function updates it.
530 bool predict_taken;
531
532 if (!inst->isControl()) {
533 TheISA::advancePC(nextPC, inst->staticInst);
534 inst->setPredTarg(nextPC);
535 inst->setPredTaken(false);
536 return false;
537 }
538
539 ThreadID tid = inst->threadNumber;
540 predict_taken = branchPred.predict(inst, nextPC, tid);
541
542 if (predict_taken) {
543 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n",
544 tid, inst->seqNum, nextPC);
545 } else {
546 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
547 tid, inst->seqNum);
548 }
549
550 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
551 tid, inst->seqNum, nextPC);
552 inst->setPredTarg(nextPC);
553 inst->setPredTaken(predict_taken);
554
555 ++fetchedBranches;
556
557 if (predict_taken) {
558 ++predictedBranches;
559 }
560
561 return predict_taken;
562}
563
564template <class Impl>
565bool
566DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
567{
568 Fault fault = NoFault;
569
570 // @todo: not sure if these should block translation.
571 //AlphaDep
572 if (cacheBlocked) {
573 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
574 tid);
575 return false;
576 } else if (isSwitchedOut()) {
577 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
578 tid);
579 return false;
580 } else if (checkInterrupt(pc)) {
581 // Hold off fetch from getting new instructions when:
582 // Cache is blocked, or
583 // while an interrupt is pending and we're not in PAL mode, or
584 // fetch is switched out.
585 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
586 tid);
587 return false;
588 }
589
590 // Align the fetch address so it's at the start of a cache block.
591 Addr block_PC = icacheBlockAlignPC(vaddr);
592
593 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
594 tid, block_PC, vaddr);
595
596 // Setup the memReq to do a read of the first instruction's address.
597 // Set the appropriate read size and flags as well.
598 // Build request here.
599 RequestPtr mem_req =
600 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
601 pc, cpu->thread[tid]->contextId(), tid);
602
603 memReq[tid] = mem_req;
604
605 // Initiate translation of the icache block
606 fetchStatus[tid] = ItlbWait;
607 FetchTranslation *trans = new FetchTranslation(this);
608 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
609 trans, BaseTLB::Execute);
610 return true;
611}
612
613template <class Impl>
614void
615DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
616{
617 ThreadID tid = mem_req->threadId();
618 Addr block_PC = mem_req->getVaddr();
619
620 // Wake up CPU if it was idle
621 cpu->wakeCPU();
622
623 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
624 mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) {
625 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
626 tid);
627 ++fetchTlbSquashes;
628 delete mem_req;
629 return;
630 }
631
632
633 // If translation was successful, attempt to read the icache block.
634 if (fault == NoFault) {
635 // Build packet here.
636 PacketPtr data_pkt = new Packet(mem_req,
637 MemCmd::ReadReq, Packet::Broadcast);
638 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
639
640 cacheDataPC[tid] = block_PC;
641 cacheDataValid[tid] = false;
642 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
643
644 fetchedCacheLines++;
645
646 // Access the cache.
647 if (!icachePort->sendTiming(data_pkt)) {
648 assert(retryPkt == NULL);
649 assert(retryTid == InvalidThreadID);
650 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
651
652 fetchStatus[tid] = IcacheWaitRetry;
653 retryPkt = data_pkt;
654 retryTid = tid;
655 cacheBlocked = true;
656 } else {
657 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
658 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
659 "response.\n", tid);
660
661 lastIcacheStall[tid] = curTick();
662 fetchStatus[tid] = IcacheWaitResponse;
663 }
664 } else {
665 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
666 mem_req->getVaddr(), memReq[tid]->getVaddr());
667 // Translation faulted, icache request won't be sent.
668 delete mem_req;
669 memReq[tid] = NULL;
670
671 // Send the fault to commit. This thread will not do anything
672 // until commit handles the fault. The only other way it can
673 // wake up is if a squash comes along and changes the PC.
674 TheISA::PCState fetchPC = pc[tid];
675
676 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
677 // We will use a nop in ordier to carry the fault.
678 DynInstPtr instruction = buildInst(tid,
679 StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()),
680 NULL, fetchPC, fetchPC, false);
681
682 instruction->setPredTarg(fetchPC);
683 instruction->fault = fault;
684 wroteToTimeBuffer = true;
685
686 DPRINTF(Activity, "Activity this cycle.\n");
687 cpu->activityThisCycle();
688
689 fetchStatus[tid] = TrapPending;
690
691 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);
692 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n",
693 tid, fault->name(), pc[tid]);
694 }
695 _status = updateFetchStatus();
696}
697
698template <class Impl>
699inline void
700DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
701{
702 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
703 tid, newPC);
704
705 pc[tid] = newPC;
706 fetchOffset[tid] = 0;
707 macroop[tid] = NULL;
708 predecoder.reset();
709
710 // Clear the icache miss if it's outstanding.
711 if (fetchStatus[tid] == IcacheWaitResponse) {
712 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
713 tid);
714 memReq[tid] = NULL;
715 } else if (fetchStatus[tid] == ItlbWait) {
716 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
717 tid);
718 memReq[tid] = NULL;
719 }
720
721 // Get rid of the retrying packet if it was from this thread.
722 if (retryTid == tid) {
723 assert(cacheBlocked);
724 if (retryPkt) {
725 delete retryPkt->req;
726 delete retryPkt;
727 }
728 retryPkt = NULL;
729 retryTid = InvalidThreadID;
730 }
731
732 fetchStatus[tid] = Squashing;
733
734 ++fetchSquashCycles;
735}
736
737template<class Impl>
738void
739DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
740 const InstSeqNum &seq_num, ThreadID tid)
741{
742 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
743
744 doSquash(newPC, tid);
745
746 // Tell the CPU to remove any instructions that are in flight between
747 // fetch and decode.
748 cpu->removeInstsUntil(seq_num, tid);
749}
750
751template<class Impl>
752bool
753DefaultFetch<Impl>::checkStall(ThreadID tid) const
754{
755 bool ret_val = false;
756
757 if (cpu->contextSwitch) {
758 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
759 ret_val = true;
760 } else if (stalls[tid].decode) {
761 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
762 ret_val = true;
763 } else if (stalls[tid].rename) {
764 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
765 ret_val = true;
766 } else if (stalls[tid].iew) {
767 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
768 ret_val = true;
769 } else if (stalls[tid].commit) {
770 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
771 ret_val = true;
772 }
773
774 return ret_val;
775}
776
777template<class Impl>
778typename DefaultFetch<Impl>::FetchStatus
779DefaultFetch<Impl>::updateFetchStatus()
780{
781 //Check Running
782 list<ThreadID>::iterator threads = activeThreads->begin();
783 list<ThreadID>::iterator end = activeThreads->end();
784
785 while (threads != end) {
786 ThreadID tid = *threads++;
787
788 if (fetchStatus[tid] == Running ||
789 fetchStatus[tid] == Squashing ||
790 fetchStatus[tid] == IcacheAccessComplete) {
791
792 if (_status == Inactive) {
793 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
794
795 if (fetchStatus[tid] == IcacheAccessComplete) {
796 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
797 "completion\n",tid);
798 }
799
800 cpu->activateStage(O3CPU::FetchIdx);
801 }
802
803 return Active;
804 }
805 }
806
807 // Stage is switching from active to inactive, notify CPU of it.
808 if (_status == Active) {
809 DPRINTF(Activity, "Deactivating stage.\n");
810
811 cpu->deactivateStage(O3CPU::FetchIdx);
812 }
813
814 return Inactive;
815}
816
817template <class Impl>
818void
819DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
820 const InstSeqNum &seq_num, DynInstPtr &squashInst,
821 ThreadID tid)
822{
823 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
824
825 doSquash(newPC, tid);
826
827 // Tell the CPU to remove any instructions that are not in the ROB.
828 cpu->removeInstsNotInROB(tid);
829}
830
831template <class Impl>
832void
833DefaultFetch<Impl>::tick()
834{
835 list<ThreadID>::iterator threads = activeThreads->begin();
836 list<ThreadID>::iterator end = activeThreads->end();
837 bool status_change = false;
838
839 wroteToTimeBuffer = false;
840
841 while (threads != end) {
842 ThreadID tid = *threads++;
843
844 // Check the signals for each thread to determine the proper status
845 // for each thread.
846 bool updated_status = checkSignalsAndUpdate(tid);
847 status_change = status_change || updated_status;
848 }
849
850 DPRINTF(Fetch, "Running stage.\n");
851
852 // Reset the number of the instruction we're fetching.
853 numInst = 0;
854
855#if FULL_SYSTEM
856 if (fromCommit->commitInfo[0].interruptPending) {
857 interruptPending = true;
858 }
859
860 if (fromCommit->commitInfo[0].clearInterrupt) {
861 interruptPending = false;
862 }
863#endif
864
865 for (threadFetched = 0; threadFetched < numFetchingThreads;
866 threadFetched++) {
867 // Fetch each of the actively fetching threads.
868 fetch(status_change);
869 }
870
871 // Record number of instructions fetched this cycle for distribution.
872 fetchNisnDist.sample(numInst);
873
874 if (status_change) {
875 // Change the fetch stage status if there was a status change.
876 _status = updateFetchStatus();
877 }
878
879 // If there was activity this cycle, inform the CPU of it.
880 if (wroteToTimeBuffer || cpu->contextSwitch) {
881 DPRINTF(Activity, "Activity this cycle.\n");
882
883 cpu->activityThisCycle();
884 }
885}
886
887template <class Impl>
888bool
889DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
890{
891 // Update the per thread stall statuses.
892 if (fromDecode->decodeBlock[tid]) {
893 stalls[tid].decode = true;
894 }
895
896 if (fromDecode->decodeUnblock[tid]) {
897 assert(stalls[tid].decode);
898 assert(!fromDecode->decodeBlock[tid]);
899 stalls[tid].decode = false;
900 }
901
902 if (fromRename->renameBlock[tid]) {
903 stalls[tid].rename = true;
904 }
905
906 if (fromRename->renameUnblock[tid]) {
907 assert(stalls[tid].rename);
908 assert(!fromRename->renameBlock[tid]);
909 stalls[tid].rename = false;
910 }
911
912 if (fromIEW->iewBlock[tid]) {
913 stalls[tid].iew = true;
914 }
915
916 if (fromIEW->iewUnblock[tid]) {
917 assert(stalls[tid].iew);
918 assert(!fromIEW->iewBlock[tid]);
919 stalls[tid].iew = false;
920 }
921
922 if (fromCommit->commitBlock[tid]) {
923 stalls[tid].commit = true;
924 }
925
926 if (fromCommit->commitUnblock[tid]) {
927 assert(stalls[tid].commit);
928 assert(!fromCommit->commitBlock[tid]);
929 stalls[tid].commit = false;
930 }
931
932 // Check squash signals from commit.
933 if (fromCommit->commitInfo[tid].squash) {
934
935 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
936 "from commit.\n",tid);
937 // In any case, squash.
938 squash(fromCommit->commitInfo[tid].pc,
939 fromCommit->commitInfo[tid].doneSeqNum,
940 fromCommit->commitInfo[tid].squashInst, tid);
941
942 // If it was a branch mispredict on a control instruction, update the
943 // branch predictor with that instruction, otherwise just kill the
944 // invalid state we generated in after sequence number
945 if (fromCommit->commitInfo[tid].mispredictInst &&
946 fromCommit->commitInfo[tid].mispredictInst->isControl()) {
947 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
948 fromCommit->commitInfo[tid].pc,
949 fromCommit->commitInfo[tid].branchTaken,
950 tid);
951 } else {
952 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
953 tid);
954 }
955
956 return true;
957 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
958 // Update the branch predictor if it wasn't a squashed instruction
959 // that was broadcasted.
960 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
961 }
962
963 // Check ROB squash signals from commit.
964 if (fromCommit->commitInfo[tid].robSquashing) {
965 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
966
967 // Continue to squash.
968 fetchStatus[tid] = Squashing;
969
970 return true;
971 }
972
973 // Check squash signals from decode.
974 if (fromDecode->decodeInfo[tid].squash) {
975 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
976 "from decode.\n",tid);
977
978 // Update the branch predictor.
979 if (fromDecode->decodeInfo[tid].branchMispredict) {
980 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
981 fromDecode->decodeInfo[tid].nextPC,
982 fromDecode->decodeInfo[tid].branchTaken,
983 tid);
984 } else {
985 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
986 tid);
987 }
988
989 if (fetchStatus[tid] != Squashing) {
990
991 TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
992 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
993 // Squash unless we're already squashing
994 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
995 fromDecode->decodeInfo[tid].doneSeqNum,
996 tid);
997
998 return true;
999 }
1000 }
1001
1002 if (checkStall(tid) &&
1003 fetchStatus[tid] != IcacheWaitResponse &&
1004 fetchStatus[tid] != IcacheWaitRetry) {
1005 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
1006
1007 fetchStatus[tid] = Blocked;
1008
1009 return true;
1010 }
1011
1012 if (fetchStatus[tid] == Blocked ||
1013 fetchStatus[tid] == Squashing) {
1014 // Switch status to running if fetch isn't being told to block or
1015 // squash this cycle.
1016 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1017 tid);
1018
1019 fetchStatus[tid] = Running;
1020
1021 return true;
1022 }
1023
1024 // If we've reached this point, we have not gotten any signals that
1025 // cause fetch to change its status. Fetch remains the same as before.
1026 return false;
1027}
1028
1029template<class Impl>
1030typename Impl::DynInstPtr
1031DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
1032 StaticInstPtr curMacroop, TheISA::PCState thisPC,
1033 TheISA::PCState nextPC, bool trace)
1034{
1035 // Get a sequence number.
1036 InstSeqNum seq = cpu->getAndIncrementInstSeq();
1037
1038 // Create a new DynInst from the instruction fetched.
1039 DynInstPtr instruction =
1040 new DynInst(staticInst, thisPC, nextPC, seq, cpu);
1041 instruction->setTid(tid);
1042
1043 instruction->setASID(tid);
1044
1045 instruction->setThreadState(cpu->thread[tid]);
1046
1047 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1048 "[sn:%lli].\n", tid, thisPC.instAddr(),
1049 thisPC.microPC(), seq);
1050
1051 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
1052 instruction->staticInst->
1053 disassemble(thisPC.instAddr()));
1054
1055#if TRACING_ON
1056 if (trace) {
1057 instruction->traceData =
1058 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1059 instruction->staticInst, thisPC, curMacroop);
1060 }
1061#else
1062 instruction->traceData = NULL;
1063#endif
1064
1065 // Add instruction to the CPU's list of instructions.
1066 instruction->setInstListIt(cpu->addInst(instruction));
1067
1068 // Write the instruction to the first slot in the queue
1069 // that heads to decode.
1070 assert(numInst < fetchWidth);
1071 toDecode->insts[toDecode->size++] = instruction;
1072
1073 return instruction;
1074}
1075
1076template<class Impl>
1077void
1078DefaultFetch<Impl>::fetch(bool &status_change)
1079{
1080 //////////////////////////////////////////
1081 // Start actual fetch
1082 //////////////////////////////////////////
1083 ThreadID tid = getFetchingThread(fetchPolicy);
1084
1085 if (tid == InvalidThreadID || drainPending) {
1086 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1087
1088 // Breaks looping condition in tick()
1089 threadFetched = numFetchingThreads;
1090 return;
1091 }
1092
1093 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1094
1095 // The current PC.
1096 TheISA::PCState thisPC = pc[tid];
1097
1098 Addr pcOffset = fetchOffset[tid];
1099 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1100
1101 bool inRom = isRomMicroPC(thisPC.microPC());
1102
1103 // If returning from the delay of a cache miss, then update the status
1104 // to running, otherwise do the cache access. Possibly move this up
1105 // to tick() function.
1106 if (fetchStatus[tid] == IcacheAccessComplete) {
1107 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1108
1109 fetchStatus[tid] = Running;
1110 status_change = true;
1111 } else if (fetchStatus[tid] == Running) {
1112 // Align the fetch PC so its at the start of a cache block.
1113 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1114
1115 // Unless buffer already got the block, fetch it from icache.
1116 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) {
1117 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1118 "instruction, starting at PC %s.\n", tid, thisPC);
1119
1120 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1121
1122 if (fetchStatus[tid] == IcacheWaitResponse)
1123 ++icacheStallCycles;
1124 else if (fetchStatus[tid] == ItlbWait)
1125 ++fetchTlbCycles;
1126 else
1127 ++fetchMiscStallCycles;
1128 return;
1129 } else if (checkInterrupt(thisPC.instAddr()) || isSwitchedOut()) {
1130 ++fetchMiscStallCycles;
1131 return;
1132 }
1133 } else {
1134 if (fetchStatus[tid] == Idle) {
1135 ++fetchIdleCycles;
1136 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1137 } else if (fetchStatus[tid] == Blocked) {
1138 ++fetchBlockedCycles;
1139 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1140 } else if (fetchStatus[tid] == Squashing) {
1141 ++fetchSquashCycles;
1142 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1143 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1144 ++icacheStallCycles;
1145 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1146 tid);
1147 } else if (fetchStatus[tid] == ItlbWait) {
1148 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1149 "finish! \n", tid);
1150 ++fetchTlbCycles;
1151 } else if (fetchStatus[tid] == TrapPending) {
1152 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n",
1153 tid);
1154 }
1155
1156
1157 // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse
1158 // so fetch should do nothing.
1159 return;
1160 }
1161
1162 ++fetchCycles;
1163
1164 TheISA::PCState nextPC = thisPC;
1165
1166 StaticInstPtr staticInst = NULL;
1167 StaticInstPtr curMacroop = macroop[tid];
1168
1169 // If the read of the first instruction was successful, then grab the
1170 // instructions from the rest of the cache line and put them into the
1171 // queue heading to decode.
1172
1173 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1174 "decode.\n", tid);
1175
1176 // Need to keep track of whether or not a predicted branch
1177 // ended this fetch block.
1178 bool predictedBranch = false;
1179
1180 TheISA::MachInst *cacheInsts =
1181 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1182
1183 const unsigned numInsts = cacheBlkSize / instSize;
1184 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1185
1186 // Loop through instruction memory from the cache.
1187 while (blkOffset < numInsts &&
1188 numInst < fetchWidth &&
1189 !predictedBranch) {
1190
1191 // If we need to process more memory, do it now.
1192 if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) {
1193 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
1194 // Walk past any annulled delay slot instructions.
1195 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
1196 while (fetchAddr != pcAddr && blkOffset < numInsts) {
1197 blkOffset++;
1198 fetchAddr += instSize;
1199 }
1200 if (blkOffset >= numInsts)
1201 break;
1202 }
1203 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
1204
1205 predecoder.setTC(cpu->thread[tid]->getTC());
1206 predecoder.moreBytes(thisPC, fetchAddr, inst);
1207
1208 if (predecoder.needMoreBytes()) {
1209 blkOffset++;
1210 fetchAddr += instSize;
1211 pcOffset += instSize;
1212 }
1213 }
1214
1215 // Extract as many instructions and/or microops as we can from
1216 // the memory we've processed so far.
1217 do {
1218 if (!(curMacroop || inRom)) {
1219 if (predecoder.extMachInstReady()) {
1220 ExtMachInst extMachInst;
1221
1222 extMachInst = predecoder.getExtMachInst(thisPC);
1223 staticInst = StaticInstPtr(extMachInst,
1224 thisPC.instAddr());
1225
1226 // Increment stat of fetched instructions.
1227 ++fetchedInsts;
1228
1229 if (staticInst->isMacroop()) {
1230 curMacroop = staticInst;
1231 } else {
1232 pcOffset = 0;
1233 }
1234 } else {
1235 // We need more bytes for this instruction.
1236 break;
1237 }
1238 }
1239 if (curMacroop || inRom) {
1240 if (inRom) {
1241 staticInst = cpu->microcodeRom.fetchMicroop(
1242 thisPC.microPC(), curMacroop);
1243 } else {
1244 staticInst = curMacroop->fetchMicroop(thisPC.microPC());
1245 }
1246 if (staticInst->isLastMicroop()) {
1247 curMacroop = NULL;
1248 pcOffset = 0;
1249 }
1250 }
1251
1252 DynInstPtr instruction =
1253 buildInst(tid, staticInst, curMacroop,
1254 thisPC, nextPC, true);
1255
1256 numInst++;
1257
1258 nextPC = thisPC;
1259
1260 // If we're branching after this instruction, quite fetching
1261 // from the same block then.
1262 predictedBranch |= thisPC.branching();
1263 predictedBranch |=
1264 lookupAndUpdateNextPC(instruction, nextPC);
1265 if (predictedBranch) {
1266 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC);
1267 }
1268
1269 // Move to the next instruction, unless we have a branch.
1270 thisPC = nextPC;
1271
1272 if (instruction->isQuiesce()) {
1273 DPRINTF(Fetch,
1274 "Quiesce instruction encountered, halting fetch!");
1275 fetchStatus[tid] = QuiescePending;
1276 status_change = true;
1277 break;
1278 }
1279 } while ((curMacroop || predecoder.extMachInstReady()) &&
1280 numInst < fetchWidth);
1281 }
1282
1283 if (predictedBranch) {
1284 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1285 "instruction encountered.\n", tid);
1286 } else if (numInst >= fetchWidth) {
1287 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1288 "for this cycle.\n", tid);
1289 } else if (blkOffset >= cacheBlkSize) {
1290 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1291 "block.\n", tid);
1292 }
1293
1294 macroop[tid] = curMacroop;
1295 fetchOffset[tid] = pcOffset;
1296
1297 if (numInst > 0) {
1298 wroteToTimeBuffer = true;
1299 }
1300
1301 pc[tid] = thisPC;
1302}
1303
1304template<class Impl>
1305void
1306DefaultFetch<Impl>::recvRetry()
1307{
1308 if (retryPkt != NULL) {
1309 assert(cacheBlocked);
1310 assert(retryTid != InvalidThreadID);
1311 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1312
1313 if (icachePort->sendTiming(retryPkt)) {
1314 fetchStatus[retryTid] = IcacheWaitResponse;
1315 retryPkt = NULL;
1316 retryTid = InvalidThreadID;
1317 cacheBlocked = false;
1318 }
1319 } else {
1320 assert(retryTid == InvalidThreadID);
1321 // Access has been squashed since it was sent out. Just clear
1322 // the cache being blocked.
1323 cacheBlocked = false;
1324 }
1325}
1326
1327///////////////////////////////////////
1328// //
1329// SMT FETCH POLICY MAINTAINED HERE //
1330// //
1331///////////////////////////////////////
1332template<class Impl>
1333ThreadID
1334DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1335{
1336 if (numThreads > 1) {
1337 switch (fetch_priority) {
1338
1339 case SingleThread:
1340 return 0;
1341
1342 case RoundRobin:
1343 return roundRobin();
1344
1345 case IQ:
1346 return iqCount();
1347
1348 case LSQ:
1349 return lsqCount();
1350
1351 case Branch:
1352 return branchCount();
1353
1354 default:
1355 return InvalidThreadID;
1356 }
1357 } else {
1358 list<ThreadID>::iterator thread = activeThreads->begin();
1359 if (thread == activeThreads->end()) {
1360 return InvalidThreadID;
1361 }
1362
1363 ThreadID tid = *thread;
1364
1365 if (fetchStatus[tid] == Running ||
1366 fetchStatus[tid] == IcacheAccessComplete ||
1367 fetchStatus[tid] == Idle) {
1368 return tid;
1369 } else {
1370 return InvalidThreadID;
1371 }
1372 }
1373}
1374
1375
1376template<class Impl>
1377ThreadID
1378DefaultFetch<Impl>::roundRobin()
1379{
1380 list<ThreadID>::iterator pri_iter = priorityList.begin();
1381 list<ThreadID>::iterator end = priorityList.end();
1382
1383 ThreadID high_pri;
1384
1385 while (pri_iter != end) {
1386 high_pri = *pri_iter;
1387
1388 assert(high_pri <= numThreads);
1389
1390 if (fetchStatus[high_pri] == Running ||
1391 fetchStatus[high_pri] == IcacheAccessComplete ||
1392 fetchStatus[high_pri] == Idle) {
1393
1394 priorityList.erase(pri_iter);
1395 priorityList.push_back(high_pri);
1396
1397 return high_pri;
1398 }
1399
1400 pri_iter++;
1401 }
1402
1403 return InvalidThreadID;
1404}
1405
1406template<class Impl>
1407ThreadID
1408DefaultFetch<Impl>::iqCount()
1409{
1410 std::priority_queue<unsigned> PQ;
1411 std::map<unsigned, ThreadID> threadMap;
1412
1413 list<ThreadID>::iterator threads = activeThreads->begin();
1414 list<ThreadID>::iterator end = activeThreads->end();
1415
1416 while (threads != end) {
1417 ThreadID tid = *threads++;
1418 unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
1419
1420 PQ.push(iqCount);
1421 threadMap[iqCount] = tid;
1422 }
1423
1424 while (!PQ.empty()) {
1425 ThreadID high_pri = threadMap[PQ.top()];
1426
1427 if (fetchStatus[high_pri] == Running ||
1428 fetchStatus[high_pri] == IcacheAccessComplete ||
1429 fetchStatus[high_pri] == Idle)
1430 return high_pri;
1431 else
1432 PQ.pop();
1433
1434 }
1435
1436 return InvalidThreadID;
1437}
1438
1439template<class Impl>
1440ThreadID
1441DefaultFetch<Impl>::lsqCount()
1442{
1443 std::priority_queue<unsigned> PQ;
1444 std::map<unsigned, ThreadID> threadMap;
1445
1446 list<ThreadID>::iterator threads = activeThreads->begin();
1447 list<ThreadID>::iterator end = activeThreads->end();
1448
1449 while (threads != end) {
1450 ThreadID tid = *threads++;
1451 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
1452
1453 PQ.push(ldstqCount);
1454 threadMap[ldstqCount] = tid;
1455 }
1456
1457 while (!PQ.empty()) {
1458 ThreadID high_pri = threadMap[PQ.top()];
1459
1460 if (fetchStatus[high_pri] == Running ||
1461 fetchStatus[high_pri] == IcacheAccessComplete ||
1462 fetchStatus[high_pri] == Idle)
1463 return high_pri;
1464 else
1465 PQ.pop();
1466 }
1467
1468 return InvalidThreadID;
1469}
1470
1471template<class Impl>
1472ThreadID
1473DefaultFetch<Impl>::branchCount()
1474{
1475#if 0
1476 list<ThreadID>::iterator thread = activeThreads->begin();
1477 assert(thread != activeThreads->end());
1478 ThreadID tid = *thread;
1479#endif
1480
1481 panic("Branch Count Fetch policy unimplemented\n");
1482 return InvalidThreadID;
1483}
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <cstring>
46
47#include "arch/isa_traits.hh"
48#include "arch/utility.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "config/use_checker.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/o3/fetch.hh"
54#include "cpu/exetrace.hh"
55#include "debug/Activity.hh"
56#include "debug/Fetch.hh"
57#include "mem/packet.hh"
58#include "mem/request.hh"
59#include "params/DerivO3CPU.hh"
60#include "sim/byteswap.hh"
61#include "sim/core.hh"
62
63#if FULL_SYSTEM
64#include "arch/tlb.hh"
65#include "arch/vtophys.hh"
66#include "sim/system.hh"
67#endif // FULL_SYSTEM
68
69using namespace std;
70
71template<class Impl>
72void
73DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
74{
75 Port::setPeer(port);
76
77 fetch->setIcache();
78}
79
80template<class Impl>
81Tick
82DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
83{
84 panic("DefaultFetch doesn't expect recvAtomic callback!");
85 return curTick();
86}
87
88template<class Impl>
89void
90DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
91{
92 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
93 "functional call.");
94}
95
96template<class Impl>
97void
98DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
99{
100 if (status == RangeChange) {
101 if (!snoopRangeSent) {
102 snoopRangeSent = true;
103 sendStatusChange(Port::RangeChange);
104 }
105 return;
106 }
107
108 panic("DefaultFetch doesn't expect recvStatusChange callback!");
109}
110
111template<class Impl>
112bool
113DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
114{
115 DPRINTF(Fetch, "Received timing\n");
116 if (pkt->isResponse()) {
117 // We shouldn't ever get a block in ownership state
118 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
119
120 fetch->processCacheCompletion(pkt);
121 }
122 //else Snooped a coherence request, just return
123 return true;
124}
125
126template<class Impl>
127void
128DefaultFetch<Impl>::IcachePort::recvRetry()
129{
130 fetch->recvRetry();
131}
132
133template<class Impl>
134DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
135 : cpu(_cpu),
136 branchPred(params),
137 predecoder(NULL),
138 decodeToFetchDelay(params->decodeToFetchDelay),
139 renameToFetchDelay(params->renameToFetchDelay),
140 iewToFetchDelay(params->iewToFetchDelay),
141 commitToFetchDelay(params->commitToFetchDelay),
142 fetchWidth(params->fetchWidth),
143 cacheBlocked(false),
144 retryPkt(NULL),
145 retryTid(InvalidThreadID),
146 numThreads(params->numThreads),
147 numFetchingThreads(params->smtNumFetchingThreads),
148 interruptPending(false),
149 drainPending(false),
150 switchedOut(false)
151{
152 if (numThreads > Impl::MaxThreads)
153 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
154 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
155 numThreads, static_cast<int>(Impl::MaxThreads));
156
157 // Set fetch stage's status to inactive.
158 _status = Inactive;
159
160 std::string policy = params->smtFetchPolicy;
161
162 // Convert string to lowercase
163 std::transform(policy.begin(), policy.end(), policy.begin(),
164 (int(*)(int)) tolower);
165
166 // Figure out fetch policy
167 if (policy == "singlethread") {
168 fetchPolicy = SingleThread;
169 if (numThreads > 1)
170 panic("Invalid Fetch Policy for a SMT workload.");
171 } else if (policy == "roundrobin") {
172 fetchPolicy = RoundRobin;
173 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
174 } else if (policy == "branch") {
175 fetchPolicy = Branch;
176 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
177 } else if (policy == "iqcount") {
178 fetchPolicy = IQ;
179 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
180 } else if (policy == "lsqcount") {
181 fetchPolicy = LSQ;
182 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
183 } else {
184 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
185 " RoundRobin,LSQcount,IQcount}\n");
186 }
187
188 // Get the size of an instruction.
189 instSize = sizeof(TheISA::MachInst);
190
191 // Name is finally available, so create the port.
192 icachePort = new IcachePort(this);
193
194 icachePort->snoopRangeSent = false;
195
196#if USE_CHECKER
197 if (cpu->checker) {
198 cpu->checker->setIcachePort(icachePort);
199 }
200#endif
201}
202
203template <class Impl>
204std::string
205DefaultFetch<Impl>::name() const
206{
207 return cpu->name() + ".fetch";
208}
209
210template <class Impl>
211void
212DefaultFetch<Impl>::regStats()
213{
214 icacheStallCycles
215 .name(name() + ".icacheStallCycles")
216 .desc("Number of cycles fetch is stalled on an Icache miss")
217 .prereq(icacheStallCycles);
218
219 fetchedInsts
220 .name(name() + ".Insts")
221 .desc("Number of instructions fetch has processed")
222 .prereq(fetchedInsts);
223
224 fetchedBranches
225 .name(name() + ".Branches")
226 .desc("Number of branches that fetch encountered")
227 .prereq(fetchedBranches);
228
229 predictedBranches
230 .name(name() + ".predictedBranches")
231 .desc("Number of branches that fetch has predicted taken")
232 .prereq(predictedBranches);
233
234 fetchCycles
235 .name(name() + ".Cycles")
236 .desc("Number of cycles fetch has run and was not squashing or"
237 " blocked")
238 .prereq(fetchCycles);
239
240 fetchSquashCycles
241 .name(name() + ".SquashCycles")
242 .desc("Number of cycles fetch has spent squashing")
243 .prereq(fetchSquashCycles);
244
245 fetchTlbCycles
246 .name(name() + ".TlbCycles")
247 .desc("Number of cycles fetch has spent waiting for tlb")
248 .prereq(fetchTlbCycles);
249
250 fetchIdleCycles
251 .name(name() + ".IdleCycles")
252 .desc("Number of cycles fetch was idle")
253 .prereq(fetchIdleCycles);
254
255 fetchBlockedCycles
256 .name(name() + ".BlockedCycles")
257 .desc("Number of cycles fetch has spent blocked")
258 .prereq(fetchBlockedCycles);
259
260 fetchedCacheLines
261 .name(name() + ".CacheLines")
262 .desc("Number of cache lines fetched")
263 .prereq(fetchedCacheLines);
264
265 fetchMiscStallCycles
266 .name(name() + ".MiscStallCycles")
267 .desc("Number of cycles fetch has spent waiting on interrupts, or "
268 "bad addresses, or out of MSHRs")
269 .prereq(fetchMiscStallCycles);
270
271 fetchIcacheSquashes
272 .name(name() + ".IcacheSquashes")
273 .desc("Number of outstanding Icache misses that were squashed")
274 .prereq(fetchIcacheSquashes);
275
276 fetchTlbSquashes
277 .name(name() + ".ItlbSquashes")
278 .desc("Number of outstanding ITLB misses that were squashed")
279 .prereq(fetchTlbSquashes);
280
281 fetchNisnDist
282 .init(/* base value */ 0,
283 /* last value */ fetchWidth,
284 /* bucket size */ 1)
285 .name(name() + ".rateDist")
286 .desc("Number of instructions fetched each cycle (Total)")
287 .flags(Stats::pdf);
288
289 idleRate
290 .name(name() + ".idleRate")
291 .desc("Percent of cycles fetch was idle")
292 .prereq(idleRate);
293 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
294
295 branchRate
296 .name(name() + ".branchRate")
297 .desc("Number of branch fetches per cycle")
298 .flags(Stats::total);
299 branchRate = fetchedBranches / cpu->numCycles;
300
301 fetchRate
302 .name(name() + ".rate")
303 .desc("Number of inst fetches per cycle")
304 .flags(Stats::total);
305 fetchRate = fetchedInsts / cpu->numCycles;
306
307 branchPred.regStats();
308}
309
310template<class Impl>
311void
312DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
313{
314 timeBuffer = time_buffer;
315
316 // Create wires to get information from proper places in time buffer.
317 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
318 fromRename = timeBuffer->getWire(-renameToFetchDelay);
319 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
320 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
321}
322
323template<class Impl>
324void
325DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
326{
327 activeThreads = at_ptr;
328}
329
330template<class Impl>
331void
332DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
333{
334 fetchQueue = fq_ptr;
335
336 // Create wire to write information to proper place in fetch queue.
337 toDecode = fetchQueue->getWire(0);
338}
339
340template<class Impl>
341void
342DefaultFetch<Impl>::initStage()
343{
344 // Setup PC and nextPC with initial state.
345 for (ThreadID tid = 0; tid < numThreads; tid++) {
346 pc[tid] = cpu->pcState(tid);
347 fetchOffset[tid] = 0;
348 macroop[tid] = NULL;
349 }
350
351 for (ThreadID tid = 0; tid < numThreads; tid++) {
352
353 fetchStatus[tid] = Running;
354
355 priorityList.push_back(tid);
356
357 memReq[tid] = NULL;
358
359 stalls[tid].decode = false;
360 stalls[tid].rename = false;
361 stalls[tid].iew = false;
362 stalls[tid].commit = false;
363 }
364
365 // Schedule fetch to get the correct PC from the CPU
366 // scheduleFetchStartupEvent(1);
367
368 // Fetch needs to start fetching instructions at the very beginning,
369 // so it must start up in active state.
370 switchToActive();
371}
372
373template<class Impl>
374void
375DefaultFetch<Impl>::setIcache()
376{
377 // Size of cache block.
378 cacheBlkSize = icachePort->peerBlockSize();
379
380 // Create mask to get rid of offset bits.
381 cacheBlkMask = (cacheBlkSize - 1);
382
383 for (ThreadID tid = 0; tid < numThreads; tid++) {
384 // Create space to store a cache line.
385 cacheData[tid] = new uint8_t[cacheBlkSize];
386 cacheDataPC[tid] = 0;
387 cacheDataValid[tid] = false;
388 }
389}
390
391template<class Impl>
392void
393DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
394{
395 ThreadID tid = pkt->req->threadId();
396
397 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
398
399 assert(!pkt->wasNacked());
400
401 // Only change the status if it's still waiting on the icache access
402 // to return.
403 if (fetchStatus[tid] != IcacheWaitResponse ||
404 pkt->req != memReq[tid] ||
405 isSwitchedOut()) {
406 ++fetchIcacheSquashes;
407 delete pkt->req;
408 delete pkt;
409 return;
410 }
411
412 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
413 cacheDataValid[tid] = true;
414
415 if (!drainPending) {
416 // Wake up the CPU (if it went to sleep and was waiting on
417 // this completion event).
418 cpu->wakeCPU();
419
420 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
421 tid);
422
423 switchToActive();
424 }
425
426 // Only switch to IcacheAccessComplete if we're not stalled as well.
427 if (checkStall(tid)) {
428 fetchStatus[tid] = Blocked;
429 } else {
430 fetchStatus[tid] = IcacheAccessComplete;
431 }
432
433 // Reset the mem req to NULL.
434 delete pkt->req;
435 delete pkt;
436 memReq[tid] = NULL;
437}
438
439template <class Impl>
440bool
441DefaultFetch<Impl>::drain()
442{
443 // Fetch is ready to drain at any time.
444 cpu->signalDrained();
445 drainPending = true;
446 return true;
447}
448
449template <class Impl>
450void
451DefaultFetch<Impl>::resume()
452{
453 drainPending = false;
454}
455
456template <class Impl>
457void
458DefaultFetch<Impl>::switchOut()
459{
460 switchedOut = true;
461 // Branch predictor needs to have its state cleared.
462 branchPred.switchOut();
463}
464
465template <class Impl>
466void
467DefaultFetch<Impl>::takeOverFrom()
468{
469 // Reset all state
470 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
471 stalls[i].decode = 0;
472 stalls[i].rename = 0;
473 stalls[i].iew = 0;
474 stalls[i].commit = 0;
475 pc[i] = cpu->pcState(i);
476 fetchStatus[i] = Running;
477 }
478 numInst = 0;
479 wroteToTimeBuffer = false;
480 _status = Inactive;
481 switchedOut = false;
482 interruptPending = false;
483 branchPred.takeOverFrom();
484}
485
486template <class Impl>
487void
488DefaultFetch<Impl>::wakeFromQuiesce()
489{
490 DPRINTF(Fetch, "Waking up from quiesce\n");
491 // Hopefully this is safe
492 // @todo: Allow other threads to wake from quiesce.
493 fetchStatus[0] = Running;
494}
495
496template <class Impl>
497inline void
498DefaultFetch<Impl>::switchToActive()
499{
500 if (_status == Inactive) {
501 DPRINTF(Activity, "Activating stage.\n");
502
503 cpu->activateStage(O3CPU::FetchIdx);
504
505 _status = Active;
506 }
507}
508
509template <class Impl>
510inline void
511DefaultFetch<Impl>::switchToInactive()
512{
513 if (_status == Active) {
514 DPRINTF(Activity, "Deactivating stage.\n");
515
516 cpu->deactivateStage(O3CPU::FetchIdx);
517
518 _status = Inactive;
519 }
520}
521
522template <class Impl>
523bool
524DefaultFetch<Impl>::lookupAndUpdateNextPC(
525 DynInstPtr &inst, TheISA::PCState &nextPC)
526{
527 // Do branch prediction check here.
528 // A bit of a misnomer...next_PC is actually the current PC until
529 // this function updates it.
530 bool predict_taken;
531
532 if (!inst->isControl()) {
533 TheISA::advancePC(nextPC, inst->staticInst);
534 inst->setPredTarg(nextPC);
535 inst->setPredTaken(false);
536 return false;
537 }
538
539 ThreadID tid = inst->threadNumber;
540 predict_taken = branchPred.predict(inst, nextPC, tid);
541
542 if (predict_taken) {
543 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n",
544 tid, inst->seqNum, nextPC);
545 } else {
546 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
547 tid, inst->seqNum);
548 }
549
550 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
551 tid, inst->seqNum, nextPC);
552 inst->setPredTarg(nextPC);
553 inst->setPredTaken(predict_taken);
554
555 ++fetchedBranches;
556
557 if (predict_taken) {
558 ++predictedBranches;
559 }
560
561 return predict_taken;
562}
563
564template <class Impl>
565bool
566DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
567{
568 Fault fault = NoFault;
569
570 // @todo: not sure if these should block translation.
571 //AlphaDep
572 if (cacheBlocked) {
573 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
574 tid);
575 return false;
576 } else if (isSwitchedOut()) {
577 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
578 tid);
579 return false;
580 } else if (checkInterrupt(pc)) {
581 // Hold off fetch from getting new instructions when:
582 // Cache is blocked, or
583 // while an interrupt is pending and we're not in PAL mode, or
584 // fetch is switched out.
585 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
586 tid);
587 return false;
588 }
589
590 // Align the fetch address so it's at the start of a cache block.
591 Addr block_PC = icacheBlockAlignPC(vaddr);
592
593 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
594 tid, block_PC, vaddr);
595
596 // Setup the memReq to do a read of the first instruction's address.
597 // Set the appropriate read size and flags as well.
598 // Build request here.
599 RequestPtr mem_req =
600 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
601 pc, cpu->thread[tid]->contextId(), tid);
602
603 memReq[tid] = mem_req;
604
605 // Initiate translation of the icache block
606 fetchStatus[tid] = ItlbWait;
607 FetchTranslation *trans = new FetchTranslation(this);
608 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
609 trans, BaseTLB::Execute);
610 return true;
611}
612
613template <class Impl>
614void
615DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
616{
617 ThreadID tid = mem_req->threadId();
618 Addr block_PC = mem_req->getVaddr();
619
620 // Wake up CPU if it was idle
621 cpu->wakeCPU();
622
623 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
624 mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) {
625 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
626 tid);
627 ++fetchTlbSquashes;
628 delete mem_req;
629 return;
630 }
631
632
633 // If translation was successful, attempt to read the icache block.
634 if (fault == NoFault) {
635 // Build packet here.
636 PacketPtr data_pkt = new Packet(mem_req,
637 MemCmd::ReadReq, Packet::Broadcast);
638 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
639
640 cacheDataPC[tid] = block_PC;
641 cacheDataValid[tid] = false;
642 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
643
644 fetchedCacheLines++;
645
646 // Access the cache.
647 if (!icachePort->sendTiming(data_pkt)) {
648 assert(retryPkt == NULL);
649 assert(retryTid == InvalidThreadID);
650 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
651
652 fetchStatus[tid] = IcacheWaitRetry;
653 retryPkt = data_pkt;
654 retryTid = tid;
655 cacheBlocked = true;
656 } else {
657 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
658 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
659 "response.\n", tid);
660
661 lastIcacheStall[tid] = curTick();
662 fetchStatus[tid] = IcacheWaitResponse;
663 }
664 } else {
665 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
666 mem_req->getVaddr(), memReq[tid]->getVaddr());
667 // Translation faulted, icache request won't be sent.
668 delete mem_req;
669 memReq[tid] = NULL;
670
671 // Send the fault to commit. This thread will not do anything
672 // until commit handles the fault. The only other way it can
673 // wake up is if a squash comes along and changes the PC.
674 TheISA::PCState fetchPC = pc[tid];
675
676 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
677 // We will use a nop in ordier to carry the fault.
678 DynInstPtr instruction = buildInst(tid,
679 StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()),
680 NULL, fetchPC, fetchPC, false);
681
682 instruction->setPredTarg(fetchPC);
683 instruction->fault = fault;
684 wroteToTimeBuffer = true;
685
686 DPRINTF(Activity, "Activity this cycle.\n");
687 cpu->activityThisCycle();
688
689 fetchStatus[tid] = TrapPending;
690
691 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);
692 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n",
693 tid, fault->name(), pc[tid]);
694 }
695 _status = updateFetchStatus();
696}
697
698template <class Impl>
699inline void
700DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
701{
702 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
703 tid, newPC);
704
705 pc[tid] = newPC;
706 fetchOffset[tid] = 0;
707 macroop[tid] = NULL;
708 predecoder.reset();
709
710 // Clear the icache miss if it's outstanding.
711 if (fetchStatus[tid] == IcacheWaitResponse) {
712 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
713 tid);
714 memReq[tid] = NULL;
715 } else if (fetchStatus[tid] == ItlbWait) {
716 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
717 tid);
718 memReq[tid] = NULL;
719 }
720
721 // Get rid of the retrying packet if it was from this thread.
722 if (retryTid == tid) {
723 assert(cacheBlocked);
724 if (retryPkt) {
725 delete retryPkt->req;
726 delete retryPkt;
727 }
728 retryPkt = NULL;
729 retryTid = InvalidThreadID;
730 }
731
732 fetchStatus[tid] = Squashing;
733
734 ++fetchSquashCycles;
735}
736
737template<class Impl>
738void
739DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
740 const InstSeqNum &seq_num, ThreadID tid)
741{
742 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
743
744 doSquash(newPC, tid);
745
746 // Tell the CPU to remove any instructions that are in flight between
747 // fetch and decode.
748 cpu->removeInstsUntil(seq_num, tid);
749}
750
751template<class Impl>
752bool
753DefaultFetch<Impl>::checkStall(ThreadID tid) const
754{
755 bool ret_val = false;
756
757 if (cpu->contextSwitch) {
758 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
759 ret_val = true;
760 } else if (stalls[tid].decode) {
761 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
762 ret_val = true;
763 } else if (stalls[tid].rename) {
764 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
765 ret_val = true;
766 } else if (stalls[tid].iew) {
767 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
768 ret_val = true;
769 } else if (stalls[tid].commit) {
770 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
771 ret_val = true;
772 }
773
774 return ret_val;
775}
776
777template<class Impl>
778typename DefaultFetch<Impl>::FetchStatus
779DefaultFetch<Impl>::updateFetchStatus()
780{
781 //Check Running
782 list<ThreadID>::iterator threads = activeThreads->begin();
783 list<ThreadID>::iterator end = activeThreads->end();
784
785 while (threads != end) {
786 ThreadID tid = *threads++;
787
788 if (fetchStatus[tid] == Running ||
789 fetchStatus[tid] == Squashing ||
790 fetchStatus[tid] == IcacheAccessComplete) {
791
792 if (_status == Inactive) {
793 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
794
795 if (fetchStatus[tid] == IcacheAccessComplete) {
796 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
797 "completion\n",tid);
798 }
799
800 cpu->activateStage(O3CPU::FetchIdx);
801 }
802
803 return Active;
804 }
805 }
806
807 // Stage is switching from active to inactive, notify CPU of it.
808 if (_status == Active) {
809 DPRINTF(Activity, "Deactivating stage.\n");
810
811 cpu->deactivateStage(O3CPU::FetchIdx);
812 }
813
814 return Inactive;
815}
816
817template <class Impl>
818void
819DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
820 const InstSeqNum &seq_num, DynInstPtr &squashInst,
821 ThreadID tid)
822{
823 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
824
825 doSquash(newPC, tid);
826
827 // Tell the CPU to remove any instructions that are not in the ROB.
828 cpu->removeInstsNotInROB(tid);
829}
830
831template <class Impl>
832void
833DefaultFetch<Impl>::tick()
834{
835 list<ThreadID>::iterator threads = activeThreads->begin();
836 list<ThreadID>::iterator end = activeThreads->end();
837 bool status_change = false;
838
839 wroteToTimeBuffer = false;
840
841 while (threads != end) {
842 ThreadID tid = *threads++;
843
844 // Check the signals for each thread to determine the proper status
845 // for each thread.
846 bool updated_status = checkSignalsAndUpdate(tid);
847 status_change = status_change || updated_status;
848 }
849
850 DPRINTF(Fetch, "Running stage.\n");
851
852 // Reset the number of the instruction we're fetching.
853 numInst = 0;
854
855#if FULL_SYSTEM
856 if (fromCommit->commitInfo[0].interruptPending) {
857 interruptPending = true;
858 }
859
860 if (fromCommit->commitInfo[0].clearInterrupt) {
861 interruptPending = false;
862 }
863#endif
864
865 for (threadFetched = 0; threadFetched < numFetchingThreads;
866 threadFetched++) {
867 // Fetch each of the actively fetching threads.
868 fetch(status_change);
869 }
870
871 // Record number of instructions fetched this cycle for distribution.
872 fetchNisnDist.sample(numInst);
873
874 if (status_change) {
875 // Change the fetch stage status if there was a status change.
876 _status = updateFetchStatus();
877 }
878
879 // If there was activity this cycle, inform the CPU of it.
880 if (wroteToTimeBuffer || cpu->contextSwitch) {
881 DPRINTF(Activity, "Activity this cycle.\n");
882
883 cpu->activityThisCycle();
884 }
885}
886
887template <class Impl>
888bool
889DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
890{
891 // Update the per thread stall statuses.
892 if (fromDecode->decodeBlock[tid]) {
893 stalls[tid].decode = true;
894 }
895
896 if (fromDecode->decodeUnblock[tid]) {
897 assert(stalls[tid].decode);
898 assert(!fromDecode->decodeBlock[tid]);
899 stalls[tid].decode = false;
900 }
901
902 if (fromRename->renameBlock[tid]) {
903 stalls[tid].rename = true;
904 }
905
906 if (fromRename->renameUnblock[tid]) {
907 assert(stalls[tid].rename);
908 assert(!fromRename->renameBlock[tid]);
909 stalls[tid].rename = false;
910 }
911
912 if (fromIEW->iewBlock[tid]) {
913 stalls[tid].iew = true;
914 }
915
916 if (fromIEW->iewUnblock[tid]) {
917 assert(stalls[tid].iew);
918 assert(!fromIEW->iewBlock[tid]);
919 stalls[tid].iew = false;
920 }
921
922 if (fromCommit->commitBlock[tid]) {
923 stalls[tid].commit = true;
924 }
925
926 if (fromCommit->commitUnblock[tid]) {
927 assert(stalls[tid].commit);
928 assert(!fromCommit->commitBlock[tid]);
929 stalls[tid].commit = false;
930 }
931
932 // Check squash signals from commit.
933 if (fromCommit->commitInfo[tid].squash) {
934
935 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
936 "from commit.\n",tid);
937 // In any case, squash.
938 squash(fromCommit->commitInfo[tid].pc,
939 fromCommit->commitInfo[tid].doneSeqNum,
940 fromCommit->commitInfo[tid].squashInst, tid);
941
942 // If it was a branch mispredict on a control instruction, update the
943 // branch predictor with that instruction, otherwise just kill the
944 // invalid state we generated in after sequence number
945 if (fromCommit->commitInfo[tid].mispredictInst &&
946 fromCommit->commitInfo[tid].mispredictInst->isControl()) {
947 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
948 fromCommit->commitInfo[tid].pc,
949 fromCommit->commitInfo[tid].branchTaken,
950 tid);
951 } else {
952 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
953 tid);
954 }
955
956 return true;
957 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
958 // Update the branch predictor if it wasn't a squashed instruction
959 // that was broadcasted.
960 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
961 }
962
963 // Check ROB squash signals from commit.
964 if (fromCommit->commitInfo[tid].robSquashing) {
965 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
966
967 // Continue to squash.
968 fetchStatus[tid] = Squashing;
969
970 return true;
971 }
972
973 // Check squash signals from decode.
974 if (fromDecode->decodeInfo[tid].squash) {
975 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
976 "from decode.\n",tid);
977
978 // Update the branch predictor.
979 if (fromDecode->decodeInfo[tid].branchMispredict) {
980 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
981 fromDecode->decodeInfo[tid].nextPC,
982 fromDecode->decodeInfo[tid].branchTaken,
983 tid);
984 } else {
985 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
986 tid);
987 }
988
989 if (fetchStatus[tid] != Squashing) {
990
991 TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
992 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
993 // Squash unless we're already squashing
994 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
995 fromDecode->decodeInfo[tid].doneSeqNum,
996 tid);
997
998 return true;
999 }
1000 }
1001
1002 if (checkStall(tid) &&
1003 fetchStatus[tid] != IcacheWaitResponse &&
1004 fetchStatus[tid] != IcacheWaitRetry) {
1005 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
1006
1007 fetchStatus[tid] = Blocked;
1008
1009 return true;
1010 }
1011
1012 if (fetchStatus[tid] == Blocked ||
1013 fetchStatus[tid] == Squashing) {
1014 // Switch status to running if fetch isn't being told to block or
1015 // squash this cycle.
1016 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1017 tid);
1018
1019 fetchStatus[tid] = Running;
1020
1021 return true;
1022 }
1023
1024 // If we've reached this point, we have not gotten any signals that
1025 // cause fetch to change its status. Fetch remains the same as before.
1026 return false;
1027}
1028
1029template<class Impl>
1030typename Impl::DynInstPtr
1031DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
1032 StaticInstPtr curMacroop, TheISA::PCState thisPC,
1033 TheISA::PCState nextPC, bool trace)
1034{
1035 // Get a sequence number.
1036 InstSeqNum seq = cpu->getAndIncrementInstSeq();
1037
1038 // Create a new DynInst from the instruction fetched.
1039 DynInstPtr instruction =
1040 new DynInst(staticInst, thisPC, nextPC, seq, cpu);
1041 instruction->setTid(tid);
1042
1043 instruction->setASID(tid);
1044
1045 instruction->setThreadState(cpu->thread[tid]);
1046
1047 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1048 "[sn:%lli].\n", tid, thisPC.instAddr(),
1049 thisPC.microPC(), seq);
1050
1051 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
1052 instruction->staticInst->
1053 disassemble(thisPC.instAddr()));
1054
1055#if TRACING_ON
1056 if (trace) {
1057 instruction->traceData =
1058 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1059 instruction->staticInst, thisPC, curMacroop);
1060 }
1061#else
1062 instruction->traceData = NULL;
1063#endif
1064
1065 // Add instruction to the CPU's list of instructions.
1066 instruction->setInstListIt(cpu->addInst(instruction));
1067
1068 // Write the instruction to the first slot in the queue
1069 // that heads to decode.
1070 assert(numInst < fetchWidth);
1071 toDecode->insts[toDecode->size++] = instruction;
1072
1073 return instruction;
1074}
1075
1076template<class Impl>
1077void
1078DefaultFetch<Impl>::fetch(bool &status_change)
1079{
1080 //////////////////////////////////////////
1081 // Start actual fetch
1082 //////////////////////////////////////////
1083 ThreadID tid = getFetchingThread(fetchPolicy);
1084
1085 if (tid == InvalidThreadID || drainPending) {
1086 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1087
1088 // Breaks looping condition in tick()
1089 threadFetched = numFetchingThreads;
1090 return;
1091 }
1092
1093 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1094
1095 // The current PC.
1096 TheISA::PCState thisPC = pc[tid];
1097
1098 Addr pcOffset = fetchOffset[tid];
1099 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1100
1101 bool inRom = isRomMicroPC(thisPC.microPC());
1102
1103 // If returning from the delay of a cache miss, then update the status
1104 // to running, otherwise do the cache access. Possibly move this up
1105 // to tick() function.
1106 if (fetchStatus[tid] == IcacheAccessComplete) {
1107 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1108
1109 fetchStatus[tid] = Running;
1110 status_change = true;
1111 } else if (fetchStatus[tid] == Running) {
1112 // Align the fetch PC so its at the start of a cache block.
1113 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1114
1115 // Unless buffer already got the block, fetch it from icache.
1116 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) {
1117 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1118 "instruction, starting at PC %s.\n", tid, thisPC);
1119
1120 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1121
1122 if (fetchStatus[tid] == IcacheWaitResponse)
1123 ++icacheStallCycles;
1124 else if (fetchStatus[tid] == ItlbWait)
1125 ++fetchTlbCycles;
1126 else
1127 ++fetchMiscStallCycles;
1128 return;
1129 } else if (checkInterrupt(thisPC.instAddr()) || isSwitchedOut()) {
1130 ++fetchMiscStallCycles;
1131 return;
1132 }
1133 } else {
1134 if (fetchStatus[tid] == Idle) {
1135 ++fetchIdleCycles;
1136 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1137 } else if (fetchStatus[tid] == Blocked) {
1138 ++fetchBlockedCycles;
1139 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1140 } else if (fetchStatus[tid] == Squashing) {
1141 ++fetchSquashCycles;
1142 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1143 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1144 ++icacheStallCycles;
1145 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1146 tid);
1147 } else if (fetchStatus[tid] == ItlbWait) {
1148 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1149 "finish! \n", tid);
1150 ++fetchTlbCycles;
1151 } else if (fetchStatus[tid] == TrapPending) {
1152 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n",
1153 tid);
1154 }
1155
1156
1157 // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse
1158 // so fetch should do nothing.
1159 return;
1160 }
1161
1162 ++fetchCycles;
1163
1164 TheISA::PCState nextPC = thisPC;
1165
1166 StaticInstPtr staticInst = NULL;
1167 StaticInstPtr curMacroop = macroop[tid];
1168
1169 // If the read of the first instruction was successful, then grab the
1170 // instructions from the rest of the cache line and put them into the
1171 // queue heading to decode.
1172
1173 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1174 "decode.\n", tid);
1175
1176 // Need to keep track of whether or not a predicted branch
1177 // ended this fetch block.
1178 bool predictedBranch = false;
1179
1180 TheISA::MachInst *cacheInsts =
1181 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1182
1183 const unsigned numInsts = cacheBlkSize / instSize;
1184 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1185
1186 // Loop through instruction memory from the cache.
1187 while (blkOffset < numInsts &&
1188 numInst < fetchWidth &&
1189 !predictedBranch) {
1190
1191 // If we need to process more memory, do it now.
1192 if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) {
1193 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
1194 // Walk past any annulled delay slot instructions.
1195 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
1196 while (fetchAddr != pcAddr && blkOffset < numInsts) {
1197 blkOffset++;
1198 fetchAddr += instSize;
1199 }
1200 if (blkOffset >= numInsts)
1201 break;
1202 }
1203 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
1204
1205 predecoder.setTC(cpu->thread[tid]->getTC());
1206 predecoder.moreBytes(thisPC, fetchAddr, inst);
1207
1208 if (predecoder.needMoreBytes()) {
1209 blkOffset++;
1210 fetchAddr += instSize;
1211 pcOffset += instSize;
1212 }
1213 }
1214
1215 // Extract as many instructions and/or microops as we can from
1216 // the memory we've processed so far.
1217 do {
1218 if (!(curMacroop || inRom)) {
1219 if (predecoder.extMachInstReady()) {
1220 ExtMachInst extMachInst;
1221
1222 extMachInst = predecoder.getExtMachInst(thisPC);
1223 staticInst = StaticInstPtr(extMachInst,
1224 thisPC.instAddr());
1225
1226 // Increment stat of fetched instructions.
1227 ++fetchedInsts;
1228
1229 if (staticInst->isMacroop()) {
1230 curMacroop = staticInst;
1231 } else {
1232 pcOffset = 0;
1233 }
1234 } else {
1235 // We need more bytes for this instruction.
1236 break;
1237 }
1238 }
1239 if (curMacroop || inRom) {
1240 if (inRom) {
1241 staticInst = cpu->microcodeRom.fetchMicroop(
1242 thisPC.microPC(), curMacroop);
1243 } else {
1244 staticInst = curMacroop->fetchMicroop(thisPC.microPC());
1245 }
1246 if (staticInst->isLastMicroop()) {
1247 curMacroop = NULL;
1248 pcOffset = 0;
1249 }
1250 }
1251
1252 DynInstPtr instruction =
1253 buildInst(tid, staticInst, curMacroop,
1254 thisPC, nextPC, true);
1255
1256 numInst++;
1257
1258 nextPC = thisPC;
1259
1260 // If we're branching after this instruction, quite fetching
1261 // from the same block then.
1262 predictedBranch |= thisPC.branching();
1263 predictedBranch |=
1264 lookupAndUpdateNextPC(instruction, nextPC);
1265 if (predictedBranch) {
1266 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC);
1267 }
1268
1269 // Move to the next instruction, unless we have a branch.
1270 thisPC = nextPC;
1271
1272 if (instruction->isQuiesce()) {
1273 DPRINTF(Fetch,
1274 "Quiesce instruction encountered, halting fetch!");
1275 fetchStatus[tid] = QuiescePending;
1276 status_change = true;
1277 break;
1278 }
1279 } while ((curMacroop || predecoder.extMachInstReady()) &&
1280 numInst < fetchWidth);
1281 }
1282
1283 if (predictedBranch) {
1284 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1285 "instruction encountered.\n", tid);
1286 } else if (numInst >= fetchWidth) {
1287 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1288 "for this cycle.\n", tid);
1289 } else if (blkOffset >= cacheBlkSize) {
1290 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1291 "block.\n", tid);
1292 }
1293
1294 macroop[tid] = curMacroop;
1295 fetchOffset[tid] = pcOffset;
1296
1297 if (numInst > 0) {
1298 wroteToTimeBuffer = true;
1299 }
1300
1301 pc[tid] = thisPC;
1302}
1303
1304template<class Impl>
1305void
1306DefaultFetch<Impl>::recvRetry()
1307{
1308 if (retryPkt != NULL) {
1309 assert(cacheBlocked);
1310 assert(retryTid != InvalidThreadID);
1311 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1312
1313 if (icachePort->sendTiming(retryPkt)) {
1314 fetchStatus[retryTid] = IcacheWaitResponse;
1315 retryPkt = NULL;
1316 retryTid = InvalidThreadID;
1317 cacheBlocked = false;
1318 }
1319 } else {
1320 assert(retryTid == InvalidThreadID);
1321 // Access has been squashed since it was sent out. Just clear
1322 // the cache being blocked.
1323 cacheBlocked = false;
1324 }
1325}
1326
1327///////////////////////////////////////
1328// //
1329// SMT FETCH POLICY MAINTAINED HERE //
1330// //
1331///////////////////////////////////////
1332template<class Impl>
1333ThreadID
1334DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1335{
1336 if (numThreads > 1) {
1337 switch (fetch_priority) {
1338
1339 case SingleThread:
1340 return 0;
1341
1342 case RoundRobin:
1343 return roundRobin();
1344
1345 case IQ:
1346 return iqCount();
1347
1348 case LSQ:
1349 return lsqCount();
1350
1351 case Branch:
1352 return branchCount();
1353
1354 default:
1355 return InvalidThreadID;
1356 }
1357 } else {
1358 list<ThreadID>::iterator thread = activeThreads->begin();
1359 if (thread == activeThreads->end()) {
1360 return InvalidThreadID;
1361 }
1362
1363 ThreadID tid = *thread;
1364
1365 if (fetchStatus[tid] == Running ||
1366 fetchStatus[tid] == IcacheAccessComplete ||
1367 fetchStatus[tid] == Idle) {
1368 return tid;
1369 } else {
1370 return InvalidThreadID;
1371 }
1372 }
1373}
1374
1375
1376template<class Impl>
1377ThreadID
1378DefaultFetch<Impl>::roundRobin()
1379{
1380 list<ThreadID>::iterator pri_iter = priorityList.begin();
1381 list<ThreadID>::iterator end = priorityList.end();
1382
1383 ThreadID high_pri;
1384
1385 while (pri_iter != end) {
1386 high_pri = *pri_iter;
1387
1388 assert(high_pri <= numThreads);
1389
1390 if (fetchStatus[high_pri] == Running ||
1391 fetchStatus[high_pri] == IcacheAccessComplete ||
1392 fetchStatus[high_pri] == Idle) {
1393
1394 priorityList.erase(pri_iter);
1395 priorityList.push_back(high_pri);
1396
1397 return high_pri;
1398 }
1399
1400 pri_iter++;
1401 }
1402
1403 return InvalidThreadID;
1404}
1405
1406template<class Impl>
1407ThreadID
1408DefaultFetch<Impl>::iqCount()
1409{
1410 std::priority_queue<unsigned> PQ;
1411 std::map<unsigned, ThreadID> threadMap;
1412
1413 list<ThreadID>::iterator threads = activeThreads->begin();
1414 list<ThreadID>::iterator end = activeThreads->end();
1415
1416 while (threads != end) {
1417 ThreadID tid = *threads++;
1418 unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
1419
1420 PQ.push(iqCount);
1421 threadMap[iqCount] = tid;
1422 }
1423
1424 while (!PQ.empty()) {
1425 ThreadID high_pri = threadMap[PQ.top()];
1426
1427 if (fetchStatus[high_pri] == Running ||
1428 fetchStatus[high_pri] == IcacheAccessComplete ||
1429 fetchStatus[high_pri] == Idle)
1430 return high_pri;
1431 else
1432 PQ.pop();
1433
1434 }
1435
1436 return InvalidThreadID;
1437}
1438
1439template<class Impl>
1440ThreadID
1441DefaultFetch<Impl>::lsqCount()
1442{
1443 std::priority_queue<unsigned> PQ;
1444 std::map<unsigned, ThreadID> threadMap;
1445
1446 list<ThreadID>::iterator threads = activeThreads->begin();
1447 list<ThreadID>::iterator end = activeThreads->end();
1448
1449 while (threads != end) {
1450 ThreadID tid = *threads++;
1451 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
1452
1453 PQ.push(ldstqCount);
1454 threadMap[ldstqCount] = tid;
1455 }
1456
1457 while (!PQ.empty()) {
1458 ThreadID high_pri = threadMap[PQ.top()];
1459
1460 if (fetchStatus[high_pri] == Running ||
1461 fetchStatus[high_pri] == IcacheAccessComplete ||
1462 fetchStatus[high_pri] == Idle)
1463 return high_pri;
1464 else
1465 PQ.pop();
1466 }
1467
1468 return InvalidThreadID;
1469}
1470
1471template<class Impl>
1472ThreadID
1473DefaultFetch<Impl>::branchCount()
1474{
1475#if 0
1476 list<ThreadID>::iterator thread = activeThreads->begin();
1477 assert(thread != activeThreads->end());
1478 ThreadID tid = *thread;
1479#endif
1480
1481 panic("Branch Count Fetch policy unimplemented\n");
1482 return InvalidThreadID;
1483}