1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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98DefaultFetch<Impl>::IcachePort::recvRetry()
99{
100 fetch->recvRetry();
101}
102
103template<class Impl>
104DefaultFetch<Impl>::DefaultFetch(Params *params)
105 : branchPred(params),
106 predecoder(NULL),
107 decodeToFetchDelay(params->decodeToFetchDelay),
108 renameToFetchDelay(params->renameToFetchDelay),
109 iewToFetchDelay(params->iewToFetchDelay),
110 commitToFetchDelay(params->commitToFetchDelay),
111 fetchWidth(params->fetchWidth),
112 cacheBlocked(false),
113 retryPkt(NULL),
114 retryTid(-1),

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1113
1114 // Make sure this is a valid index.
1115 assert(offset <= cacheBlkSize - instSize);
1116
1117 // Get the instruction from the array of the cache line.
1118 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1119 (&cacheData[tid][offset]));
1120
1121 predecoder.setTC(cpu->thread[tid]->getTC());
1122 predecoder.moreBytes(fetch_PC, 0, inst);
1123
1124 ext_inst = predecoder.getExtMachInst();
1125
1126 // Create a new DynInst from the instruction fetched.
1127 DynInstPtr instruction = new DynInst(ext_inst,
1128 fetch_PC, fetch_NPC,
1129 next_PC, next_NPC,
1130 inst_seq, cpu);
1131 instruction->setTid(tid);
1132
1133 instruction->setASID(tid);

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