1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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314template<class Impl>
315void
316DefaultFetch<Impl>::initStage()
317{
318 // Setup PC and nextPC with initial state.
319 for (int tid = 0; tid < numThreads; tid++) {
320 PC[tid] = cpu->readPC(tid);
321 nextPC[tid] = cpu->readNextPC(tid);
322 nextNPC[tid] = cpu->readNextNPC(tid);
323 }
324
325 // Size of cache block.
326 cacheBlkSize = icachePort->peerBlockSize();
327
328 // Create mask to get rid of offset bits.
329 cacheBlkMask = (cacheBlkSize - 1);
330

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497{
498 // Do branch prediction check here.
499 // A bit of a misnomer...next_PC is actually the current PC until
500 // this function updates it.
501 bool predict_taken;
502
503 if (!inst->isControl()) {
504#if ISA_HAS_DELAY_SLOT
505 next_PC = next_NPC;
506 next_NPC = next_NPC + instSize;
507 inst->setPredTarg(next_PC, next_NPC);
508#else
509 next_PC = next_PC + instSize;
510 inst->setPredTarg(next_PC, next_PC + sizeof(TheISA::MachInst));
511#endif
512 inst->setPredTaken(false);
513 return false;
514 }
515
516 int tid = inst->threadNumber;
517#if ISA_HAS_DELAY_SLOT
518 Addr pred_PC = next_PC;
519 predict_taken = branchPred.predict(inst, pred_PC, tid);
520
521 if (predict_taken) {
522 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken.\n", tid);
523 } else {
524 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid);
525 }
526
527 next_PC = next_NPC;
528 if (predict_taken) {
529 next_NPC = pred_PC;
530 // Update delay slot info
531 ++delaySlotInfo[tid].numInsts;
532 delaySlotInfo[tid].targetAddr = pred_PC;
533 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
534 delaySlotInfo[tid].numInsts);
535 } else {
536 next_NPC = next_NPC + instSize;
537 }
538#else
539 predict_taken = branchPred.predict(inst, next_PC, tid);
540#endif
541 DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n",
542 tid, next_PC, next_NPC);
543 inst->setPredTarg(next_PC, next_NPC);
544 inst->setPredTaken(predict_taken);
545
546 ++fetchedBranches;
547
548 if (predict_taken) {
549 ++predictedBranches;
550 }
551
552 return predict_taken;

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657 }
658
659 ret_fault = fault;
660 return true;
661}
662
663template <class Impl>
664inline void
665DefaultFetch::doSquash(const Addr &new_PC,
666 const Addr &new_NPC, unsigned tid)
667{
668 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
669 tid, new_PC, new_NPC);
670
671 PC[tid] = new_PC;
672 nextPC[tid] = new_NPC;
673 nextNPC[tid] = new_NPC + instSize;
674
675 // Clear the icache miss if it's outstanding.
676 if (fetchStatus[tid] == IcacheWaitResponse) {
677 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
678 tid);
679 memReq[tid] = NULL;
680 }
681

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691
692 fetchStatus[tid] = Squashing;
693
694 ++fetchSquashCycles;
695}
696
697template<class Impl>
698void
699DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
700 const InstSeqNum &seq_num,
701 unsigned tid)
702{
703 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
704
705 doSquash(new_PC, new_NPC, tid);
706
707#if ISA_HAS_DELAY_SLOT
708 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
709 delaySlotInfo[tid].numInsts = 0;
710 delaySlotInfo[tid].targetAddr = 0;
711 delaySlotInfo[tid].targetReady = false;
712 }
713#endif

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780 cpu->deactivateStage(O3CPU::FetchIdx);
781 }
782
783 return Inactive;
784}
785
786template <class Impl>
787void
788DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
789 const InstSeqNum &seq_num,
790 bool squash_delay_slot, unsigned tid)
791{
792 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
793
794 doSquash(new_PC, new_NPC, tid);
795
796#if ISA_HAS_DELAY_SLOT
797 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
798 delaySlotInfo[tid].numInsts = 0;
799 delaySlotInfo[tid].targetAddr = 0;
800 delaySlotInfo[tid].targetReady = false;
801 }
802

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916
917#if ISA_HAS_DELAY_SLOT
918 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
919#else
920 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
921#endif
922 // In any case, squash.
923 squash(fromCommit->commitInfo[tid].nextPC,
924 fromCommit->commitInfo[tid].nextNPC,
925 doneSeqNum,
926 fromCommit->commitInfo[tid].squashDelaySlot,
927 tid);
928
929 // Also check if there's a mispredict that happened.
930 if (fromCommit->commitInfo[tid].branchMispredict) {
931 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
932 fromCommit->commitInfo[tid].nextPC,

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974
975#if ISA_HAS_DELAY_SLOT
976 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
977#else
978 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
979#endif
980 // Squash unless we're already squashing
981 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
982 fromDecode->decodeInfo[tid].nextNPC,
983 doneSeqNum,
984 tid);
985
986 return true;
987 }
988 }
989
990 if (checkStall(tid) &&

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1031 return;
1032 }
1033
1034 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1035
1036 // The current PC.
1037 Addr &fetch_PC = PC[tid];
1038
1039 Addr &fetch_NPC = nextPC[tid];
1040
1041 // Fault code for memory access.
1042 Fault fault = NoFault;
1043
1044 // If returning from the delay of a cache miss, then update the status
1045 // to running, otherwise do the cache access. Possibly move this up
1046 // to tick() function.
1047 if (fetchStatus[tid] == IcacheAccessComplete) {
1048 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",

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1089 // If we had a stall due to an icache miss, then return.
1090 if (fetchStatus[tid] == IcacheWaitResponse) {
1091 ++icacheStallCycles;
1092 status_change = true;
1093 return;
1094 }
1095
1096 Addr next_PC = fetch_PC;
1097 Addr next_NPC = fetch_NPC;
1098
1099 InstSeqNum inst_seq;
1100 MachInst inst;
1101 ExtMachInst ext_inst;
1102 // @todo: Fix this hack.
1103 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1104
1105 if (fault == NoFault) {
1106 // If the read of the first instruction was successful, then grab the

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1137 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1138#elif THE_ISA == SPARC_ISA
1139 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1140#elif THE_ISA == MIPS_ISA
1141 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1142#endif
1143
1144 // Create a new DynInst from the instruction fetched.
1145 DynInstPtr instruction = new DynInst(ext_inst,
1146 fetch_PC, fetch_NPC,
1147 next_PC, next_NPC,
1148 inst_seq, cpu);
1149 instruction->setTid(tid);
1150
1151 instruction->setASID(tid);
1152
1153 instruction->setThreadState(cpu->thread[tid]);
1154
1155 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "

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1237
1238 // Now that fetching is completed, update the PC to signify what the next
1239 // cycle will be.
1240 if (fault == NoFault) {
1241#if ISA_HAS_DELAY_SLOT
1242 if (delaySlotInfo[tid].targetReady &&
1243 delaySlotInfo[tid].numInsts == 0) {
1244 // Set PC to target
1245 PC[tid] = next_PC;
1246 nextPC[tid] = next_NPC;
1247 nextNPC[tid] = next_NPC + instSize;
1248
1249 delaySlotInfo[tid].targetReady = false;
1250 } else {
1251 PC[tid] = next_PC;
1252 nextPC[tid] = next_NPC;
1253 nextNPC[tid] = next_NPC + instSize;
1254 }
1255

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