1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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554}
555
556template <class Impl>
557bool
558DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
559{
560 Fault fault = NoFault;
561
562 //AlphaDep
563 if (cacheBlocked || isSwitchedOut() ||
564 (interruptPending && (fetch_PC & 0x3))) {
565 // Hold off fetch from getting new instructions when:
566 // Cache is blocked, or
567 // while an interrupt is pending and we're not in PAL mode, or
568 // fetch is switched out.
569 return false;
570 }
571
572 // Align the fetch PC so it's at the start of a cache block.
573 fetch_PC = icacheBlockAlignPC(fetch_PC);
574
575 // If we've already got the block, no need to try to fetch it again.
576 if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
577 return true;
578 }
579
580 // Setup the memReq to do a read of the first instruction's address.
581 // Set the appropriate read size and flags as well.
582 // Build request here.
583 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0,
584 fetch_PC, cpu->readCpuId(), tid);
585
586 memReq[tid] = mem_req;
587
588 // Translate the instruction request.
589 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
590
591 // In the case of faults, the fetch stage may need to stall and wait

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