1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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58 panic("DefaultFetch doesn't expect recvAtomic callback!");
59 return curTick;
60}
61
62template<class Impl>
63void
64DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
65{
66 warn("Default fetch doesn't update it's state from a functional call.");
67}
68
69template<class Impl>
70void
71DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
72{
73 if (status == RangeChange)
74 return;
75
76 panic("DefaultFetch doesn't expect recvStatusChange callback!");
77}
78
79template<class Impl>
80bool
81DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
82{
83 if (pkt->isResponse()) {
84 fetch->processCacheCompletion(pkt);
85 }
86 //else Snooped a coherence request, just return
87 return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94 fetch->recvRetry();
95}
96
97template<class Impl>
98DefaultFetch<Impl>::DefaultFetch(Params *params)
99 : branchPred(params),
100 decodeToFetchDelay(params->decodeToFetchDelay),
101 renameToFetchDelay(params->renameToFetchDelay),
102 iewToFetchDelay(params->iewToFetchDelay),
103 commitToFetchDelay(params->commitToFetchDelay),
104 fetchWidth(params->fetchWidth),
105 cacheBlocked(false),
106 retryPkt(NULL),
107 retryTid(-1),

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1112
1113 // Make sure this is a valid index.
1114 assert(offset <= cacheBlkSize - instSize);
1115
1116 // Get the instruction from the array of the cache line.
1117 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1118 (&cacheData[tid][offset]));
1119
1120#if THE_ISA == ALPHA_ISA
1121 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1122#elif THE_ISA == SPARC_ISA
1123 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1124#endif
1125
1126 // Create a new DynInst from the instruction fetched.
1127 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1128 next_PC,
1129 inst_seq, cpu);
1130 instruction->setTid(tid);
1131
1132 instruction->setASID(tid);

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1159
1160 // Increment stat of fetched instructions.
1161 ++fetchedInsts;
1162
1163 // Move to the next instruction, unless we have a branch.
1164 fetch_PC = next_PC;
1165
1166 if (instruction->isQuiesce()) {
1167// warn("%lli: Quiesce instruction encountered, halting fetch!",
1168// curTick);
1169 fetchStatus[tid] = QuiescePending;
1170 ++numInst;
1171 status_change = true;
1172 break;
1173 }
1174
1175 offset += instSize;
1176

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1274
1275 toDecode->insts[numInst] = instruction;
1276 toDecode->size++;
1277
1278 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1279
1280 fetchStatus[tid] = TrapPending;
1281 status_change = true;
1282
1283// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1284#else // !FULL_SYSTEM
1285 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1286#endif // FULL_SYSTEM
1287 }
1288}
1289
1290template<class Impl>
1291void
1292DefaultFetch<Impl>::recvRetry()
1293{
1294 if (retryPkt != NULL) {

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