fetch.hh (9814:7ad2b0186a32) fetch.hh (9982:b2bfc23f932c)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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269 * expected to be set to the current PC; it will be updated with what
270 * the next PC will be.
271 * @param next_NPC Used for ISAs which use delay slots.
272 * @return Whether or not a branch was predicted as taken.
273 */
274 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
275
276 /**
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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269 * expected to be set to the current PC; it will be updated with what
270 * the next PC will be.
271 * @param next_NPC Used for ISAs which use delay slots.
272 * @return Whether or not a branch was predicted as taken.
273 */
274 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
275
276 /**
277 * Fetches the cache line that contains fetch_PC. Returns any
277 * Fetches the cache line that contains the fetch PC. Returns any
278 * fault that happened. Puts the data into the class variable
278 * fault that happened. Puts the data into the class variable
279 * cacheData.
279 * fetchBuffer, which may not hold the entire fetched cache line.
280 * @param vaddr The memory address that is being fetched from.
281 * @param ret_fault The fault reference that will be set to the result of
282 * the icache access.
283 * @param tid Thread id.
284 * @param pc The actual PC of the current instruction.
285 * @return Any fault that occured.
286 */
287 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);

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334
335 /** Does the actual fetching of instructions and passing them on to the
336 * next stage.
337 * @param status_change fetch() sets this variable if there was a status
338 * change (ie switching to IcacheMissStall).
339 */
340 void fetch(bool &status_change);
341
280 * @param vaddr The memory address that is being fetched from.
281 * @param ret_fault The fault reference that will be set to the result of
282 * the icache access.
283 * @param tid Thread id.
284 * @param pc The actual PC of the current instruction.
285 * @return Any fault that occured.
286 */
287 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);

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334
335 /** Does the actual fetching of instructions and passing them on to the
336 * next stage.
337 * @param status_change fetch() sets this variable if there was a status
338 * change (ie switching to IcacheMissStall).
339 */
340 void fetch(bool &status_change);
341
342 /** Align a PC to the start of an I-cache block. */
343 Addr icacheBlockAlignPC(Addr addr)
342 /** Align a PC to the start of a fetch buffer block. */
343 Addr fetchBufferAlignPC(Addr addr)
344 {
344 {
345 return (addr & ~(cacheBlkMask));
345 return (addr & ~(fetchBufferMask));
346 }
347
348 /** The decoder. */
349 TheISA::Decoder *decoder[Impl::MaxThreads];
350
351 private:
352 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
353 StaticInstPtr curMacroop, TheISA::PCState thisPC,

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458 PacketPtr retryPkt;
459
460 /** The thread that is waiting on the cache to tell fetch to retry. */
461 ThreadID retryTid;
462
463 /** Cache block size. */
464 unsigned int cacheBlkSize;
465
346 }
347
348 /** The decoder. */
349 TheISA::Decoder *decoder[Impl::MaxThreads];
350
351 private:
352 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
353 StaticInstPtr curMacroop, TheISA::PCState thisPC,

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458 PacketPtr retryPkt;
459
460 /** The thread that is waiting on the cache to tell fetch to retry. */
461 ThreadID retryTid;
462
463 /** Cache block size. */
464 unsigned int cacheBlkSize;
465
466 /** Mask to get a cache block's address. */
467 Addr cacheBlkMask;
466 /** The size of the fetch buffer in bytes. The fetch buffer
467 * itself may be smaller than a cache line.
468 */
469 unsigned fetchBufferSize;
468
470
469 /** The cache line being fetched. */
470 uint8_t *cacheData[Impl::MaxThreads];
471 /** Mask to align a fetch address to a fetch buffer boundary. */
472 Addr fetchBufferMask;
471
473
472 /** The PC of the cacheline that has been loaded. */
473 Addr cacheDataPC[Impl::MaxThreads];
474 /** The fetch data that is being fetched and buffered. */
475 uint8_t *fetchBuffer[Impl::MaxThreads];
474
476
475 /** Whether or not the cache data is valid. */
476 bool cacheDataValid[Impl::MaxThreads];
477 /** The PC of the first instruction loaded into the fetch buffer. */
478 Addr fetchBufferPC[Impl::MaxThreads];
477
479
480 /** Whether or not the fetch buffer data is valid. */
481 bool fetchBufferValid[Impl::MaxThreads];
482
478 /** Size of instructions. */
479 int instSize;
480
481 /** Icache stall statistics. */
482 Counter lastIcacheStall[Impl::MaxThreads];
483
484 /** List of Active Threads */
485 std::list<ThreadID> *activeThreads;

--- 75 unchanged lines hidden --- 		483 /** Size of instructions. */
484 int instSize;
485
486 /** Icache stall statistics. */
487 Counter lastIcacheStall[Impl::MaxThreads];
488
489 /** List of Active Threads */
490 std::list<ThreadID> *activeThreads;

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