fetch.hh (9444:ab47fe7f03f0) fetch.hh (9480:d059f8a95a42)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/decoder.hh"
48#include "arch/utility.hh"
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/pc_event.hh"
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/decoder.hh"
48#include "arch/utility.hh"
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/pc_event.hh"
52#include "cpu/pred/bpred_unit.hh"
52#include "cpu/timebuf.hh"
53#include "cpu/translation.hh"
54#include "mem/packet.hh"
55#include "mem/port.hh"
56#include "sim/eventq.hh"
57
58struct DerivO3CPUParams;
59

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71 public:
72 /** Typedefs from Impl. */
73 typedef typename Impl::CPUPol CPUPol;
74 typedef typename Impl::DynInst DynInst;
75 typedef typename Impl::DynInstPtr DynInstPtr;
76 typedef typename Impl::O3CPU O3CPU;
77
78 /** Typedefs from the CPU policy. */
53#include "cpu/timebuf.hh"
54#include "cpu/translation.hh"
55#include "mem/packet.hh"
56#include "mem/port.hh"
57#include "sim/eventq.hh"
58
59struct DerivO3CPUParams;
60

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72 public:
73 /** Typedefs from Impl. */
74 typedef typename Impl::CPUPol CPUPol;
75 typedef typename Impl::DynInst DynInst;
76 typedef typename Impl::DynInstPtr DynInstPtr;
77 typedef typename Impl::O3CPU O3CPU;
78
79 /** Typedefs from the CPU policy. */
79 typedef typename CPUPol::BPredUnit BPredUnit;
80 typedef typename CPUPol::FetchStruct FetchStruct;
81 typedef typename CPUPol::TimeStruct TimeStruct;
82
83 /** Typedefs from ISA. */
84 typedef TheISA::MachInst MachInst;
85 typedef TheISA::ExtMachInst ExtMachInst;
86
87 class FetchTranslation : public BaseTLB::Translation

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400 /** Internal fetch instruction queue. */
401 TimeBuffer<FetchStruct> *fetchQueue;
402
403 //Might be annoying how this name is different than the queue.
404 /** Wire used to write any information heading to decode. */
405 typename TimeBuffer<FetchStruct>::wire toDecode;
406
407 /** BPredUnit. */
80 typedef typename CPUPol::FetchStruct FetchStruct;
81 typedef typename CPUPol::TimeStruct TimeStruct;
82
83 /** Typedefs from ISA. */
84 typedef TheISA::MachInst MachInst;
85 typedef TheISA::ExtMachInst ExtMachInst;
86
87 class FetchTranslation : public BaseTLB::Translation

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400 /** Internal fetch instruction queue. */
401 TimeBuffer<FetchStruct> *fetchQueue;
402
403 //Might be annoying how this name is different than the queue.
404 /** Wire used to write any information heading to decode. */
405 typename TimeBuffer<FetchStruct>::wire toDecode;
406
407 /** BPredUnit. */
408 BPredUnit branchPred;
408 BPredUnit *branchPred;
409
410 TheISA::PCState pc[Impl::MaxThreads];
411
412 Addr fetchOffset[Impl::MaxThreads];
413
414 StaticInstPtr macroop[Impl::MaxThreads];
415
416 /** Can the fetch stage redirect from an interrupt on this instruction? */

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410 TheISA::PCState pc[Impl::MaxThreads];
411
412 Addr fetchOffset[Impl::MaxThreads];
413
414 StaticInstPtr macroop[Impl::MaxThreads];
415
416 /** Can the fetch stage redirect from an interrupt on this instruction? */

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