fetch.hh (9427:ddf45c1d54d4) fetch.hh (9444:ab47fe7f03f0)
1/*
1/*
2 * Copyright (c) 2010-2011 ARM Limited
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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160 enum ThreadStatus {
161 Running,
162 Idle,
163 Squashing,
164 Blocked,
165 Fetching,
166 TrapPending,
167 QuiescePending,
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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160 enum ThreadStatus {
161 Running,
162 Idle,
163 Squashing,
164 Blocked,
165 Fetching,
166 TrapPending,
167 QuiescePending,
168 SwitchOut,
169 ItlbWait,
170 IcacheWaitResponse,
171 IcacheWaitRetry,
172 IcacheAccessComplete,
173 NoGoodAddr
174 };
175
176 /** Fetching Policy, Add new policies here.*/

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221 void setIcache();
222
223 /** Handles retrying the fetch access. */
224 void recvRetry();
225
226 /** Processes cache completion event. */
227 void processCacheCompletion(PacketPtr pkt);
228
168 ItlbWait,
169 IcacheWaitResponse,
170 IcacheWaitRetry,
171 IcacheAccessComplete,
172 NoGoodAddr
173 };
174
175 /** Fetching Policy, Add new policies here.*/

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220 void setIcache();
221
222 /** Handles retrying the fetch access. */
223 void recvRetry();
224
225 /** Processes cache completion event. */
226 void processCacheCompletion(PacketPtr pkt);
227
229 /** Begins the drain of the fetch stage. */
230 bool drain();
228 /** Resume after a drain. */
229 void drainResume();
231
230
232 /** Resumes execution after a drain. */
233 void resume();
231 /** Perform sanity checks after a drain. */
232 void drainSanityCheck() const;
234
233
235 /** Tells fetch stage to prepare to be switched out. */
236 void switchOut();
234 /** Has the stage drained? */
235 bool isDrained() const;
237
238 /** Takes over from another CPU's thread. */
239 void takeOverFrom();
240
236
237 /** Takes over from another CPU's thread. */
238 void takeOverFrom();
239
241 /** Checks if the fetch stage is switched out. */
242 bool isSwitchedOut() { return switchedOut; }
240 /**
241 * Stall the fetch stage after reaching a safe drain point.
242 *
243 * The CPU uses this method to stop fetching instructions from a
244 * thread that has been drained. The drain stall is different from
245 * all other stalls in that it is signaled instantly from the
246 * commit stage (without the normal communication delay) when it
247 * has reached a safe point to drain from.
248 */
249 void drainStall(ThreadID tid);
243
244 /** Tells fetch to wake up from a quiesce instruction. */
245 void wakeFromQuiesce();
246
247 private:
250
251 /** Tells fetch to wake up from a quiesce instruction. */
252 void wakeFromQuiesce();
253
254 private:
255 /** Reset this pipeline stage */
256 void resetStage();
257
248 /** Changes the status of this stage to active, and indicates this
249 * to the CPU.
250 */
251 inline void switchToActive();
252
253 /** Changes the status of this stage to inactive, and indicates
254 * this to the CPU.
255 */

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418 int numInst;
419
420 /** Source of possible stalls. */
421 struct Stalls {
422 bool decode;
423 bool rename;
424 bool iew;
425 bool commit;
258 /** Changes the status of this stage to active, and indicates this
259 * to the CPU.
260 */
261 inline void switchToActive();
262
263 /** Changes the status of this stage to inactive, and indicates
264 * this to the CPU.
265 */

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428 int numInst;
429
430 /** Source of possible stalls. */
431 struct Stalls {
432 bool decode;
433 bool rename;
434 bool iew;
435 bool commit;
436 bool drain;
426 };
427
428 /** Tracks which stages are telling fetch to stall. */
429 Stalls stalls[Impl::MaxThreads];
430
431 /** Decode to fetch delay. */
432 Cycles decodeToFetchDelay;
433

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485 /** Thread ID being fetched. */
486 ThreadID threadFetched;
487
488 /** Checks if there is an interrupt pending. If there is, fetch
489 * must stop once it is not fetching PAL instructions.
490 */
491 bool interruptPending;
492
437 };
438
439 /** Tracks which stages are telling fetch to stall. */
440 Stalls stalls[Impl::MaxThreads];
441
442 /** Decode to fetch delay. */
443 Cycles decodeToFetchDelay;
444

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496 /** Thread ID being fetched. */
497 ThreadID threadFetched;
498
499 /** Checks if there is an interrupt pending. If there is, fetch
500 * must stop once it is not fetching PAL instructions.
501 */
502 bool interruptPending;
503
493 /** Is there a drain pending. */
494 bool drainPending;
495
496 /** Records if fetch is switched out. */
497 bool switchedOut;
498
499 /** Set to true if a pipelined I-cache request should be issued. */
500 bool issuePipelinedIfetch[Impl::MaxThreads];
501
502 /** Event used to delay fault generation of translation faults */
503 FinishTranslationEvent finishTranslationEvent;
504
505 // @todo: Consider making these vectors and tracking on a per thread basis.
506 /** Stat for total number of cycles stalled due to an icache miss. */

--- 52 unchanged lines hidden --- 		504 /** Set to true if a pipelined I-cache request should be issued. */
505 bool issuePipelinedIfetch[Impl::MaxThreads];
506
507 /** Event used to delay fault generation of translation faults */
508 FinishTranslationEvent finishTranslationEvent;
509
510 // @todo: Consider making these vectors and tracking on a per thread basis.
511 /** Stat for total number of cycles stalled due to an icache miss. */

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