| fetch.hh (9023:e9201a7bce59) | fetch.hh (9184:a1a8f137b796) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 414 unchanged lines hidden (view full) --- 423 bool rename; 424 bool iew; 425 bool commit; 426 }; 427 428 /** Tracks which stages are telling fetch to stall. */ 429 Stalls stalls[Impl::MaxThreads]; 430 | 1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 414 unchanged lines hidden (view full) --- 423 bool rename; 424 bool iew; 425 bool commit; 426 }; 427 428 /** Tracks which stages are telling fetch to stall. */ 429 Stalls stalls[Impl::MaxThreads]; 430 |
| 431 /** Decode to fetch delay, in ticks. */ 432 unsigned decodeToFetchDelay; | 431 /** Decode to fetch delay. */ 432 Cycles decodeToFetchDelay; |
| 433 | 433 |
| 434 /** Rename to fetch delay, in ticks. */ 435 unsigned renameToFetchDelay; | 434 /** Rename to fetch delay. */ 435 Cycles renameToFetchDelay; |
| 436 | 436 |
| 437 /** IEW to fetch delay, in ticks. */ 438 unsigned iewToFetchDelay; | 437 /** IEW to fetch delay. */ 438 Cycles iewToFetchDelay; |
| 439 | 439 |
| 440 /** Commit to fetch delay, in ticks. */ 441 unsigned commitToFetchDelay; | 440 /** Commit to fetch delay. */ 441 Cycles commitToFetchDelay; |
| 442 443 /** The width of fetch in instructions. */ 444 unsigned fetchWidth; 445 446 /** Is the cache blocked? If so no threads can access it. */ 447 bool cacheBlocked; 448 449 /** The packet that is waiting to be retried. */ --- 109 unchanged lines hidden --- | 442 443 /** The width of fetch in instructions. */ 444 unsigned fetchWidth; 445 446 /** Is the cache blocked? If so no threads can access it. */ 447 bool cacheBlocked; 448 449 /** The packet that is waiting to be retried. */ --- 109 unchanged lines hidden --- |