fetch.hh (9020:14321ce30881) fetch.hh (9023:e9201a7bce59)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/decoder.hh"
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/decoder.hh"
48#include "arch/predecoder.hh"
49#include "arch/utility.hh"
50#include "base/statistics.hh"
51#include "config/the_isa.hh"
52#include "cpu/pc_event.hh"
53#include "cpu/timebuf.hh"
54#include "cpu/translation.hh"
55#include "mem/packet.hh"
56#include "mem/port.hh"

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335
336 /** Align a PC to the start of an I-cache block. */
337 Addr icacheBlockAlignPC(Addr addr)
338 {
339 return (addr & ~(cacheBlkMask));
340 }
341
342 /** The decoder. */
48#include "arch/utility.hh"
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/pc_event.hh"
52#include "cpu/timebuf.hh"
53#include "cpu/translation.hh"
54#include "mem/packet.hh"
55#include "mem/port.hh"

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334
335 /** Align a PC to the start of an I-cache block. */
336 Addr icacheBlockAlignPC(Addr addr)
337 {
338 return (addr & ~(cacheBlkMask));
339 }
340
341 /** The decoder. */
343 TheISA::Decoder decoder;
342 TheISA::Decoder *decoder[Impl::MaxThreads];
344
345 private:
346 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
347 StaticInstPtr curMacroop, TheISA::PCState thisPC,
348 TheISA::PCState nextPC, bool trace);
349
350 /** Returns the appropriate thread to fetch, given the fetch policy. */
351 ThreadID getFetchingThread(FetchPriority &fetch_priority);

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393
394 //Might be annoying how this name is different than the queue.
395 /** Wire used to write any information heading to decode. */
396 typename TimeBuffer<FetchStruct>::wire toDecode;
397
398 /** BPredUnit. */
399 BPredUnit branchPred;
400
343
344 private:
345 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
346 StaticInstPtr curMacroop, TheISA::PCState thisPC,
347 TheISA::PCState nextPC, bool trace);
348
349 /** Returns the appropriate thread to fetch, given the fetch policy. */
350 ThreadID getFetchingThread(FetchPriority &fetch_priority);

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392
393 //Might be annoying how this name is different than the queue.
394 /** Wire used to write any information heading to decode. */
395 typename TimeBuffer<FetchStruct>::wire toDecode;
396
397 /** BPredUnit. */
398 BPredUnit branchPred;
399
401 /** Predecoder. */
402 TheISA::Predecoder predecoder;
403
404 TheISA::PCState pc[Impl::MaxThreads];
405
406 Addr fetchOffset[Impl::MaxThreads];
407
408 StaticInstPtr macroop[Impl::MaxThreads];
409
410 /** Can the fetch stage redirect from an interrupt on this instruction? */
411 bool delayedCommit[Impl::MaxThreads];

--- 151 unchanged lines hidden --- 		400 TheISA::PCState pc[Impl::MaxThreads];
401
402 Addr fetchOffset[Impl::MaxThreads];
403
404 StaticInstPtr macroop[Impl::MaxThreads];
405
406 /** Can the fetch stage redirect from an interrupt on this instruction? */
407 bool delayedCommit[Impl::MaxThreads];

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