fetch.hh (8541:27aaee8ec7cc) fetch.hh (8707:489489c67fd9)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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80 typedef typename CPUPol::BPredUnit BPredUnit;
81 typedef typename CPUPol::FetchStruct FetchStruct;
82 typedef typename CPUPol::TimeStruct TimeStruct;
83
84 /** Typedefs from ISA. */
85 typedef TheISA::MachInst MachInst;
86 typedef TheISA::ExtMachInst ExtMachInst;
87
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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80 typedef typename CPUPol::BPredUnit BPredUnit;
81 typedef typename CPUPol::FetchStruct FetchStruct;
82 typedef typename CPUPol::TimeStruct TimeStruct;
83
84 /** Typedefs from ISA. */
85 typedef TheISA::MachInst MachInst;
86 typedef TheISA::ExtMachInst ExtMachInst;
87
88 /** IcachePort class for DefaultFetch. Handles doing the
89 * communication with the cache/memory.
90 */
91 class IcachePort : public Port
92 {
93 protected:
94 /** Pointer to fetch. */
95 DefaultFetch<Impl> *fetch;
96
97 public:
98 /** Default constructor. */
99 IcachePort(DefaultFetch<Impl> *_fetch)
100 : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch)
101 { }
102
103 bool snoopRangeSent;
104
105 virtual void setPeer(Port *port);
106
107 protected:
108 /** Atomic version of receive. Panics. */
109 virtual Tick recvAtomic(PacketPtr pkt);
110
111 /** Functional version of receive. Panics. */
112 virtual void recvFunctional(PacketPtr pkt);
113
114 /** Receives status change. Other than range changing, panics. */
115 virtual void recvStatusChange(Status status);
116
117 /** Returns the address ranges of this device. */
118 virtual void getDeviceAddressRanges(AddrRangeList &resp,
119 bool &snoop)
120 { resp.clear(); snoop = true; }
121
122 /** Timing version of receive. Handles setting fetch to the
123 * proper status to start fetching. */
124 virtual bool recvTiming(PacketPtr pkt);
125
126 /** Handles doing a retry of a failed fetch. */
127 virtual void recvRetry();
128 };
129
130 class FetchTranslation : public BaseTLB::Translation
131 {
132 protected:
133 DefaultFetch<Impl> *fetch;
134
135 public:
136 FetchTranslation(DefaultFetch<Impl> *_fetch)
137 : fetch(_fetch)

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243 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
244
245 /** Returns the name of fetch. */
246 std::string name() const;
247
248 /** Registers statistics. */
249 void regStats();
250
88 class FetchTranslation : public BaseTLB::Translation
89 {
90 protected:
91 DefaultFetch<Impl> *fetch;
92
93 public:
94 FetchTranslation(DefaultFetch<Impl> *_fetch)
95 : fetch(_fetch)

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201 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
202
203 /** Returns the name of fetch. */
204 std::string name() const;
205
206 /** Registers statistics. */
207 void regStats();
208
251 /** Returns the icache port. */
252 Port *getIcachePort() { return icachePort; }
253
254 /** Sets the main backwards communication time buffer pointer. */
255 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
256
257 /** Sets pointer to list of active threads. */
258 void setActiveThreads(std::list<ThreadID> *at_ptr);
259
260 /** Sets pointer to time buffer used to communicate to the next stage. */
261 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
262
263 /** Initialize stage. */
264 void initStage();
265
266 /** Tells the fetch stage that the Icache is set. */
267 void setIcache();
268
209 /** Sets the main backwards communication time buffer pointer. */
210 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
211
212 /** Sets pointer to list of active threads. */
213 void setActiveThreads(std::list<ThreadID> *at_ptr);
214
215 /** Sets pointer to time buffer used to communicate to the next stage. */
216 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
217
218 /** Initialize stage. */
219 void initStage();
220
221 /** Tells the fetch stage that the Icache is set. */
222 void setIcache();
223
224 /** Handles retrying the fetch access. */
225 void recvRetry();
226
269 /** Processes cache completion event. */
270 void processCacheCompletion(PacketPtr pkt);
271
272 /** Begins the drain of the fetch stage. */
273 bool drain();
274
275 /** Resumes execution after a drain. */
276 void resume();

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384 /** The decoder. */
385 Decoder decoder;
386
387 private:
388 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
389 StaticInstPtr curMacroop, TheISA::PCState thisPC,
390 TheISA::PCState nextPC, bool trace);
391
227 /** Processes cache completion event. */
228 void processCacheCompletion(PacketPtr pkt);
229
230 /** Begins the drain of the fetch stage. */
231 bool drain();
232
233 /** Resumes execution after a drain. */
234 void resume();

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342 /** The decoder. */
343 Decoder decoder;
344
345 private:
346 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
347 StaticInstPtr curMacroop, TheISA::PCState thisPC,
348 TheISA::PCState nextPC, bool trace);
349
392 /** Handles retrying the fetch access. */
393 void recvRetry();
394
395 /** Returns the appropriate thread to fetch, given the fetch policy. */
396 ThreadID getFetchingThread(FetchPriority &fetch_priority);
397
398 /** Returns the appropriate thread to fetch using a round robin policy. */
399 ThreadID roundRobin();
400
401 /** Returns the appropriate thread to fetch using the IQ count policy. */
402 ThreadID iqCount();

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435
436 /** Internal fetch instruction queue. */
437 TimeBuffer<FetchStruct> *fetchQueue;
438
439 //Might be annoying how this name is different than the queue.
440 /** Wire used to write any information heading to decode. */
441 typename TimeBuffer<FetchStruct>::wire toDecode;
442
350 /** Returns the appropriate thread to fetch, given the fetch policy. */
351 ThreadID getFetchingThread(FetchPriority &fetch_priority);
352
353 /** Returns the appropriate thread to fetch using a round robin policy. */
354 ThreadID roundRobin();
355
356 /** Returns the appropriate thread to fetch using the IQ count policy. */
357 ThreadID iqCount();

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390
391 /** Internal fetch instruction queue. */
392 TimeBuffer<FetchStruct> *fetchQueue;
393
394 //Might be annoying how this name is different than the queue.
395 /** Wire used to write any information heading to decode. */
396 typename TimeBuffer<FetchStruct>::wire toDecode;
397
443 /** Icache interface. */
444 IcachePort *icachePort;
445
446 /** BPredUnit. */
447 BPredUnit branchPred;
448
449 /** Predecoder. */
450 TheISA::Predecoder predecoder;
451
452 TheISA::PCState pc[Impl::MaxThreads];
453

--- 157 unchanged lines hidden --- 		398 /** BPredUnit. */
399 BPredUnit branchPred;
400
401 /** Predecoder. */
402 TheISA::Predecoder predecoder;
403
404 TheISA::PCState pc[Impl::MaxThreads];
405

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