fetch.hh (8460:3893d9d2c6c2) fetch.hh (8462:80492ae5148e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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145 BaseTLB::Mode mode)
146 {
147 assert(mode == BaseTLB::Execute);
148 fetch->finishTranslation(fault, req);
149 delete this;
150 }
151 };
152
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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145 BaseTLB::Mode mode)
146 {
147 assert(mode == BaseTLB::Execute);
148 fetch->finishTranslation(fault, req);
149 delete this;
150 }
151 };
152
153 private:
154 /* Event to delay delivery of a fetch translation result in case of
155 * a fault and the nop to carry the fault cannot be generated
156 * immediately */
157 class FinishTranslationEvent : public Event
158 {
159 private:
160 DefaultFetch<Impl> *fetch;
161 Fault fault;
162 RequestPtr req;
163
164 public:
165 FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
166 : fetch(_fetch)
167 {}
168
169 void setFault(Fault _fault)
170 {
171 fault = _fault;
172 }
173
174 void setReq(RequestPtr _req)
175 {
176 req = _req;
177 }
178
179 /** Process the delayed finish translation */
180 void process()
181 {
182 assert(fetch->numInst < fetch->fetchWidth);
183 fetch->finishTranslation(fault, req);
184 }
185
186 const char *description() const
187 {
188 return "FullO3CPU FetchFinishTranslation";
189 }
190 };
191
153 public:
154 /** Overall fetch status. Used to determine if the CPU can
155 * deschedule itsef due to a lack of activity.
156 */
157 enum FetchStatus {
158 Active,
159 Inactive
160 };

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358
359 /** Returns the appropriate thread to fetch using the LSQ count policy. */
360 ThreadID lsqCount();
361
362 /** Returns the appropriate thread to fetch using the branch count
363 * policy. */
364 ThreadID branchCount();
365
192 public:
193 /** Overall fetch status. Used to determine if the CPU can
194 * deschedule itsef due to a lack of activity.
195 */
196 enum FetchStatus {
197 Active,
198 Inactive
199 };

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397
398 /** Returns the appropriate thread to fetch using the LSQ count policy. */
399 ThreadID lsqCount();
400
401 /** Returns the appropriate thread to fetch using the branch count
402 * policy. */
403 ThreadID branchCount();
404
405 /** Pipeline the next I-cache access to the current one. */
406 void pipelineIcacheAccesses(ThreadID tid);
407
408 /** Profile the reasons of fetch stall. */
409 void profileStall(ThreadID tid);
410
366 private:
367 /** Pointer to the O3CPU. */
368 O3CPU *cpu;
369
370 /** Time buffer interface. */
371 TimeBuffer<TimeStruct> *timeBuffer;
372
373 /** Wire to get decode's information from backwards time buffer. */

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492 bool interruptPending;
493
494 /** Is there a drain pending. */
495 bool drainPending;
496
497 /** Records if fetch is switched out. */
498 bool switchedOut;
499
411 private:
412 /** Pointer to the O3CPU. */
413 O3CPU *cpu;
414
415 /** Time buffer interface. */
416 TimeBuffer<TimeStruct> *timeBuffer;
417
418 /** Wire to get decode's information from backwards time buffer. */

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537 bool interruptPending;
538
539 /** Is there a drain pending. */
540 bool drainPending;
541
542 /** Records if fetch is switched out. */
543 bool switchedOut;
544
545 /** Set to true if a pipelined I-cache request should be issued. */
546 bool issuePipelinedIfetch[Impl::MaxThreads];
547
548 /** Event used to delay fault generation of translation faults */
549 FinishTranslationEvent finishTranslationEvent;
550
500 // @todo: Consider making these vectors and tracking on a per thread basis.
501 /** Stat for total number of cycles stalled due to an icache miss. */
502 Stats::Scalar icacheStallCycles;
503 /** Stat for total number of fetched instructions. */
504 Stats::Scalar fetchedInsts;
505 /** Total number of fetched branches. */
506 Stats::Scalar fetchedBranches;
507 /** Stat for total number of predicted branches. */

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515 /** Stat for total number of cycles spent blocked due to other stages in
516 * the pipeline.
517 */
518 Stats::Scalar fetchIdleCycles;
519 /** Total number of cycles spent blocked. */
520 Stats::Scalar fetchBlockedCycles;
521 /** Total number of cycles spent in any other state. */
522 Stats::Scalar fetchMiscStallCycles;
551 // @todo: Consider making these vectors and tracking on a per thread basis.
552 /** Stat for total number of cycles stalled due to an icache miss. */
553 Stats::Scalar icacheStallCycles;
554 /** Stat for total number of fetched instructions. */
555 Stats::Scalar fetchedInsts;
556 /** Total number of fetched branches. */
557 Stats::Scalar fetchedBranches;
558 /** Stat for total number of predicted branches. */

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566 /** Stat for total number of cycles spent blocked due to other stages in
567 * the pipeline.
568 */
569 Stats::Scalar fetchIdleCycles;
570 /** Total number of cycles spent blocked. */
571 Stats::Scalar fetchBlockedCycles;
572 /** Total number of cycles spent in any other state. */
573 Stats::Scalar fetchMiscStallCycles;
574 /** Total number of cycles spent in waiting for drains. */
575 Stats::Scalar fetchPendingDrainCycles;
576 /** Total number of stall cycles caused by no active threads to run. */
577 Stats::Scalar fetchNoActiveThreadStallCycles;
578 /** Total number of stall cycles caused by pending traps. */
579 Stats::Scalar fetchPendingTrapStallCycles;
580 /** Total number of stall cycles caused by pending quiesce instructions. */
581 Stats::Scalar fetchPendingQuiesceStallCycles;
582 /** Total number of stall cycles caused by I-cache wait retrys. */
583 Stats::Scalar fetchIcacheWaitRetryStallCycles;
523 /** Stat for total number of fetched cache lines. */
524 Stats::Scalar fetchedCacheLines;
525 /** Total number of outstanding icache accesses that were dropped
526 * due to a squash.
527 */
528 Stats::Scalar fetchIcacheSquashes;
529 /** Total number of outstanding tlb accesses that were dropped
530 * due to a squash.

--- 13 unchanged lines hidden --- 		584 /** Stat for total number of fetched cache lines. */
585 Stats::Scalar fetchedCacheLines;
586 /** Total number of outstanding icache accesses that were dropped
587 * due to a squash.
588 */
589 Stats::Scalar fetchIcacheSquashes;
590 /** Total number of outstanding tlb accesses that were dropped
591 * due to a squash.

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