fetch.hh (8229:78bf55f23338) fetch.hh (8314:13ac7b9939ef)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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398 TheISA::Predecoder predecoder;
399
400 TheISA::PCState pc[Impl::MaxThreads];
401
402 Addr fetchOffset[Impl::MaxThreads];
403
404 StaticInstPtr macroop[Impl::MaxThreads];
405
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 389 unchanged lines hidden (view full) ---

398 TheISA::Predecoder predecoder;
399
400 TheISA::PCState pc[Impl::MaxThreads];
401
402 Addr fetchOffset[Impl::MaxThreads];
403
404 StaticInstPtr macroop[Impl::MaxThreads];
405
406 /** Can the fetch stage redirect from an interrupt on this instruction? */
407 bool delayedCommit[Impl::MaxThreads];
408
406 /** Memory request used to access cache. */
407 RequestPtr memReq[Impl::MaxThreads];
408
409 /** Variable that tracks if fetch has written to the time buffer this
410 * cycle. Used to tell CPU if there is activity this cycle.
411 */
412 bool wroteToTimeBuffer;
413

--- 126 unchanged lines hidden --- 		409 /** Memory request used to access cache. */
410 RequestPtr memReq[Impl::MaxThreads];
411
412 /** Variable that tracks if fetch has written to the time buffer this
413 * cycle. Used to tell CPU if there is activity this cycle.
414 */
415 bool wroteToTimeBuffer;
416

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