fetch.hh (7720:65d338a8dba4) fetch.hh (7764:03efcdc3421f)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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230 * @return Whether or not a branch was predicted as taken.
231 */
232 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
233
234 /**
235 * Fetches the cache line that contains fetch_PC. Returns any
236 * fault that happened. Puts the data into the class variable
237 * cacheData.
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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230 * @return Whether or not a branch was predicted as taken.
231 */
232 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
233
234 /**
235 * Fetches the cache line that contains fetch_PC. Returns any
236 * fault that happened. Puts the data into the class variable
237 * cacheData.
238 * @param fetch_PC The PC address that is being fetched from.
238 * @param vaddr The memory address that is being fetched from.
239 * @param ret_fault The fault reference that will be set to the result of
240 * the icache access.
241 * @param tid Thread id.
239 * @param ret_fault The fault reference that will be set to the result of
240 * the icache access.
241 * @param tid Thread id.
242 * @param pc The actual PC of the current instruction.
242 * @return Any fault that occured.
243 */
243 * @return Any fault that occured.
244 */
244 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid);
245 bool fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid, Addr pc);
245
246 /** Squashes a specific thread and resets the PC. */
247 inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
248
249 /** Squashes a specific thread and resets the PC. Also tells the CPU to
250 * remove any instructions between fetch and decode that should be sqaushed.
251 */
252 void squashFromDecode(const TheISA::PCState &newPC,

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286
287 /** Align a PC to the start of an I-cache block. */
288 Addr icacheBlockAlignPC(Addr addr)
289 {
290 return (addr & ~(cacheBlkMask));
291 }
292
293 private:
246
247 /** Squashes a specific thread and resets the PC. */
248 inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
249
250 /** Squashes a specific thread and resets the PC. Also tells the CPU to
251 * remove any instructions between fetch and decode that should be sqaushed.
252 */
253 void squashFromDecode(const TheISA::PCState &newPC,

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287
288 /** Align a PC to the start of an I-cache block. */
289 Addr icacheBlockAlignPC(Addr addr)
290 {
291 return (addr & ~(cacheBlkMask));
292 }
293
294 private:
295 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
296 StaticInstPtr curMacroop, TheISA::PCState thisPC,
297 TheISA::PCState nextPC, bool trace);
298
294 /** Handles retrying the fetch access. */
295 void recvRetry();
296
297 /** Returns the appropriate thread to fetch, given the fetch policy. */
298 ThreadID getFetchingThread(FetchPriority &fetch_priority);
299
300 /** Returns the appropriate thread to fetch using a round robin policy. */
301 ThreadID roundRobin();

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342 /** BPredUnit. */
343 BPredUnit branchPred;
344
345 /** Predecoder. */
346 TheISA::Predecoder predecoder;
347
348 TheISA::PCState pc[Impl::MaxThreads];
349
299 /** Handles retrying the fetch access. */
300 void recvRetry();
301
302 /** Returns the appropriate thread to fetch, given the fetch policy. */
303 ThreadID getFetchingThread(FetchPriority &fetch_priority);
304
305 /** Returns the appropriate thread to fetch using a round robin policy. */
306 ThreadID roundRobin();

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347 /** BPredUnit. */
348 BPredUnit branchPred;
349
350 /** Predecoder. */
351 TheISA::Predecoder predecoder;
352
353 TheISA::PCState pc[Impl::MaxThreads];
354
355 Addr fetchOffset[Impl::MaxThreads];
356
357 StaticInstPtr macroop[Impl::MaxThreads];
358
350 /** Memory request used to access cache. */
351 RequestPtr memReq[Impl::MaxThreads];
352
353 /** Variable that tracks if fetch has written to the time buffer this
354 * cycle. Used to tell CPU if there is activity this cycle.
355 */
356 bool wroteToTimeBuffer;
357

--- 120 unchanged lines hidden --- 		359 /** Memory request used to access cache. */
360 RequestPtr memReq[Impl::MaxThreads];
361
362 /** Variable that tracks if fetch has written to the time buffer this
363 * cycle. Used to tell CPU if there is activity this cycle.
364 */
365 bool wroteToTimeBuffer;
366

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