fetch.hh (5494:85c8d296c1cb) fetch.hh (5529:9ae69b9cd7fd)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "base/timebuf.hh"
39#include "cpu/pc_event.hh"
40#include "mem/packet.hh"
41#include "mem/port.hh"
42#include "sim/eventq.hh"
43
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "base/timebuf.hh"
39#include "cpu/pc_event.hh"
40#include "mem/packet.hh"
41#include "mem/port.hh"
42#include "sim/eventq.hh"
43
44class DerivO3CPUParams;
45
44/**
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
51 */
52template <class Impl>
53class DefaultFetch
54{
55 public:
56 /** Typedefs from Impl. */
57 typedef typename Impl::CPUPol CPUPol;
58 typedef typename Impl::DynInst DynInst;
59 typedef typename Impl::DynInstPtr DynInstPtr;
60 typedef typename Impl::O3CPU O3CPU;
46/**
47 * DefaultFetch class handles both single threaded and SMT fetch. Its
48 * width is specified by the parameters; each cycle it tries to fetch
49 * that many instructions. It supports using a branch predictor to
50 * predict direction and targets.
51 * It supports the idling functionality of the CPU by indicating to
52 * the CPU when it is active and inactive.
53 */
54template <class Impl>
55class DefaultFetch
56{
57 public:
58 /** Typedefs from Impl. */
59 typedef typename Impl::CPUPol CPUPol;
60 typedef typename Impl::DynInst DynInst;
61 typedef typename Impl::DynInstPtr DynInstPtr;
62 typedef typename Impl::O3CPU O3CPU;
61 typedef typename Impl::Params Params;
62
63 /** Typedefs from the CPU policy. */
64 typedef typename CPUPol::BPredUnit BPredUnit;
65 typedef typename CPUPol::FetchStruct FetchStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67
68 /** Typedefs from ISA. */
69 typedef TheISA::MachInst MachInst;

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155 /** Fetch policy. */
156 FetchPriority fetchPolicy;
157
158 /** List that has the threads organized by priority. */
159 std::list<unsigned> priorityList;
160
161 public:
162 /** DefaultFetch constructor. */
63
64 /** Typedefs from the CPU policy. */
65 typedef typename CPUPol::BPredUnit BPredUnit;
66 typedef typename CPUPol::FetchStruct FetchStruct;
67 typedef typename CPUPol::TimeStruct TimeStruct;
68
69 /** Typedefs from ISA. */
70 typedef TheISA::MachInst MachInst;

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156 /** Fetch policy. */
157 FetchPriority fetchPolicy;
158
159 /** List that has the threads organized by priority. */
160 std::list<unsigned> priorityList;
161
162 public:
163 /** DefaultFetch constructor. */
163 DefaultFetch(O3CPU *_cpu, Params *params);
164 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
164
165 /** Returns the name of fetch. */
166 std::string name() const;
167
168 /** Registers statistics. */
169 void regStats();
170
171 /** Returns the icache port. */

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166 /** Returns the name of fetch. */
167 std::string name() const;
168
169 /** Registers statistics. */
170 void regStats();
171
172 /** Returns the icache port. */

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