fetch.hh (3949:b6664282d899) fetch.hh (3968:0a08763926a1)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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357 /** Variable that tracks if fetch has written to the time buffer this
358 * cycle. Used to tell CPU if there is activity this cycle.
359 */
360 bool wroteToTimeBuffer;
361
362 /** Tracks how many instructions has been fetched this cycle. */
363 int numInst;
364
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 348 unchanged lines hidden (view full) ---

357 /** Variable that tracks if fetch has written to the time buffer this
358 * cycle. Used to tell CPU if there is activity this cycle.
359 */
360 bool wroteToTimeBuffer;
361
362 /** Tracks how many instructions has been fetched this cycle. */
363 int numInst;
364
365 /** Tracks delay slot information for threads in ISAs which use
366 * delay slots;
367 */
368 struct DelaySlotInfo {
369 InstSeqNum delaySlotSeqNum;
370 InstSeqNum branchSeqNum;
371 int numInsts;
372 Addr targetAddr;
373 bool targetReady;
374 };
375
376 DelaySlotInfo delaySlotInfo[Impl::MaxThreads];
377
378 /** Source of possible stalls. */
379 struct Stalls {
380 bool decode;
381 bool rename;
382 bool iew;
383 bool commit;
384 };
385

--- 109 unchanged lines hidden --- 		365 /** Source of possible stalls. */
366 struct Stalls {
367 bool decode;
368 bool rename;
369 bool iew;
370 bool commit;
371 };
372

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