fetch.hh (2843:19c4c6c2b5b1) | fetch.hh (2863:2592e056dc5c) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 167 unchanged lines hidden (view full) --- 176 177 /** Initialize stage. */ 178 void initStage(); 179 180 /** Processes cache completion event. */ 181 void processCacheCompletion(PacketPtr pkt); 182 183 /** Begins the drain of the fetch stage. */ | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 167 unchanged lines hidden (view full) --- 176 177 /** Initialize stage. */ 178 void initStage(); 179 180 /** Processes cache completion event. */ 181 void processCacheCompletion(PacketPtr pkt); 182 183 /** Begins the drain of the fetch stage. */ |
184 void drain(); | 184 bool drain(); |
185 186 /** Resumes execution after a drain. */ 187 void resume(); 188 189 /** Tells fetch stage to prepare to be switched out. */ 190 void switchOut(); 191 192 /** Takes over from another CPU's thread. */ --- 278 unchanged lines hidden --- | 185 186 /** Resumes execution after a drain. */ 187 void resume(); 188 189 /** Tells fetch stage to prepare to be switched out. */ 190 void switchOut(); 191 192 /** Takes over from another CPU's thread. */ --- 278 unchanged lines hidden --- |