fetch.hh (2808:a88ea76f6738) fetch.hh (2840:227f7c4f8c81)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
39#include "mem/packet_impl.hh"
40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
39#include "mem/packet_impl.hh"
40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
43class Sampler;
44
45/**
46 * DefaultFetch class handles both single threaded and SMT fetch. Its
47 * width is specified by the parameters; each cycle it tries to fetch
48 * that many instructions. It supports using a branch predictor to
49 * predict direction and targets.
50 * It supports the idling functionality of the CPU by indicating to
51 * the CPU when it is active and inactive.
52 */

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43/**
44 * DefaultFetch class handles both single threaded and SMT fetch. Its
45 * width is specified by the parameters; each cycle it tries to fetch
46 * that many instructions. It supports using a branch predictor to
47 * predict direction and targets.
48 * It supports the idling functionality of the CPU by indicating to
49 * the CPU when it is active and inactive.
50 */

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