fetch.hh (2757:58e3a66e72f7) fetch.hh (2808:a88ea76f6738)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
39#include "mem/packet.hh"
39#include "mem/packet_impl.hh"
40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
43class Sampler;
44
45/**
46 * DefaultFetch class handles both single threaded and SMT fetch. Its
47 * width is specified by the parameters; each cycle it tries to fetch

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40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
43class Sampler;
44
45/**
46 * DefaultFetch class handles both single threaded and SMT fetch. Its
47 * width is specified by the parameters; each cycle it tries to fetch

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