fetch.hh (13641:648f3106ebdf) fetch.hh (14195:c5efdb3319aa)
1/*
2 * Copyright (c) 2010-2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 45 unchanged lines hidden (view full) ---

54#include "cpu/translation.hh"
55#include "enums/FetchPolicy.hh"
56#include "mem/packet.hh"
57#include "mem/port.hh"
58#include "sim/eventq.hh"
59#include "sim/probe/probe.hh"
60
61struct DerivO3CPUParams;
1/*
2 * Copyright (c) 2010-2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 45 unchanged lines hidden (view full) ---

54#include "cpu/translation.hh"
55#include "enums/FetchPolicy.hh"
56#include "mem/packet.hh"
57#include "mem/port.hh"
58#include "sim/eventq.hh"
59#include "sim/probe/probe.hh"
60
61struct DerivO3CPUParams;
62template <class Impl>
63class FullO3CPU;
62
63/**
64 * DefaultFetch class handles both single threaded and SMT fetch. Its
65 * width is specified by the parameters; each cycle it tries to fetch
66 * that many instructions. It supports using a branch predictor to
67 * predict direction and targets.
68 * It supports the idling functionality of the CPU by indicating to
69 * the CPU when it is active and inactive.

--- 10 unchanged lines hidden (view full) ---

80
81 /** Typedefs from the CPU policy. */
82 typedef typename CPUPol::FetchStruct FetchStruct;
83 typedef typename CPUPol::TimeStruct TimeStruct;
84
85 /** Typedefs from ISA. */
86 typedef TheISA::MachInst MachInst;
87
64
65/**
66 * DefaultFetch class handles both single threaded and SMT fetch. Its
67 * width is specified by the parameters; each cycle it tries to fetch
68 * that many instructions. It supports using a branch predictor to
69 * predict direction and targets.
70 * It supports the idling functionality of the CPU by indicating to
71 * the CPU when it is active and inactive.

--- 10 unchanged lines hidden (view full) ---

82
83 /** Typedefs from the CPU policy. */
84 typedef typename CPUPol::FetchStruct FetchStruct;
85 typedef typename CPUPol::TimeStruct TimeStruct;
86
87 /** Typedefs from ISA. */
88 typedef TheISA::MachInst MachInst;
89
90 /**
91 * IcachePort class for instruction fetch.
92 */
93 class IcachePort : public MasterPort
94 {
95 protected:
96 /** Pointer to fetch. */
97 DefaultFetch<Impl> *fetch;
98
99 public:
100 /** Default constructor. */
101 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
102 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
103 { }
104
105 protected:
106
107 /** Timing version of receive. Handles setting fetch to the
108 * proper status to start fetching. */
109 virtual bool recvTimingResp(PacketPtr pkt);
110
111 /** Handles doing a retry of a failed fetch. */
112 virtual void recvReqRetry();
113 };
114
88 class FetchTranslation : public BaseTLB::Translation
89 {
90 protected:
91 DefaultFetch<Impl> *fetch;
92
93 public:
94 FetchTranslation(DefaultFetch<Impl> *_fetch)
95 : fetch(_fetch)

--- 252 unchanged lines hidden (view full) ---

348 Addr fetchBufferAlignPC(Addr addr)
349 {
350 return (addr & ~(fetchBufferMask));
351 }
352
353 /** The decoder. */
354 TheISA::Decoder *decoder[Impl::MaxThreads];
355
115 class FetchTranslation : public BaseTLB::Translation
116 {
117 protected:
118 DefaultFetch<Impl> *fetch;
119
120 public:
121 FetchTranslation(DefaultFetch<Impl> *_fetch)
122 : fetch(_fetch)

--- 252 unchanged lines hidden (view full) ---

375 Addr fetchBufferAlignPC(Addr addr)
376 {
377 return (addr & ~(fetchBufferMask));
378 }
379
380 /** The decoder. */
381 TheISA::Decoder *decoder[Impl::MaxThreads];
382
383 MasterPort &getInstPort() { return icachePort; }
384
356 private:
357 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
358 StaticInstPtr curMacroop, TheISA::PCState thisPC,
359 TheISA::PCState nextPC, bool trace);
360
361 /** Returns the appropriate thread to fetch, given the fetch policy. */
362 ThreadID getFetchingThread();
363

--- 142 unchanged lines hidden (view full) ---

506 /** Thread ID being fetched. */
507 ThreadID threadFetched;
508
509 /** Checks if there is an interrupt pending. If there is, fetch
510 * must stop once it is not fetching PAL instructions.
511 */
512 bool interruptPending;
513
385 private:
386 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
387 StaticInstPtr curMacroop, TheISA::PCState thisPC,
388 TheISA::PCState nextPC, bool trace);
389
390 /** Returns the appropriate thread to fetch, given the fetch policy. */
391 ThreadID getFetchingThread();
392

--- 142 unchanged lines hidden (view full) ---

535 /** Thread ID being fetched. */
536 ThreadID threadFetched;
537
538 /** Checks if there is an interrupt pending. If there is, fetch
539 * must stop once it is not fetching PAL instructions.
540 */
541 bool interruptPending;
542
543 /** Instruction port. Note that it has to appear after the fetch stage. */
544 IcachePort icachePort;
545
514 /** Set to true if a pipelined I-cache request should be issued. */
515 bool issuePipelinedIfetch[Impl::MaxThreads];
516
517 /** Event used to delay fault generation of translation faults */
518 FinishTranslationEvent finishTranslationEvent;
519
520 // @todo: Consider making these vectors and tracking on a per thread basis.
521 /** Stat for total number of cycles stalled due to an icache miss. */

--- 52 unchanged lines hidden --- 		546 /** Set to true if a pipelined I-cache request should be issued. */
547 bool issuePipelinedIfetch[Impl::MaxThreads];
548
549 /** Event used to delay fault generation of translation faults */
550 FinishTranslationEvent finishTranslationEvent;
551
552 // @todo: Consider making these vectors and tracking on a per thread basis.
553 /** Stat for total number of cycles stalled due to an icache miss. */

--- 52 unchanged lines hidden ---