fetch.hh (12622:91cce46512f2) fetch.hh (12749:223c83ed9979)
1/*
2 * Copyright (c) 2010-2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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94 : fetch(_fetch)
95 {}
96
97 void
98 markDelayed()
99 {}
100
101 void
1/*
2 * Copyright (c) 2010-2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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94 : fetch(_fetch)
95 {}
96
97 void
98 markDelayed()
99 {}
100
101 void
102 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
102 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
103 BaseTLB::Mode mode)
104 {
105 assert(mode == BaseTLB::Execute);
106 fetch->finishTranslation(fault, req);
107 delete this;
108 }
109 };
110

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124 : fetch(_fetch)
125 {}
126
127 void setFault(Fault _fault)
128 {
129 fault = _fault;
130 }
131
103 BaseTLB::Mode mode)
104 {
105 assert(mode == BaseTLB::Execute);
106 fetch->finishTranslation(fault, req);
107 delete this;
108 }
109 };
110

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124 : fetch(_fetch)
125 {}
126
127 void setFault(Fault _fault)
128 {
129 fault = _fault;
130 }
131
132 void setReq(RequestPtr _req)
132 void setReq(const RequestPtr &_req)
133 {
134 req = _req;
135 }
136
137 /** Process the delayed finish translation */
138 void process()
139 {
140 assert(fetch->numInst < fetch->fetchWidth);

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290 * @param vaddr The memory address that is being fetched from.
291 * @param ret_fault The fault reference that will be set to the result of
292 * the icache access.
293 * @param tid Thread id.
294 * @param pc The actual PC of the current instruction.
295 * @return Any fault that occured.
296 */
297 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
133 {
134 req = _req;
135 }
136
137 /** Process the delayed finish translation */
138 void process()
139 {
140 assert(fetch->numInst < fetch->fetchWidth);

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290 * @param vaddr The memory address that is being fetched from.
291 * @param ret_fault The fault reference that will be set to the result of
292 * the icache access.
293 * @param tid Thread id.
294 * @param pc The actual PC of the current instruction.
295 * @return Any fault that occured.
296 */
297 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
298 void finishTranslation(const Fault &fault, RequestPtr mem_req);
298 void finishTranslation(const Fault &fault, const RequestPtr &mem_req);
299
300
301 /** Check if an interrupt is pending and that we need to handle
302 */
303 bool
304 checkInterrupt(Addr pc)
305 {
306 return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));

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300
301 /** Check if an interrupt is pending and that we need to handle
302 */
303 bool
304 checkInterrupt(Addr pc)
305 {
306 return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));

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