1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
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37#include "base/statistics.hh"
38#include "base/timebuf.hh"
39#include "cpu/pc_event.hh"
40#include "mem/packet.hh"
41#include "mem/port.hh"
42#include "sim/eventq.hh"
43
44/**
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
51 */
52template <class Impl>
53class DefaultFetch
54{
55 public:
56 /** Typedefs from Impl. */
57 typedef typename Impl::CPUPol CPUPol;
58 typedef typename Impl::DynInst DynInst;
59 typedef typename Impl::DynInstPtr DynInstPtr;
60 typedef typename Impl::O3CPU O3CPU;
61 typedef typename Impl::Params Params;
62
63 /** Typedefs from the CPU policy. */
64 typedef typename CPUPol::BPredUnit BPredUnit;
65 typedef typename CPUPol::FetchStruct FetchStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67
68 /** Typedefs from ISA. */
69 typedef TheISA::MachInst MachInst;
70 typedef TheISA::ExtMachInst ExtMachInst;
71
72 /** IcachePort class for DefaultFetch. Handles doing the
73 * communication with the cache/memory.
74 */
75 class IcachePort : public Port
76 {
77 protected:
78 /** Pointer to fetch. */
79 DefaultFetch<Impl> *fetch;
80
81 public:
82 /** Default constructor. */
83 IcachePort(DefaultFetch<Impl> *_fetch)
84 : Port(_fetch->name() + "-iport"), fetch(_fetch)
85 { }
86
87 bool snoopRangeSent;
88
89 protected:
90 /** Atomic version of receive. Panics. */
91 virtual Tick recvAtomic(PacketPtr pkt);
92
93 /** Functional version of receive. Panics. */
94 virtual void recvFunctional(PacketPtr pkt);
95
96 /** Receives status change. Other than range changing, panics. */
97 virtual void recvStatusChange(Status status);
98
99 /** Returns the address ranges of this device. */
100 virtual void getDeviceAddressRanges(AddrRangeList &resp,
101 AddrRangeList &snoop)
102 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
103
104 /** Timing version of receive. Handles setting fetch to the
105 * proper status to start fetching. */
106 virtual bool recvTiming(PacketPtr pkt);
107
108 /** Handles doing a retry of a failed fetch. */
109 virtual void recvRetry();
110 };
111
112
113 public:
114 /** Overall fetch status. Used to determine if the CPU can
115 * deschedule itsef due to a lack of activity.
116 */
117 enum FetchStatus {
118 Active,
119 Inactive
120 };
121
122 /** Individual thread status. */
123 enum ThreadStatus {
124 Running,
125 Idle,
126 Squashing,
127 Blocked,
128 Fetching,
129 TrapPending,
130 QuiescePending,
131 SwitchOut,
132 IcacheWaitResponse,
133 IcacheWaitRetry,
134 IcacheAccessComplete
135 };
136
137 /** Fetching Policy, Add new policies here.*/
138 enum FetchPriority {
139 SingleThread,
140 RoundRobin,
141 Branch,
142 IQ,
143 LSQ
144 };
145
146 private:
147 /** Fetch status. */
148 FetchStatus _status;
149
150 /** Per-thread status. */
151 ThreadStatus fetchStatus[Impl::MaxThreads];
152
153 /** Fetch policy. */
154 FetchPriority fetchPolicy;
155
156 /** List that has the threads organized by priority. */
157 std::list<unsigned> priorityList;
158
159 public:
160 /** DefaultFetch constructor. */
161 DefaultFetch(Params *params);
162
163 /** Returns the name of fetch. */
164 std::string name() const;
165
166 /** Registers statistics. */
167 void regStats();
168
169 /** Returns the icache port. */
170 Port *getIcachePort() { return icachePort; }
171
172 /** Sets CPU pointer. */
173 void setCPU(O3CPU *cpu_ptr);
174
175 /** Sets the main backwards communication time buffer pointer. */
176 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
177
178 /** Sets pointer to list of active threads. */
179 void setActiveThreads(std::list<unsigned> *at_ptr);
180
181 /** Sets pointer to time buffer used to communicate to the next stage. */
182 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
183
184 /** Initialize stage. */
185 void initStage();
186
187 /** Processes cache completion event. */
188 void processCacheCompletion(PacketPtr pkt);
189
190 /** Begins the drain of the fetch stage. */
191 bool drain();
192
193 /** Resumes execution after a drain. */
194 void resume();
195
196 /** Tells fetch stage to prepare to be switched out. */
197 void switchOut();
198
199 /** Takes over from another CPU's thread. */
200 void takeOverFrom();
201
202 /** Checks if the fetch stage is switched out. */
203 bool isSwitchedOut() { return switchedOut; }
204
205 /** Tells fetch to wake up from a quiesce instruction. */
206 void wakeFromQuiesce();
207
208 private:
209 /** Changes the status of this stage to active, and indicates this
210 * to the CPU.
211 */
212 inline void switchToActive();
213
214 /** Changes the status of this stage to inactive, and indicates
215 * this to the CPU.
216 */
217 inline void switchToInactive();
218
219 /**
220 * Looks up in the branch predictor to see if the next PC should be
221 * either next PC+=MachInst or a branch target.
222 * @param next_PC Next PC variable passed in by reference. It is
223 * expected to be set to the current PC; it will be updated with what
224 * the next PC will be.
225 * @param next_NPC Used for ISAs which use delay slots.
226 * @return Whether or not a branch was predicted as taken.
227 */
228 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
229
230 /**
231 * Fetches the cache line that contains fetch_PC. Returns any
232 * fault that happened. Puts the data into the class variable
233 * cacheData.
234 * @param fetch_PC The PC address that is being fetched from.
235 * @param ret_fault The fault reference that will be set to the result of
236 * the icache access.
237 * @param tid Thread id.
238 * @return Any fault that occured.
239 */
240 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
241
242 /** Squashes a specific thread and resets the PC. */
243 inline void doSquash(const Addr &new_PC, const Addr &new_NPC, unsigned tid);
244
245 /** Squashes a specific thread and resets the PC. Also tells the CPU to
246 * remove any instructions between fetch and decode that should be sqaushed.
247 */
248 void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
249 const InstSeqNum &seq_num, unsigned tid);
250
251 /** Checks if a thread is stalled. */
252 bool checkStall(unsigned tid) const;
253
254 /** Updates overall fetch stage status; to be called at the end of each
255 * cycle. */
256 FetchStatus updateFetchStatus();
257
258 public:
259 /** Squashes a specific thread and resets the PC. Also tells the CPU to
260 * remove any instructions that are not in the ROB. The source of this
261 * squash should be the commit stage.
262 */
263 void squash(const Addr &new_PC, const Addr &new_NPC,
264 const InstSeqNum &seq_num,
265 bool squash_delay_slot, unsigned tid);
266
267 /** Ticks the fetch stage, processing all inputs signals and fetching
268 * as many instructions as possible.
269 */
270 void tick();
271
272 /** Checks all input signals and updates the status as necessary.
273 * @return: Returns if the status has changed due to input signals.
274 */
275 bool checkSignalsAndUpdate(unsigned tid);
276
277 /** Does the actual fetching of instructions and passing them on to the
278 * next stage.
279 * @param status_change fetch() sets this variable if there was a status
280 * change (ie switching to IcacheMissStall).
281 */
282 void fetch(bool &status_change);
283
284 /** Align a PC to the start of an I-cache block. */
285 Addr icacheBlockAlignPC(Addr addr)
286 {
287 addr = TheISA::realPCToFetchPC(addr);
288 return (addr & ~(cacheBlkMask));
289 }
290
291 private:
292 /** Handles retrying the fetch access. */
293 void recvRetry();
294
295 /** Returns the appropriate thread to fetch, given the fetch policy. */
296 int getFetchingThread(FetchPriority &fetch_priority);
297
298 /** Returns the appropriate thread to fetch using a round robin policy. */
299 int roundRobin();
300
301 /** Returns the appropriate thread to fetch using the IQ count policy. */
302 int iqCount();
303
304 /** Returns the appropriate thread to fetch using the LSQ count policy. */
305 int lsqCount();
306
307 /** Returns the appropriate thread to fetch using the branch count policy. */
308 int branchCount();
309
310 private:
311 /** Pointer to the O3CPU. */
312 O3CPU *cpu;
313
314 /** Time buffer interface. */
315 TimeBuffer<TimeStruct> *timeBuffer;
316
317 /** Wire to get decode's information from backwards time buffer. */
318 typename TimeBuffer<TimeStruct>::wire fromDecode;
319
320 /** Wire to get rename's information from backwards time buffer. */
321 typename TimeBuffer<TimeStruct>::wire fromRename;
322
323 /** Wire to get iew's information from backwards time buffer. */
324 typename TimeBuffer<TimeStruct>::wire fromIEW;
325
326 /** Wire to get commit's information from backwards time buffer. */
327 typename TimeBuffer<TimeStruct>::wire fromCommit;
328
329 /** Internal fetch instruction queue. */
330 TimeBuffer<FetchStruct> *fetchQueue;
331
332 //Might be annoying how this name is different than the queue.
333 /** Wire used to write any information heading to decode. */
334 typename TimeBuffer<FetchStruct>::wire toDecode;
335
336 /** Icache interface. */
337 IcachePort *icachePort;
338
339 /** BPredUnit. */
340 BPredUnit branchPred;
341
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345 /** Per-thread fetch PC. */
346 Addr PC[Impl::MaxThreads];
347
348 /** Per-thread next PC. */
349 Addr nextPC[Impl::MaxThreads];
350
351 /** Per-thread next Next PC.
352 * This is not a real register but is used for
353 * architectures that use a branch-delay slot.
354 * (such as MIPS or Sparc)
355 */
356 Addr nextNPC[Impl::MaxThreads];
357
358 /** Memory request used to access cache. */
359 RequestPtr memReq[Impl::MaxThreads];
360
361 /** Variable that tracks if fetch has written to the time buffer this
362 * cycle. Used to tell CPU if there is activity this cycle.
363 */
364 bool wroteToTimeBuffer;
365
366 /** Tracks how many instructions has been fetched this cycle. */
367 int numInst;
368
369 /** Source of possible stalls. */
370 struct Stalls {
371 bool decode;
372 bool rename;
373 bool iew;
374 bool commit;
375 };
376
377 /** Tracks which stages are telling fetch to stall. */
378 Stalls stalls[Impl::MaxThreads];
379
380 /** Decode to fetch delay, in ticks. */
381 unsigned decodeToFetchDelay;
382
383 /** Rename to fetch delay, in ticks. */
384 unsigned renameToFetchDelay;
385
386 /** IEW to fetch delay, in ticks. */
387 unsigned iewToFetchDelay;
388
389 /** Commit to fetch delay, in ticks. */
390 unsigned commitToFetchDelay;
391
392 /** The width of fetch in instructions. */
393 unsigned fetchWidth;
394
395 /** Is the cache blocked? If so no threads can access it. */
396 bool cacheBlocked;
397
398 /** The packet that is waiting to be retried. */
399 PacketPtr retryPkt;
400
401 /** The thread that is waiting on the cache to tell fetch to retry. */
402 int retryTid;
403
404 /** Cache block size. */
405 int cacheBlkSize;
406
407 /** Mask to get a cache block's address. */
408 Addr cacheBlkMask;
409
410 /** The cache line being fetched. */
411 uint8_t *cacheData[Impl::MaxThreads];
412
413 /** The PC of the cacheline that has been loaded. */
414 Addr cacheDataPC[Impl::MaxThreads];
415
416 /** Whether or not the cache data is valid. */
417 bool cacheDataValid[Impl::MaxThreads];
418
419 /** Size of instructions. */
420 int instSize;
421
422 /** Icache stall statistics. */
423 Counter lastIcacheStall[Impl::MaxThreads];
424
425 /** List of Active Threads */
426 std::list<unsigned> *activeThreads;
427
428 /** Number of threads. */
429 unsigned numThreads;
430
431 /** Number of threads that are actively fetching. */
432 unsigned numFetchingThreads;
433
434 /** Thread ID being fetched. */
435 int threadFetched;
436
437 /** Checks if there is an interrupt pending. If there is, fetch
438 * must stop once it is not fetching PAL instructions.
439 */
440 bool interruptPending;
441
442 /** Is there a drain pending. */
443 bool drainPending;
444
445 /** Records if fetch is switched out. */
446 bool switchedOut;
447
448 // @todo: Consider making these vectors and tracking on a per thread basis.
449 /** Stat for total number of cycles stalled due to an icache miss. */
450 Stats::Scalar<> icacheStallCycles;
451 /** Stat for total number of fetched instructions. */
452 Stats::Scalar<> fetchedInsts;
453 /** Total number of fetched branches. */
454 Stats::Scalar<> fetchedBranches;
455 /** Stat for total number of predicted branches. */
456 Stats::Scalar<> predictedBranches;
457 /** Stat for total number of cycles spent fetching. */
458 Stats::Scalar<> fetchCycles;
459 /** Stat for total number of cycles spent squashing. */
460 Stats::Scalar<> fetchSquashCycles;
461 /** Stat for total number of cycles spent blocked due to other stages in
462 * the pipeline.
463 */
464 Stats::Scalar<> fetchIdleCycles;
465 /** Total number of cycles spent blocked. */
466 Stats::Scalar<> fetchBlockedCycles;
467 /** Total number of cycles spent in any other state. */
468 Stats::Scalar<> fetchMiscStallCycles;
469 /** Stat for total number of fetched cache lines. */
470 Stats::Scalar<> fetchedCacheLines;
471 /** Total number of outstanding icache accesses that were dropped
472 * due to a squash.
473 */
474 Stats::Scalar<> fetchIcacheSquashes;
475 /** Distribution of number of instructions fetched each cycle. */
476 Stats::Distribution<> fetchNisnDist;
477 /** Rate of how often fetch was idle. */
478 Stats::Formula idleRate;
479 /** Number of branch fetches per cycle. */
480 Stats::Formula branchRate;
481 /** Number of instruction fetched per cycle. */
482 Stats::Formula fetchRate;
483};
484
485#endif //__CPU_O3_FETCH_HH__
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