1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 202 unchanged lines hidden (view full) --- 211 void setActiveThreads(std::list<ThreadID> *at_ptr); 212 213 /** Sets pointer to time buffer used to communicate to the next stage. */ 214 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 215 216 /** Initialize stage. */ 217 void startupStage(); 218 |
219 /** Handles retrying the fetch access. */ 220 void recvRetry(); 221 222 /** Processes cache completion event. */ 223 void processCacheCompletion(PacketPtr pkt); 224 225 /** Resume after a drain. */ 226 void drainResume(); --- 229 unchanged lines hidden (view full) --- 456 457 /** The packet that is waiting to be retried. */ 458 PacketPtr retryPkt; 459 460 /** The thread that is waiting on the cache to tell fetch to retry. */ 461 ThreadID retryTid; 462 463 /** Cache block size. */ |
464 unsigned int cacheBlkSize; |
465 466 /** Mask to get a cache block's address. */ 467 Addr cacheBlkMask; 468 469 /** The cache line being fetched. */ 470 uint8_t *cacheData[Impl::MaxThreads]; 471 472 /** The PC of the cacheline that has been loaded. */ --- 88 unchanged lines hidden --- |