1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_FETCH_HH__ 33#define __CPU_O3_FETCH_HH__ 34 35#include "arch/utility.hh" |
36#include "arch/predecoder.hh" |
37#include "base/statistics.hh" 38#include "base/timebuf.hh" 39#include "cpu/pc_event.hh" 40#include "mem/packet.hh" 41#include "mem/port.hh" 42#include "sim/eventq.hh" 43 44/** --- 289 unchanged lines hidden (view full) --- 334 typename TimeBuffer<FetchStruct>::wire toDecode; 335 336 /** Icache interface. */ 337 IcachePort *icachePort; 338 339 /** BPredUnit. */ 340 BPredUnit branchPred; 341 |
342 /** Predecoder. */ 343 TheISA::Predecoder predecoder; 344 |
345 /** Per-thread fetch PC. */ 346 Addr PC[Impl::MaxThreads]; 347 348 /** Per-thread next PC. */ 349 Addr nextPC[Impl::MaxThreads]; 350 351 /** Per-thread next Next PC. 352 * This is not a real register but is used for --- 133 unchanged lines hidden --- |