1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 393 unchanged lines hidden (view full) --- 402 Addr cacheBlkMask; 403 404 /** The cache line being fetched. */ 405 uint8_t *cacheData[Impl::MaxThreads]; 406 407 /** The PC of the cacheline that has been loaded. */ 408 Addr cacheDataPC[Impl::MaxThreads]; 409 |
410 /** Whether or not the cache data is valid. */ 411 bool cacheDataValid[Impl::MaxThreads]; 412 |
413 /** Size of instructions. */ 414 int instSize; 415 416 /** Icache stall statistics. */ 417 Counter lastIcacheStall[Impl::MaxThreads]; 418 419 /** List of Active Threads */ 420 std::list<unsigned> *activeThreads; --- 59 unchanged lines hidden --- |