2c2
< * Copyright (c) 2004-2006 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2005 The Regents of The University of Michigan
26a27,28
> *
> * Authors: Kevin Lim
29,30c31,32
< #ifndef __CPU_O3_FETCH_HH__
< #define __CPU_O3_FETCH_HH__
---
> // Todo: SMT fetch,
> // Add a way to get a stage's current status.
31a34,36
> #ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__
> #define __CPU_O3_CPU_SIMPLE_FETCH_HH__
>
38,39d42
< class Sampler;
<
41,46c44,46
< * DefaultFetch class handles both single threaded and SMT fetch. Its
< * width is specified by the parameters; each cycle it tries to fetch
< * that many instructions. It supports using a branch predictor to
< * predict direction and targets.
< * It supports the idling functionalitiy of the CPU by indicating to
< * the CPU when it is active and inactive.
---
> * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch
> * will stall if there's an Icache miss, but otherwise assumes a one cycle
> * Icache hit.
47a48
>
49c50
< class DefaultFetch
---
> class SimpleFetch
59d59
< /** Typedefs from the CPU policy. */
66d65
< typedef TheISA::ExtMachInst ExtMachInst;
69,78c68
< /** Overall fetch status. Used to determine if the CPU can
< * deschedule itsef due to a lack of activity.
< */
< enum FetchStatus {
< Active,
< Inactive
< };
<
< /** Individual thread status. */
< enum ThreadStatus {
---
> enum Status {
83,86d72
< Fetching,
< TrapPending,
< QuiescePending,
< SwitchOut,
91,98c77,78
< /** Fetching Policy, Add new policies here.*/
< enum FetchPriority {
< SingleThread,
< RoundRobin,
< Branch,
< IQ,
< LSQ
< };
---
> // May eventually need statuses on a per thread basis.
> Status _status;
100,102c80
< private:
< /** Fetch status. */
< FetchStatus _status;
---
> bool stalled;
104,112d81
< /** Per-thread status. */
< ThreadStatus fetchStatus[Impl::MaxThreads];
<
< /** Fetch policy. */
< FetchPriority fetchPolicy;
<
< /** List that has the threads organized by priority. */
< std::list<unsigned> priorityList;
<
117,121c86
< MemReqPtr req;
< /** Pointer to fetch. */
< DefaultFetch *fetch;
< /** Thread id. */
< // unsigned threadId;
---
> SimpleFetch *fetch;
124,127c89
< /** Constructs a cache completion event, which tells fetch when the
< * cache miss is complete.
< */
< CacheCompletionEvent(MemReqPtr &_req, DefaultFetch *_fetch);
---
> CacheCompletionEvent(SimpleFetch *_fetch);
129d90
< /** Processes cache completion event. */
131d91
< /** Returns the description of the cache completion event. */
136,137c96,97
< /** DefaultFetch constructor. */
< DefaultFetch(Params *params);
---
> /** SimpleFetch constructor. */
> SimpleFetch(Params ¶ms);
139,142d98
< /** Returns the name of fetch. */
< std::string name() const;
<
< /** Registers statistics. */
145d100
< /** Sets CPU pointer. */
148d102
< /** Sets the main backwards communication time buffer pointer. */
151,154d104
< /** Sets pointer to list of active threads. */
< void setActiveThreads(std::list<unsigned> *at_ptr);
<
< /** Sets pointer to time buffer used to communicate to the next stage. */
157,158c107
< /** Sets pointer to page table. */
< // void setPageTable(PageTable *pt_ptr);
---
> void processCacheCompletion();
160,175d108
< /** Initialize stage. */
< void initStage();
<
< /** Processes cache completion event. */
< void processCacheCompletion(MemReqPtr &req);
<
< void switchOut();
<
< void doSwitchOut();
<
< void takeOverFrom();
<
< bool isSwitchedOut() { return switchedOut; }
<
< void wakeFromQuiesce();
<
177,186d109
< /** Changes the status of this stage to active, and indicates this
< * to the CPU.
< */
< inline void switchToActive();
<
< /** Changes the status of this stage to inactive, and indicates
< * this to the CPU.
< */
< inline void switchToInactive();
<
202,204d124
< * @param ret_fault The fault reference that will be set to the result of
< * the icache access.
< * @param tid Thread id.
207c127
< bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
---
> Fault fetchCacheLine(Addr fetch_PC);
209,210c129
< /** Squashes a specific thread and resets the PC. */
< inline void doSquash(const Addr &new_PC, unsigned tid);
---
> inline void doSquash(const Addr &new_PC);
212,216c131
< /** Squashes a specific thread and resets the PC. Also tells the CPU to
< * remove any instructions between fetch and decode that should be sqaushed.
< */
< void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
< unsigned tid);
---
> void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num);
218,224d132
< /** Checks if a thread is stalled. */
< bool checkStall(unsigned tid) const;
<
< /** Updates overall fetch stage status; to be called at the end of each
< * cycle. */
< FetchStatus updateFetchStatus();
<
226,230c134,135
< /** Squashes a specific thread and resets the PC. Also tells the CPU to
< * remove any instructions that are not in the ROB. The source of this
< * squash should be the commit stage.
< */
< void squash(const Addr &new_PC, unsigned tid);
---
> // Figure out PC vs next PC and how it should be updated
> void squash(const Addr &new_PC);
232,234d136
< /** Ticks the fetch stage, processing all inputs signals and fetching
< * as many instructions as possible.
< */
237,240c139
< /** Checks all input signals and updates the status as necessary.
< * @return: Returns if the status has changed due to input signals.
< */
< bool checkSignalsAndUpdate(unsigned tid);
---
> void fetch();
242,249c141,142
< /** Does the actual fetching of instructions and passing them on to the
< * next stage.
< * @param status_change fetch() sets this variable if there was a status
< * change (ie switching to IcacheMissStall).
< */
< void fetch(bool &status_change);
<
< /** Align a PC to the start of an I-cache block. */
---
> // Align an address (typically a PC) to the start of an I-cache block.
> // We fold in the PISA 64- to 32-bit conversion here as well.
257,272d149
< /** Returns the appropriate thread to fetch, given the fetch policy. */
< int getFetchingThread(FetchPriority &fetch_priority);
<
< /** Returns the appropriate thread to fetch using a round robin policy. */
< int roundRobin();
<
< /** Returns the appropriate thread to fetch using the IQ count policy. */
< int iqCount();
<
< /** Returns the appropriate thread to fetch using the LSQ count policy. */
< int lsqCount();
<
< /** Returns the appropriate thread to fetch using the branch count policy. */
< int branchCount();
<
< private:
304,307d180
< Addr PC[Impl::MaxThreads];
<
< Addr nextPC[Impl::MaxThreads];
<
309c182
< MemReqPtr memReq[Impl::MaxThreads];
---
> MemReqPtr memReq;
311,329d183
< /** Variable that tracks if fetch has written to the time buffer this
< * cycle. Used to tell CPU if there is activity this cycle.
< */
< bool wroteToTimeBuffer;
<
< /** Tracks how many instructions has been fetched this cycle. */
< int numInst;
<
< /** Source of possible stalls. */
< struct Stalls {
< bool decode;
< bool rename;
< bool iew;
< bool commit;
< };
<
< /** Tracks which stages are telling fetch to stall. */
< Stalls stalls[Impl::MaxThreads];
<
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< uint8_t *cacheData[Impl::MaxThreads];
---
> uint8_t *cacheData;
358c212
< Counter lastIcacheStall[Impl::MaxThreads];
---
> Counter lastIcacheStall;
360,382d213
< /** List of Active Threads */
< std::list<unsigned> *activeThreads;
<
< /** Number of threads. */
< unsigned numThreads;
<
< /** Number of threads that are actively fetching. */
< unsigned numFetchingThreads;
<
< /** Thread ID being fetched. */
< int threadFetched;
<
< bool interruptPending;
<
< bool switchedOut;
<
< #if !FULL_SYSTEM
< /** Page table pointer. */
< // PageTable *pTable;
< #endif
<
< // @todo: Consider making these vectors and tracking on a per thread basis.
< /** Stat for total number of cycles stalled due to an icache miss. */
384d214
< /** Stat for total number of fetched instructions. */
386,387d215
< Stats::Scalar<> fetchedBranches;
< /** Stat for total number of predicted branches. */
389d216
< /** Stat for total number of cycles spent fetching. */
391d217
< /** Stat for total number of cycles spent squashing. */
393,396d218
< /** Stat for total number of cycles spent blocked due to other stages in
< * the pipeline.
< */
< Stats::Scalar<> fetchIdleCycles;
398,400d219
<
< Stats::Scalar<> fetchMiscStallCycles;
< /** Stat for total number of fetched cache lines. */
403,408c222
< Stats::Scalar<> fetchIcacheSquashes;
< /** Distribution of number of instructions fetched each cycle. */
< Stats::Distribution<> fetchNisnDist;
< Stats::Formula idleRate;
< Stats::Formula branchRate;
< Stats::Formula fetchRate;
---
> Stats::Distribution<> fetch_nisn_dist;
411c225
< #endif //__CPU_O3_FETCH_HH__
---
> #endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__
< * Copyright (c) 2004-2006 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2005 The Regents of The University of Michigan
26a27,28
> *
> * Authors: Kevin Lim
29,30c31,32
< #ifndef __CPU_O3_FETCH_HH__
< #define __CPU_O3_FETCH_HH__
---
> // Todo: SMT fetch,
> // Add a way to get a stage's current status.
31a34,36
> #ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__
> #define __CPU_O3_CPU_SIMPLE_FETCH_HH__
>
38,39d42
< class Sampler;
<
41,46c44,46
< * DefaultFetch class handles both single threaded and SMT fetch. Its
< * width is specified by the parameters; each cycle it tries to fetch
< * that many instructions. It supports using a branch predictor to
< * predict direction and targets.
< * It supports the idling functionalitiy of the CPU by indicating to
< * the CPU when it is active and inactive.
---
> * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch
> * will stall if there's an Icache miss, but otherwise assumes a one cycle
> * Icache hit.
47a48
>
49c50
< class DefaultFetch
---
> class SimpleFetch
59d59
< /** Typedefs from the CPU policy. */
66d65
< typedef TheISA::ExtMachInst ExtMachInst;
69,78c68
< /** Overall fetch status. Used to determine if the CPU can
< * deschedule itsef due to a lack of activity.
< */
< enum FetchStatus {
< Active,
< Inactive
< };
<
< /** Individual thread status. */
< enum ThreadStatus {
---
> enum Status {
83,86d72
< Fetching,
< TrapPending,
< QuiescePending,
< SwitchOut,
91,98c77,78
< /** Fetching Policy, Add new policies here.*/
< enum FetchPriority {
< SingleThread,
< RoundRobin,
< Branch,
< IQ,
< LSQ
< };
---
> // May eventually need statuses on a per thread basis.
> Status _status;
100,102c80
< private:
< /** Fetch status. */
< FetchStatus _status;
---
> bool stalled;
104,112d81
< /** Per-thread status. */
< ThreadStatus fetchStatus[Impl::MaxThreads];
<
< /** Fetch policy. */
< FetchPriority fetchPolicy;
<
< /** List that has the threads organized by priority. */
< std::list<unsigned> priorityList;
<
117,121c86
< MemReqPtr req;
< /** Pointer to fetch. */
< DefaultFetch *fetch;
< /** Thread id. */
< // unsigned threadId;
---
> SimpleFetch *fetch;
124,127c89
< /** Constructs a cache completion event, which tells fetch when the
< * cache miss is complete.
< */
< CacheCompletionEvent(MemReqPtr &_req, DefaultFetch *_fetch);
---
> CacheCompletionEvent(SimpleFetch *_fetch);
129d90
< /** Processes cache completion event. */
131d91
< /** Returns the description of the cache completion event. */
136,137c96,97
< /** DefaultFetch constructor. */
< DefaultFetch(Params *params);
---
> /** SimpleFetch constructor. */
> SimpleFetch(Params ¶ms);
139,142d98
< /** Returns the name of fetch. */
< std::string name() const;
<
< /** Registers statistics. */
145d100
< /** Sets CPU pointer. */
148d102
< /** Sets the main backwards communication time buffer pointer. */
151,154d104
< /** Sets pointer to list of active threads. */
< void setActiveThreads(std::list<unsigned> *at_ptr);
<
< /** Sets pointer to time buffer used to communicate to the next stage. */
157,158c107
< /** Sets pointer to page table. */
< // void setPageTable(PageTable *pt_ptr);
---
> void processCacheCompletion();
160,175d108
< /** Initialize stage. */
< void initStage();
<
< /** Processes cache completion event. */
< void processCacheCompletion(MemReqPtr &req);
<
< void switchOut();
<
< void doSwitchOut();
<
< void takeOverFrom();
<
< bool isSwitchedOut() { return switchedOut; }
<
< void wakeFromQuiesce();
<
177,186d109
< /** Changes the status of this stage to active, and indicates this
< * to the CPU.
< */
< inline void switchToActive();
<
< /** Changes the status of this stage to inactive, and indicates
< * this to the CPU.
< */
< inline void switchToInactive();
<
202,204d124
< * @param ret_fault The fault reference that will be set to the result of
< * the icache access.
< * @param tid Thread id.
207c127
< bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
---
> Fault fetchCacheLine(Addr fetch_PC);
209,210c129
< /** Squashes a specific thread and resets the PC. */
< inline void doSquash(const Addr &new_PC, unsigned tid);
---
> inline void doSquash(const Addr &new_PC);
212,216c131
< /** Squashes a specific thread and resets the PC. Also tells the CPU to
< * remove any instructions between fetch and decode that should be sqaushed.
< */
< void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
< unsigned tid);
---
> void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num);
218,224d132
< /** Checks if a thread is stalled. */
< bool checkStall(unsigned tid) const;
<
< /** Updates overall fetch stage status; to be called at the end of each
< * cycle. */
< FetchStatus updateFetchStatus();
<
226,230c134,135
< /** Squashes a specific thread and resets the PC. Also tells the CPU to
< * remove any instructions that are not in the ROB. The source of this
< * squash should be the commit stage.
< */
< void squash(const Addr &new_PC, unsigned tid);
---
> // Figure out PC vs next PC and how it should be updated
> void squash(const Addr &new_PC);
232,234d136
< /** Ticks the fetch stage, processing all inputs signals and fetching
< * as many instructions as possible.
< */
237,240c139
< /** Checks all input signals and updates the status as necessary.
< * @return: Returns if the status has changed due to input signals.
< */
< bool checkSignalsAndUpdate(unsigned tid);
---
> void fetch();
242,249c141,142
< /** Does the actual fetching of instructions and passing them on to the
< * next stage.
< * @param status_change fetch() sets this variable if there was a status
< * change (ie switching to IcacheMissStall).
< */
< void fetch(bool &status_change);
<
< /** Align a PC to the start of an I-cache block. */
---
> // Align an address (typically a PC) to the start of an I-cache block.
> // We fold in the PISA 64- to 32-bit conversion here as well.
257,272d149
< /** Returns the appropriate thread to fetch, given the fetch policy. */
< int getFetchingThread(FetchPriority &fetch_priority);
<
< /** Returns the appropriate thread to fetch using a round robin policy. */
< int roundRobin();
<
< /** Returns the appropriate thread to fetch using the IQ count policy. */
< int iqCount();
<
< /** Returns the appropriate thread to fetch using the LSQ count policy. */
< int lsqCount();
<
< /** Returns the appropriate thread to fetch using the branch count policy. */
< int branchCount();
<
< private:
304,307d180
< Addr PC[Impl::MaxThreads];
<
< Addr nextPC[Impl::MaxThreads];
<
309c182
< MemReqPtr memReq[Impl::MaxThreads];
---
> MemReqPtr memReq;
311,329d183
< /** Variable that tracks if fetch has written to the time buffer this
< * cycle. Used to tell CPU if there is activity this cycle.
< */
< bool wroteToTimeBuffer;
<
< /** Tracks how many instructions has been fetched this cycle. */
< int numInst;
<
< /** Source of possible stalls. */
< struct Stalls {
< bool decode;
< bool rename;
< bool iew;
< bool commit;
< };
<
< /** Tracks which stages are telling fetch to stall. */
< Stalls stalls[Impl::MaxThreads];
<
352c206
< uint8_t *cacheData[Impl::MaxThreads];
---
> uint8_t *cacheData;
358c212
< Counter lastIcacheStall[Impl::MaxThreads];
---
> Counter lastIcacheStall;
360,382d213
< /** List of Active Threads */
< std::list<unsigned> *activeThreads;
<
< /** Number of threads. */
< unsigned numThreads;
<
< /** Number of threads that are actively fetching. */
< unsigned numFetchingThreads;
<
< /** Thread ID being fetched. */
< int threadFetched;
<
< bool interruptPending;
<
< bool switchedOut;
<
< #if !FULL_SYSTEM
< /** Page table pointer. */
< // PageTable *pTable;
< #endif
<
< // @todo: Consider making these vectors and tracking on a per thread basis.
< /** Stat for total number of cycles stalled due to an icache miss. */
384d214
< /** Stat for total number of fetched instructions. */
386,387d215
< Stats::Scalar<> fetchedBranches;
< /** Stat for total number of predicted branches. */
389d216
< /** Stat for total number of cycles spent fetching. */
391d217
< /** Stat for total number of cycles spent squashing. */
393,396d218
< /** Stat for total number of cycles spent blocked due to other stages in
< * the pipeline.
< */
< Stats::Scalar<> fetchIdleCycles;
398,400d219
<
< Stats::Scalar<> fetchMiscStallCycles;
< /** Stat for total number of fetched cache lines. */
403,408c222
< Stats::Scalar<> fetchIcacheSquashes;
< /** Distribution of number of instructions fetched each cycle. */
< Stats::Distribution<> fetchNisnDist;
< Stats::Formula idleRate;
< Stats::Formula branchRate;
< Stats::Formula fetchRate;
---
> Stats::Distribution<> fetch_nisn_dist;
411c225
< #endif //__CPU_O3_FETCH_HH__
---
> #endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__