2c2
< * Copyright (c) 2004-2005 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2006 The Regents of The University of Michigan
27,28d26
< *
< * Authors: Kevin Lim
31,32c29,30
< // Todo: SMT fetch,
< // Add a way to get a stage's current status.
---
> #ifndef __CPU_O3_FETCH_HH__
> #define __CPU_O3_FETCH_HH__
34,36c32
< #ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__
< #define __CPU_O3_CPU_SIMPLE_FETCH_HH__
<
---
> #include "arch/utility.hh"
40c36,37
< #include "mem/mem_interface.hh"
---
> #include "mem/packet.hh"
> #include "mem/port.hh"
42a40,41
> class Sampler;
>
44,46c43,48
< * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch
< * will stall if there's an Icache miss, but otherwise assumes a one cycle
< * Icache hit.
---
> * DefaultFetch class handles both single threaded and SMT fetch. Its
> * width is specified by the parameters; each cycle it tries to fetch
> * that many instructions. It supports using a branch predictor to
> * predict direction and targets.
> * It supports the idling functionalitiy of the CPU by indicating to
> * the CPU when it is active and inactive.
48d49
<
50c51
< class SimpleFetch
---
> class DefaultFetch
59a61
> /** Typedefs from the CPU policy. */
65a68
> typedef TheISA::ExtMachInst ExtMachInst;
66a70,95
> class IcachePort : public Port
> {
> protected:
> DefaultFetch<Impl> *fetch;
>
> public:
> IcachePort(DefaultFetch<Impl> *_fetch)
> : Port(_fetch->name() + "-iport"), fetch(_fetch)
> { }
>
> protected:
> virtual Tick recvAtomic(PacketPtr pkt);
>
> virtual void recvFunctional(PacketPtr pkt);
>
> virtual void recvStatusChange(Status status);
>
> virtual void getDeviceAddressRanges(AddrRangeList &resp,
> AddrRangeList &snoop)
> { resp.clear(); snoop.clear(); }
>
> virtual bool recvTiming(PacketPtr pkt);
>
> virtual void recvRetry();
> };
>
68c97,106
< enum Status {
---
> /** Overall fetch status. Used to determine if the CPU can
> * deschedule itsef due to a lack of activity.
> */
> enum FetchStatus {
> Active,
> Inactive
> };
>
> /** Individual thread status. */
> enum ThreadStatus {
73,74c111,117
< IcacheMissStall,
< IcacheMissComplete
---
> Fetching,
> TrapPending,
> QuiescePending,
> SwitchOut,
> IcacheWaitResponse,
> IcacheRetry,
> IcacheAccessComplete
77,78c120,127
< // May eventually need statuses on a per thread basis.
< Status _status;
---
> /** Fetching Policy, Add new policies here.*/
> enum FetchPriority {
> SingleThread,
> RoundRobin,
> Branch,
> IQ,
> LSQ
> };
80c129,131
< bool stalled;
---
> private:
> /** Fetch status. */
> FetchStatus _status;
82,86c133,134
< public:
< class CacheCompletionEvent : public Event
< {
< private:
< SimpleFetch *fetch;
---
> /** Per-thread status. */
> ThreadStatus fetchStatus[Impl::MaxThreads];
88,89c136,137
< public:
< CacheCompletionEvent(SimpleFetch *_fetch);
---
> /** Fetch policy. */
> FetchPriority fetchPolicy;
91,93c139,140
< virtual void process();
< virtual const char *description();
< };
---
> /** List that has the threads organized by priority. */
> std::list<unsigned> priorityList;
96,97c143,144
< /** SimpleFetch constructor. */
< SimpleFetch(Params ¶ms);
---
> /** DefaultFetch constructor. */
> DefaultFetch(Params *params);
98a146,149
> /** Returns the name of fetch. */
> std::string name() const;
>
> /** Registers statistics. */
100a152
> /** Sets CPU pointer. */
102a155
> /** Sets the main backwards communication time buffer pointer. */
104a158,161
> /** Sets pointer to list of active threads. */
> void setActiveThreads(std::list<unsigned> *at_ptr);
>
> /** Sets pointer to time buffer used to communicate to the next stage. */
107c164,165
< void processCacheCompletion();
---
> /** Sets pointer to page table. */
> // void setPageTable(PageTable *pt_ptr);
108a167,182
> /** Initialize stage. */
> void initStage();
>
> /** Processes cache completion event. */
> void processCacheCompletion(PacketPtr pkt);
>
> void switchOut();
>
> void doSwitchOut();
>
> void takeOverFrom();
>
> bool isSwitchedOut() { return switchedOut; }
>
> void wakeFromQuiesce();
>
109a184,193
> /** Changes the status of this stage to active, and indicates this
> * to the CPU.
> */
> inline void switchToActive();
>
> /** Changes the status of this stage to inactive, and indicates
> * this to the CPU.
> */
> inline void switchToInactive();
>
124a209,211
> * @param ret_fault The fault reference that will be set to the result of
> * the icache access.
> * @param tid Thread id.
127c214
< Fault fetchCacheLine(Addr fetch_PC);
---
> bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
129c216,217
< inline void doSquash(const Addr &new_PC);
---
> /** Squashes a specific thread and resets the PC. */
> inline void doSquash(const Addr &new_PC, unsigned tid);
131c219,223
< void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num);
---
> /** Squashes a specific thread and resets the PC. Also tells the CPU to
> * remove any instructions between fetch and decode that should be sqaushed.
> */
> void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
> unsigned tid);
132a225,231
> /** Checks if a thread is stalled. */
> bool checkStall(unsigned tid) const;
>
> /** Updates overall fetch stage status; to be called at the end of each
> * cycle. */
> FetchStatus updateFetchStatus();
>
134,135c233,237
< // Figure out PC vs next PC and how it should be updated
< void squash(const Addr &new_PC);
---
> /** Squashes a specific thread and resets the PC. Also tells the CPU to
> * remove any instructions that are not in the ROB. The source of this
> * squash should be the commit stage.
> */
> void squash(const Addr &new_PC, unsigned tid);
136a239,241
> /** Ticks the fetch stage, processing all inputs signals and fetching
> * as many instructions as possible.
> */
139c244,247
< void fetch();
---
> /** Checks all input signals and updates the status as necessary.
> * @return: Returns if the status has changed due to input signals.
> */
> bool checkSignalsAndUpdate(unsigned tid);
141,142c249,256
< // Align an address (typically a PC) to the start of an I-cache block.
< // We fold in the PISA 64- to 32-bit conversion here as well.
---
> /** Does the actual fetching of instructions and passing them on to the
> * next stage.
> * @param status_change fetch() sets this variable if there was a status
> * change (ie switching to IcacheMissStall).
> */
> void fetch(bool &status_change);
>
> /** Align a PC to the start of an I-cache block. */
149a264,279
> /** Returns the appropriate thread to fetch, given the fetch policy. */
> int getFetchingThread(FetchPriority &fetch_priority);
>
> /** Returns the appropriate thread to fetch using a round robin policy. */
> int roundRobin();
>
> /** Returns the appropriate thread to fetch using the IQ count policy. */
> int iqCount();
>
> /** Returns the appropriate thread to fetch using the LSQ count policy. */
> int lsqCount();
>
> /** Returns the appropriate thread to fetch using the branch count policy. */
> int branchCount();
>
> private:
174a305,306
> MemObject *mem;
>
176c308
< MemInterface *icacheInterface;
---
> IcachePort *icachePort;
181,182c313
< /** Memory request used to access cache. */
< MemReqPtr memReq;
---
> Addr PC[Impl::MaxThreads];
183a315,338
> Addr nextPC[Impl::MaxThreads];
>
> /** Memory packet used to access cache. */
> PacketPtr memPkt[Impl::MaxThreads];
>
> /** Variable that tracks if fetch has written to the time buffer this
> * cycle. Used to tell CPU if there is activity this cycle.
> */
> bool wroteToTimeBuffer;
>
> /** Tracks how many instructions has been fetched this cycle. */
> int numInst;
>
> /** Source of possible stalls. */
> struct Stalls {
> bool decode;
> bool rename;
> bool iew;
> bool commit;
> };
>
> /** Tracks which stages are telling fetch to stall. */
> Stalls stalls[Impl::MaxThreads];
>
206c361
< uint8_t *cacheData;
---
> uint8_t *cacheData[Impl::MaxThreads];
212c367
< Counter lastIcacheStall;
---
> Counter lastIcacheStall[Impl::MaxThreads];
213a369,391
> /** List of Active Threads */
> std::list<unsigned> *activeThreads;
>
> /** Number of threads. */
> unsigned numThreads;
>
> /** Number of threads that are actively fetching. */
> unsigned numFetchingThreads;
>
> /** Thread ID being fetched. */
> int threadFetched;
>
> bool interruptPending;
>
> bool switchedOut;
>
> #if !FULL_SYSTEM
> /** Page table pointer. */
> // PageTable *pTable;
> #endif
>
> // @todo: Consider making these vectors and tracking on a per thread basis.
> /** Stat for total number of cycles stalled due to an icache miss. */
214a393
> /** Stat for total number of fetched instructions. */
215a395,396
> Stats::Scalar<> fetchedBranches;
> /** Stat for total number of predicted branches. */
216a398
> /** Stat for total number of cycles spent fetching. */
217a400
> /** Stat for total number of cycles spent squashing. */
218a402,405
> /** Stat for total number of cycles spent blocked due to other stages in
> * the pipeline.
> */
> Stats::Scalar<> fetchIdleCycles;
219a407,409
>
> Stats::Scalar<> fetchMiscStallCycles;
> /** Stat for total number of fetched cache lines. */
222c412,417
< Stats::Distribution<> fetch_nisn_dist;
---
> Stats::Scalar<> fetchIcacheSquashes;
> /** Distribution of number of instructions fetched each cycle. */
> Stats::Distribution<> fetchNisnDist;
> Stats::Formula idleRate;
> Stats::Formula branchRate;
> Stats::Formula fetchRate;
225c420
< #endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__
---
> #endif //__CPU_O3_FETCH_HH__
< * Copyright (c) 2004-2005 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2006 The Regents of The University of Michigan
27,28d26
< *
< * Authors: Kevin Lim
31,32c29,30
< // Todo: SMT fetch,
< // Add a way to get a stage's current status.
---
> #ifndef __CPU_O3_FETCH_HH__
> #define __CPU_O3_FETCH_HH__
34,36c32
< #ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__
< #define __CPU_O3_CPU_SIMPLE_FETCH_HH__
<
---
> #include "arch/utility.hh"
40c36,37
< #include "mem/mem_interface.hh"
---
> #include "mem/packet.hh"
> #include "mem/port.hh"
42a40,41
> class Sampler;
>
44,46c43,48
< * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch
< * will stall if there's an Icache miss, but otherwise assumes a one cycle
< * Icache hit.
---
> * DefaultFetch class handles both single threaded and SMT fetch. Its
> * width is specified by the parameters; each cycle it tries to fetch
> * that many instructions. It supports using a branch predictor to
> * predict direction and targets.
> * It supports the idling functionalitiy of the CPU by indicating to
> * the CPU when it is active and inactive.
48d49
<
50c51
< class SimpleFetch
---
> class DefaultFetch
59a61
> /** Typedefs from the CPU policy. */
65a68
> typedef TheISA::ExtMachInst ExtMachInst;
66a70,95
> class IcachePort : public Port
> {
> protected:
> DefaultFetch<Impl> *fetch;
>
> public:
> IcachePort(DefaultFetch<Impl> *_fetch)
> : Port(_fetch->name() + "-iport"), fetch(_fetch)
> { }
>
> protected:
> virtual Tick recvAtomic(PacketPtr pkt);
>
> virtual void recvFunctional(PacketPtr pkt);
>
> virtual void recvStatusChange(Status status);
>
> virtual void getDeviceAddressRanges(AddrRangeList &resp,
> AddrRangeList &snoop)
> { resp.clear(); snoop.clear(); }
>
> virtual bool recvTiming(PacketPtr pkt);
>
> virtual void recvRetry();
> };
>
68c97,106
< enum Status {
---
> /** Overall fetch status. Used to determine if the CPU can
> * deschedule itsef due to a lack of activity.
> */
> enum FetchStatus {
> Active,
> Inactive
> };
>
> /** Individual thread status. */
> enum ThreadStatus {
73,74c111,117
< IcacheMissStall,
< IcacheMissComplete
---
> Fetching,
> TrapPending,
> QuiescePending,
> SwitchOut,
> IcacheWaitResponse,
> IcacheRetry,
> IcacheAccessComplete
77,78c120,127
< // May eventually need statuses on a per thread basis.
< Status _status;
---
> /** Fetching Policy, Add new policies here.*/
> enum FetchPriority {
> SingleThread,
> RoundRobin,
> Branch,
> IQ,
> LSQ
> };
80c129,131
< bool stalled;
---
> private:
> /** Fetch status. */
> FetchStatus _status;
82,86c133,134
< public:
< class CacheCompletionEvent : public Event
< {
< private:
< SimpleFetch *fetch;
---
> /** Per-thread status. */
> ThreadStatus fetchStatus[Impl::MaxThreads];
88,89c136,137
< public:
< CacheCompletionEvent(SimpleFetch *_fetch);
---
> /** Fetch policy. */
> FetchPriority fetchPolicy;
91,93c139,140
< virtual void process();
< virtual const char *description();
< };
---
> /** List that has the threads organized by priority. */
> std::list<unsigned> priorityList;
96,97c143,144
< /** SimpleFetch constructor. */
< SimpleFetch(Params ¶ms);
---
> /** DefaultFetch constructor. */
> DefaultFetch(Params *params);
98a146,149
> /** Returns the name of fetch. */
> std::string name() const;
>
> /** Registers statistics. */
100a152
> /** Sets CPU pointer. */
102a155
> /** Sets the main backwards communication time buffer pointer. */
104a158,161
> /** Sets pointer to list of active threads. */
> void setActiveThreads(std::list<unsigned> *at_ptr);
>
> /** Sets pointer to time buffer used to communicate to the next stage. */
107c164,165
< void processCacheCompletion();
---
> /** Sets pointer to page table. */
> // void setPageTable(PageTable *pt_ptr);
108a167,182
> /** Initialize stage. */
> void initStage();
>
> /** Processes cache completion event. */
> void processCacheCompletion(PacketPtr pkt);
>
> void switchOut();
>
> void doSwitchOut();
>
> void takeOverFrom();
>
> bool isSwitchedOut() { return switchedOut; }
>
> void wakeFromQuiesce();
>
109a184,193
> /** Changes the status of this stage to active, and indicates this
> * to the CPU.
> */
> inline void switchToActive();
>
> /** Changes the status of this stage to inactive, and indicates
> * this to the CPU.
> */
> inline void switchToInactive();
>
124a209,211
> * @param ret_fault The fault reference that will be set to the result of
> * the icache access.
> * @param tid Thread id.
127c214
< Fault fetchCacheLine(Addr fetch_PC);
---
> bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
129c216,217
< inline void doSquash(const Addr &new_PC);
---
> /** Squashes a specific thread and resets the PC. */
> inline void doSquash(const Addr &new_PC, unsigned tid);
131c219,223
< void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num);
---
> /** Squashes a specific thread and resets the PC. Also tells the CPU to
> * remove any instructions between fetch and decode that should be sqaushed.
> */
> void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
> unsigned tid);
132a225,231
> /** Checks if a thread is stalled. */
> bool checkStall(unsigned tid) const;
>
> /** Updates overall fetch stage status; to be called at the end of each
> * cycle. */
> FetchStatus updateFetchStatus();
>
134,135c233,237
< // Figure out PC vs next PC and how it should be updated
< void squash(const Addr &new_PC);
---
> /** Squashes a specific thread and resets the PC. Also tells the CPU to
> * remove any instructions that are not in the ROB. The source of this
> * squash should be the commit stage.
> */
> void squash(const Addr &new_PC, unsigned tid);
136a239,241
> /** Ticks the fetch stage, processing all inputs signals and fetching
> * as many instructions as possible.
> */
139c244,247
< void fetch();
---
> /** Checks all input signals and updates the status as necessary.
> * @return: Returns if the status has changed due to input signals.
> */
> bool checkSignalsAndUpdate(unsigned tid);
141,142c249,256
< // Align an address (typically a PC) to the start of an I-cache block.
< // We fold in the PISA 64- to 32-bit conversion here as well.
---
> /** Does the actual fetching of instructions and passing them on to the
> * next stage.
> * @param status_change fetch() sets this variable if there was a status
> * change (ie switching to IcacheMissStall).
> */
> void fetch(bool &status_change);
>
> /** Align a PC to the start of an I-cache block. */
149a264,279
> /** Returns the appropriate thread to fetch, given the fetch policy. */
> int getFetchingThread(FetchPriority &fetch_priority);
>
> /** Returns the appropriate thread to fetch using a round robin policy. */
> int roundRobin();
>
> /** Returns the appropriate thread to fetch using the IQ count policy. */
> int iqCount();
>
> /** Returns the appropriate thread to fetch using the LSQ count policy. */
> int lsqCount();
>
> /** Returns the appropriate thread to fetch using the branch count policy. */
> int branchCount();
>
> private:
174a305,306
> MemObject *mem;
>
176c308
< MemInterface *icacheInterface;
---
> IcachePort *icachePort;
181,182c313
< /** Memory request used to access cache. */
< MemReqPtr memReq;
---
> Addr PC[Impl::MaxThreads];
183a315,338
> Addr nextPC[Impl::MaxThreads];
>
> /** Memory packet used to access cache. */
> PacketPtr memPkt[Impl::MaxThreads];
>
> /** Variable that tracks if fetch has written to the time buffer this
> * cycle. Used to tell CPU if there is activity this cycle.
> */
> bool wroteToTimeBuffer;
>
> /** Tracks how many instructions has been fetched this cycle. */
> int numInst;
>
> /** Source of possible stalls. */
> struct Stalls {
> bool decode;
> bool rename;
> bool iew;
> bool commit;
> };
>
> /** Tracks which stages are telling fetch to stall. */
> Stalls stalls[Impl::MaxThreads];
>
206c361
< uint8_t *cacheData;
---
> uint8_t *cacheData[Impl::MaxThreads];
212c367
< Counter lastIcacheStall;
---
> Counter lastIcacheStall[Impl::MaxThreads];
213a369,391
> /** List of Active Threads */
> std::list<unsigned> *activeThreads;
>
> /** Number of threads. */
> unsigned numThreads;
>
> /** Number of threads that are actively fetching. */
> unsigned numFetchingThreads;
>
> /** Thread ID being fetched. */
> int threadFetched;
>
> bool interruptPending;
>
> bool switchedOut;
>
> #if !FULL_SYSTEM
> /** Page table pointer. */
> // PageTable *pTable;
> #endif
>
> // @todo: Consider making these vectors and tracking on a per thread basis.
> /** Stat for total number of cycles stalled due to an icache miss. */
214a393
> /** Stat for total number of fetched instructions. */
215a395,396
> Stats::Scalar<> fetchedBranches;
> /** Stat for total number of predicted branches. */
216a398
> /** Stat for total number of cycles spent fetching. */
217a400
> /** Stat for total number of cycles spent squashing. */
218a402,405
> /** Stat for total number of cycles spent blocked due to other stages in
> * the pipeline.
> */
> Stats::Scalar<> fetchIdleCycles;
219a407,409
>
> Stats::Scalar<> fetchMiscStallCycles;
> /** Stat for total number of fetched cache lines. */
222c412,417
< Stats::Distribution<> fetch_nisn_dist;
---
> Stats::Scalar<> fetchIcacheSquashes;
> /** Distribution of number of instructions fetched each cycle. */
> Stats::Distribution<> fetchNisnDist;
> Stats::Formula idleRate;
> Stats::Formula branchRate;
> Stats::Formula fetchRate;
225c420
< #endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__
---
> #endif //__CPU_O3_FETCH_HH__