1/*
| 1/*
|
2 * Copyright (c) 2010 ARM Limited
| 2 * Copyright (c) 2010-2011 ARM Limited
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/predecoder.hh"
48#include "arch/utility.hh"
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/decode.hh"
52#include "cpu/pc_event.hh"
53#include "cpu/timebuf.hh"
54#include "cpu/translation.hh"
55#include "mem/packet.hh"
56#include "mem/port.hh"
57#include "sim/eventq.hh"
58
59class DerivO3CPUParams;
60
61/**
62 * DefaultFetch class handles both single threaded and SMT fetch. Its
63 * width is specified by the parameters; each cycle it tries to fetch
64 * that many instructions. It supports using a branch predictor to
65 * predict direction and targets.
66 * It supports the idling functionality of the CPU by indicating to
67 * the CPU when it is active and inactive.
68 */
69template <class Impl>
70class DefaultFetch
71{
72 public:
73 /** Typedefs from Impl. */
74 typedef typename Impl::CPUPol CPUPol;
75 typedef typename Impl::DynInst DynInst;
76 typedef typename Impl::DynInstPtr DynInstPtr;
77 typedef typename Impl::O3CPU O3CPU;
78
79 /** Typedefs from the CPU policy. */
80 typedef typename CPUPol::BPredUnit BPredUnit;
81 typedef typename CPUPol::FetchStruct FetchStruct;
82 typedef typename CPUPol::TimeStruct TimeStruct;
83
84 /** Typedefs from ISA. */
85 typedef TheISA::MachInst MachInst;
86 typedef TheISA::ExtMachInst ExtMachInst;
87
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/predecoder.hh"
48#include "arch/utility.hh"
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/decode.hh"
52#include "cpu/pc_event.hh"
53#include "cpu/timebuf.hh"
54#include "cpu/translation.hh"
55#include "mem/packet.hh"
56#include "mem/port.hh"
57#include "sim/eventq.hh"
58
59class DerivO3CPUParams;
60
61/**
62 * DefaultFetch class handles both single threaded and SMT fetch. Its
63 * width is specified by the parameters; each cycle it tries to fetch
64 * that many instructions. It supports using a branch predictor to
65 * predict direction and targets.
66 * It supports the idling functionality of the CPU by indicating to
67 * the CPU when it is active and inactive.
68 */
69template <class Impl>
70class DefaultFetch
71{
72 public:
73 /** Typedefs from Impl. */
74 typedef typename Impl::CPUPol CPUPol;
75 typedef typename Impl::DynInst DynInst;
76 typedef typename Impl::DynInstPtr DynInstPtr;
77 typedef typename Impl::O3CPU O3CPU;
78
79 /** Typedefs from the CPU policy. */
80 typedef typename CPUPol::BPredUnit BPredUnit;
81 typedef typename CPUPol::FetchStruct FetchStruct;
82 typedef typename CPUPol::TimeStruct TimeStruct;
83
84 /** Typedefs from ISA. */
85 typedef TheISA::MachInst MachInst;
86 typedef TheISA::ExtMachInst ExtMachInst;
87
|
88 /** IcachePort class for DefaultFetch. Handles doing the
89 * communication with the cache/memory.
90 */
91 class IcachePort : public Port
92 {
93 protected:
94 /** Pointer to fetch. */
95 DefaultFetch<Impl> *fetch;
96
97 public:
98 /** Default constructor. */
99 IcachePort(DefaultFetch<Impl> *_fetch)
100 : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch)
101 { }
102
103 bool snoopRangeSent;
104
105 virtual void setPeer(Port *port);
106
107 protected:
108 /** Atomic version of receive. Panics. */
109 virtual Tick recvAtomic(PacketPtr pkt);
110
111 /** Functional version of receive. Panics. */
112 virtual void recvFunctional(PacketPtr pkt);
113
114 /** Receives status change. Other than range changing, panics. */
115 virtual void recvStatusChange(Status status);
116
117 /** Returns the address ranges of this device. */
118 virtual void getDeviceAddressRanges(AddrRangeList &resp,
119 bool &snoop)
120 { resp.clear(); snoop = true; }
121
122 /** Timing version of receive. Handles setting fetch to the
123 * proper status to start fetching. */
124 virtual bool recvTiming(PacketPtr pkt);
125
126 /** Handles doing a retry of a failed fetch. */
127 virtual void recvRetry();
128 };
129
| |
130 class FetchTranslation : public BaseTLB::Translation
131 {
132 protected:
133 DefaultFetch<Impl> *fetch;
134
135 public:
136 FetchTranslation(DefaultFetch<Impl> *_fetch)
137 : fetch(_fetch)
138 {}
139
140 void
141 markDelayed()
142 {}
143
144 void
145 finish(Fault fault, RequestPtr req, ThreadContext *tc,
146 BaseTLB::Mode mode)
147 {
148 assert(mode == BaseTLB::Execute);
149 fetch->finishTranslation(fault, req);
150 delete this;
151 }
152 };
153
154 private:
155 /* Event to delay delivery of a fetch translation result in case of
156 * a fault and the nop to carry the fault cannot be generated
157 * immediately */
158 class FinishTranslationEvent : public Event
159 {
160 private:
161 DefaultFetch<Impl> *fetch;
162 Fault fault;
163 RequestPtr req;
164
165 public:
166 FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
167 : fetch(_fetch)
168 {}
169
170 void setFault(Fault _fault)
171 {
172 fault = _fault;
173 }
174
175 void setReq(RequestPtr _req)
176 {
177 req = _req;
178 }
179
180 /** Process the delayed finish translation */
181 void process()
182 {
183 assert(fetch->numInst < fetch->fetchWidth);
184 fetch->finishTranslation(fault, req);
185 }
186
187 const char *description() const
188 {
189 return "FullO3CPU FetchFinishTranslation";
190 }
191 };
192
193 public:
194 /** Overall fetch status. Used to determine if the CPU can
195 * deschedule itsef due to a lack of activity.
196 */
197 enum FetchStatus {
198 Active,
199 Inactive
200 };
201
202 /** Individual thread status. */
203 enum ThreadStatus {
204 Running,
205 Idle,
206 Squashing,
207 Blocked,
208 Fetching,
209 TrapPending,
210 QuiescePending,
211 SwitchOut,
212 ItlbWait,
213 IcacheWaitResponse,
214 IcacheWaitRetry,
215 IcacheAccessComplete,
216 NoGoodAddr
217 };
218
219 /** Fetching Policy, Add new policies here.*/
220 enum FetchPriority {
221 SingleThread,
222 RoundRobin,
223 Branch,
224 IQ,
225 LSQ
226 };
227
228 private:
229 /** Fetch status. */
230 FetchStatus _status;
231
232 /** Per-thread status. */
233 ThreadStatus fetchStatus[Impl::MaxThreads];
234
235 /** Fetch policy. */
236 FetchPriority fetchPolicy;
237
238 /** List that has the threads organized by priority. */
239 std::list<ThreadID> priorityList;
240
241 public:
242 /** DefaultFetch constructor. */
243 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
244
245 /** Returns the name of fetch. */
246 std::string name() const;
247
248 /** Registers statistics. */
249 void regStats();
250
| 88 class FetchTranslation : public BaseTLB::Translation
89 {
90 protected:
91 DefaultFetch<Impl> *fetch;
92
93 public:
94 FetchTranslation(DefaultFetch<Impl> *_fetch)
95 : fetch(_fetch)
96 {}
97
98 void
99 markDelayed()
100 {}
101
102 void
103 finish(Fault fault, RequestPtr req, ThreadContext *tc,
104 BaseTLB::Mode mode)
105 {
106 assert(mode == BaseTLB::Execute);
107 fetch->finishTranslation(fault, req);
108 delete this;
109 }
110 };
111
112 private:
113 /* Event to delay delivery of a fetch translation result in case of
114 * a fault and the nop to carry the fault cannot be generated
115 * immediately */
116 class FinishTranslationEvent : public Event
117 {
118 private:
119 DefaultFetch<Impl> *fetch;
120 Fault fault;
121 RequestPtr req;
122
123 public:
124 FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
125 : fetch(_fetch)
126 {}
127
128 void setFault(Fault _fault)
129 {
130 fault = _fault;
131 }
132
133 void setReq(RequestPtr _req)
134 {
135 req = _req;
136 }
137
138 /** Process the delayed finish translation */
139 void process()
140 {
141 assert(fetch->numInst < fetch->fetchWidth);
142 fetch->finishTranslation(fault, req);
143 }
144
145 const char *description() const
146 {
147 return "FullO3CPU FetchFinishTranslation";
148 }
149 };
150
151 public:
152 /** Overall fetch status. Used to determine if the CPU can
153 * deschedule itsef due to a lack of activity.
154 */
155 enum FetchStatus {
156 Active,
157 Inactive
158 };
159
160 /** Individual thread status. */
161 enum ThreadStatus {
162 Running,
163 Idle,
164 Squashing,
165 Blocked,
166 Fetching,
167 TrapPending,
168 QuiescePending,
169 SwitchOut,
170 ItlbWait,
171 IcacheWaitResponse,
172 IcacheWaitRetry,
173 IcacheAccessComplete,
174 NoGoodAddr
175 };
176
177 /** Fetching Policy, Add new policies here.*/
178 enum FetchPriority {
179 SingleThread,
180 RoundRobin,
181 Branch,
182 IQ,
183 LSQ
184 };
185
186 private:
187 /** Fetch status. */
188 FetchStatus _status;
189
190 /** Per-thread status. */
191 ThreadStatus fetchStatus[Impl::MaxThreads];
192
193 /** Fetch policy. */
194 FetchPriority fetchPolicy;
195
196 /** List that has the threads organized by priority. */
197 std::list<ThreadID> priorityList;
198
199 public:
200 /** DefaultFetch constructor. */
201 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
202
203 /** Returns the name of fetch. */
204 std::string name() const;
205
206 /** Registers statistics. */
207 void regStats();
208
|
251 /** Returns the icache port. */
252 Port *getIcachePort() { return icachePort; }
253
| |
254 /** Sets the main backwards communication time buffer pointer. */
255 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
256
257 /** Sets pointer to list of active threads. */
258 void setActiveThreads(std::list<ThreadID> *at_ptr);
259
260 /** Sets pointer to time buffer used to communicate to the next stage. */
261 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
262
263 /** Initialize stage. */
264 void initStage();
265
266 /** Tells the fetch stage that the Icache is set. */
267 void setIcache();
268
| 209 /** Sets the main backwards communication time buffer pointer. */
210 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
211
212 /** Sets pointer to list of active threads. */
213 void setActiveThreads(std::list<ThreadID> *at_ptr);
214
215 /** Sets pointer to time buffer used to communicate to the next stage. */
216 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
217
218 /** Initialize stage. */
219 void initStage();
220
221 /** Tells the fetch stage that the Icache is set. */
222 void setIcache();
223
|
| 224 /** Handles retrying the fetch access. */
225 void recvRetry();
226
|
269 /** Processes cache completion event. */
270 void processCacheCompletion(PacketPtr pkt);
271
272 /** Begins the drain of the fetch stage. */
273 bool drain();
274
275 /** Resumes execution after a drain. */
276 void resume();
277
278 /** Tells fetch stage to prepare to be switched out. */
279 void switchOut();
280
281 /** Takes over from another CPU's thread. */
282 void takeOverFrom();
283
284 /** Checks if the fetch stage is switched out. */
285 bool isSwitchedOut() { return switchedOut; }
286
287 /** Tells fetch to wake up from a quiesce instruction. */
288 void wakeFromQuiesce();
289
290 private:
291 /** Changes the status of this stage to active, and indicates this
292 * to the CPU.
293 */
294 inline void switchToActive();
295
296 /** Changes the status of this stage to inactive, and indicates
297 * this to the CPU.
298 */
299 inline void switchToInactive();
300
301 /**
302 * Looks up in the branch predictor to see if the next PC should be
303 * either next PC+=MachInst or a branch target.
304 * @param next_PC Next PC variable passed in by reference. It is
305 * expected to be set to the current PC; it will be updated with what
306 * the next PC will be.
307 * @param next_NPC Used for ISAs which use delay slots.
308 * @return Whether or not a branch was predicted as taken.
309 */
310 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
311
312 /**
313 * Fetches the cache line that contains fetch_PC. Returns any
314 * fault that happened. Puts the data into the class variable
315 * cacheData.
316 * @param vaddr The memory address that is being fetched from.
317 * @param ret_fault The fault reference that will be set to the result of
318 * the icache access.
319 * @param tid Thread id.
320 * @param pc The actual PC of the current instruction.
321 * @return Any fault that occured.
322 */
323 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
324 void finishTranslation(Fault fault, RequestPtr mem_req);
325
326
327 /** Check if an interrupt is pending and that we need to handle
328 */
329 bool
330 checkInterrupt(Addr pc)
331 {
332 return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
333 }
334
335 /** Squashes a specific thread and resets the PC. */
336 inline void doSquash(const TheISA::PCState &newPC,
337 const DynInstPtr squashInst, ThreadID tid);
338
339 /** Squashes a specific thread and resets the PC. Also tells the CPU to
340 * remove any instructions between fetch and decode that should be sqaushed.
341 */
342 void squashFromDecode(const TheISA::PCState &newPC,
343 const DynInstPtr squashInst,
344 const InstSeqNum seq_num, ThreadID tid);
345
346 /** Checks if a thread is stalled. */
347 bool checkStall(ThreadID tid) const;
348
349 /** Updates overall fetch stage status; to be called at the end of each
350 * cycle. */
351 FetchStatus updateFetchStatus();
352
353 public:
354 /** Squashes a specific thread and resets the PC. Also tells the CPU to
355 * remove any instructions that are not in the ROB. The source of this
356 * squash should be the commit stage.
357 */
358 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
359 DynInstPtr squashInst, ThreadID tid);
360
361 /** Ticks the fetch stage, processing all inputs signals and fetching
362 * as many instructions as possible.
363 */
364 void tick();
365
366 /** Checks all input signals and updates the status as necessary.
367 * @return: Returns if the status has changed due to input signals.
368 */
369 bool checkSignalsAndUpdate(ThreadID tid);
370
371 /** Does the actual fetching of instructions and passing them on to the
372 * next stage.
373 * @param status_change fetch() sets this variable if there was a status
374 * change (ie switching to IcacheMissStall).
375 */
376 void fetch(bool &status_change);
377
378 /** Align a PC to the start of an I-cache block. */
379 Addr icacheBlockAlignPC(Addr addr)
380 {
381 return (addr & ~(cacheBlkMask));
382 }
383
384 /** The decoder. */
385 Decoder decoder;
386
387 private:
388 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
389 StaticInstPtr curMacroop, TheISA::PCState thisPC,
390 TheISA::PCState nextPC, bool trace);
391
| 227 /** Processes cache completion event. */
228 void processCacheCompletion(PacketPtr pkt);
229
230 /** Begins the drain of the fetch stage. */
231 bool drain();
232
233 /** Resumes execution after a drain. */
234 void resume();
235
236 /** Tells fetch stage to prepare to be switched out. */
237 void switchOut();
238
239 /** Takes over from another CPU's thread. */
240 void takeOverFrom();
241
242 /** Checks if the fetch stage is switched out. */
243 bool isSwitchedOut() { return switchedOut; }
244
245 /** Tells fetch to wake up from a quiesce instruction. */
246 void wakeFromQuiesce();
247
248 private:
249 /** Changes the status of this stage to active, and indicates this
250 * to the CPU.
251 */
252 inline void switchToActive();
253
254 /** Changes the status of this stage to inactive, and indicates
255 * this to the CPU.
256 */
257 inline void switchToInactive();
258
259 /**
260 * Looks up in the branch predictor to see if the next PC should be
261 * either next PC+=MachInst or a branch target.
262 * @param next_PC Next PC variable passed in by reference. It is
263 * expected to be set to the current PC; it will be updated with what
264 * the next PC will be.
265 * @param next_NPC Used for ISAs which use delay slots.
266 * @return Whether or not a branch was predicted as taken.
267 */
268 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
269
270 /**
271 * Fetches the cache line that contains fetch_PC. Returns any
272 * fault that happened. Puts the data into the class variable
273 * cacheData.
274 * @param vaddr The memory address that is being fetched from.
275 * @param ret_fault The fault reference that will be set to the result of
276 * the icache access.
277 * @param tid Thread id.
278 * @param pc The actual PC of the current instruction.
279 * @return Any fault that occured.
280 */
281 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
282 void finishTranslation(Fault fault, RequestPtr mem_req);
283
284
285 /** Check if an interrupt is pending and that we need to handle
286 */
287 bool
288 checkInterrupt(Addr pc)
289 {
290 return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
291 }
292
293 /** Squashes a specific thread and resets the PC. */
294 inline void doSquash(const TheISA::PCState &newPC,
295 const DynInstPtr squashInst, ThreadID tid);
296
297 /** Squashes a specific thread and resets the PC. Also tells the CPU to
298 * remove any instructions between fetch and decode that should be sqaushed.
299 */
300 void squashFromDecode(const TheISA::PCState &newPC,
301 const DynInstPtr squashInst,
302 const InstSeqNum seq_num, ThreadID tid);
303
304 /** Checks if a thread is stalled. */
305 bool checkStall(ThreadID tid) const;
306
307 /** Updates overall fetch stage status; to be called at the end of each
308 * cycle. */
309 FetchStatus updateFetchStatus();
310
311 public:
312 /** Squashes a specific thread and resets the PC. Also tells the CPU to
313 * remove any instructions that are not in the ROB. The source of this
314 * squash should be the commit stage.
315 */
316 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
317 DynInstPtr squashInst, ThreadID tid);
318
319 /** Ticks the fetch stage, processing all inputs signals and fetching
320 * as many instructions as possible.
321 */
322 void tick();
323
324 /** Checks all input signals and updates the status as necessary.
325 * @return: Returns if the status has changed due to input signals.
326 */
327 bool checkSignalsAndUpdate(ThreadID tid);
328
329 /** Does the actual fetching of instructions and passing them on to the
330 * next stage.
331 * @param status_change fetch() sets this variable if there was a status
332 * change (ie switching to IcacheMissStall).
333 */
334 void fetch(bool &status_change);
335
336 /** Align a PC to the start of an I-cache block. */
337 Addr icacheBlockAlignPC(Addr addr)
338 {
339 return (addr & ~(cacheBlkMask));
340 }
341
342 /** The decoder. */
343 Decoder decoder;
344
345 private:
346 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
347 StaticInstPtr curMacroop, TheISA::PCState thisPC,
348 TheISA::PCState nextPC, bool trace);
349
|
392 /** Handles retrying the fetch access. */
393 void recvRetry();
394
| |
395 /** Returns the appropriate thread to fetch, given the fetch policy. */
396 ThreadID getFetchingThread(FetchPriority &fetch_priority);
397
398 /** Returns the appropriate thread to fetch using a round robin policy. */
399 ThreadID roundRobin();
400
401 /** Returns the appropriate thread to fetch using the IQ count policy. */
402 ThreadID iqCount();
403
404 /** Returns the appropriate thread to fetch using the LSQ count policy. */
405 ThreadID lsqCount();
406
407 /** Returns the appropriate thread to fetch using the branch count
408 * policy. */
409 ThreadID branchCount();
410
411 /** Pipeline the next I-cache access to the current one. */
412 void pipelineIcacheAccesses(ThreadID tid);
413
414 /** Profile the reasons of fetch stall. */
415 void profileStall(ThreadID tid);
416
417 private:
418 /** Pointer to the O3CPU. */
419 O3CPU *cpu;
420
421 /** Time buffer interface. */
422 TimeBuffer<TimeStruct> *timeBuffer;
423
424 /** Wire to get decode's information from backwards time buffer. */
425 typename TimeBuffer<TimeStruct>::wire fromDecode;
426
427 /** Wire to get rename's information from backwards time buffer. */
428 typename TimeBuffer<TimeStruct>::wire fromRename;
429
430 /** Wire to get iew's information from backwards time buffer. */
431 typename TimeBuffer<TimeStruct>::wire fromIEW;
432
433 /** Wire to get commit's information from backwards time buffer. */
434 typename TimeBuffer<TimeStruct>::wire fromCommit;
435
436 /** Internal fetch instruction queue. */
437 TimeBuffer<FetchStruct> *fetchQueue;
438
439 //Might be annoying how this name is different than the queue.
440 /** Wire used to write any information heading to decode. */
441 typename TimeBuffer<FetchStruct>::wire toDecode;
442
| 350 /** Returns the appropriate thread to fetch, given the fetch policy. */
351 ThreadID getFetchingThread(FetchPriority &fetch_priority);
352
353 /** Returns the appropriate thread to fetch using a round robin policy. */
354 ThreadID roundRobin();
355
356 /** Returns the appropriate thread to fetch using the IQ count policy. */
357 ThreadID iqCount();
358
359 /** Returns the appropriate thread to fetch using the LSQ count policy. */
360 ThreadID lsqCount();
361
362 /** Returns the appropriate thread to fetch using the branch count
363 * policy. */
364 ThreadID branchCount();
365
366 /** Pipeline the next I-cache access to the current one. */
367 void pipelineIcacheAccesses(ThreadID tid);
368
369 /** Profile the reasons of fetch stall. */
370 void profileStall(ThreadID tid);
371
372 private:
373 /** Pointer to the O3CPU. */
374 O3CPU *cpu;
375
376 /** Time buffer interface. */
377 TimeBuffer<TimeStruct> *timeBuffer;
378
379 /** Wire to get decode's information from backwards time buffer. */
380 typename TimeBuffer<TimeStruct>::wire fromDecode;
381
382 /** Wire to get rename's information from backwards time buffer. */
383 typename TimeBuffer<TimeStruct>::wire fromRename;
384
385 /** Wire to get iew's information from backwards time buffer. */
386 typename TimeBuffer<TimeStruct>::wire fromIEW;
387
388 /** Wire to get commit's information from backwards time buffer. */
389 typename TimeBuffer<TimeStruct>::wire fromCommit;
390
391 /** Internal fetch instruction queue. */
392 TimeBuffer<FetchStruct> *fetchQueue;
393
394 //Might be annoying how this name is different than the queue.
395 /** Wire used to write any information heading to decode. */
396 typename TimeBuffer<FetchStruct>::wire toDecode;
397
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443 /** Icache interface. */
444 IcachePort *icachePort;
445
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446 /** BPredUnit. */
447 BPredUnit branchPred;
448
449 /** Predecoder. */
450 TheISA::Predecoder predecoder;
451
452 TheISA::PCState pc[Impl::MaxThreads];
453
454 Addr fetchOffset[Impl::MaxThreads];
455
456 StaticInstPtr macroop[Impl::MaxThreads];
457
458 /** Can the fetch stage redirect from an interrupt on this instruction? */
459 bool delayedCommit[Impl::MaxThreads];
460
461 /** Memory request used to access cache. */
462 RequestPtr memReq[Impl::MaxThreads];
463
464 /** Variable that tracks if fetch has written to the time buffer this
465 * cycle. Used to tell CPU if there is activity this cycle.
466 */
467 bool wroteToTimeBuffer;
468
469 /** Tracks how many instructions has been fetched this cycle. */
470 int numInst;
471
472 /** Source of possible stalls. */
473 struct Stalls {
474 bool decode;
475 bool rename;
476 bool iew;
477 bool commit;
478 };
479
480 /** Tracks which stages are telling fetch to stall. */
481 Stalls stalls[Impl::MaxThreads];
482
483 /** Decode to fetch delay, in ticks. */
484 unsigned decodeToFetchDelay;
485
486 /** Rename to fetch delay, in ticks. */
487 unsigned renameToFetchDelay;
488
489 /** IEW to fetch delay, in ticks. */
490 unsigned iewToFetchDelay;
491
492 /** Commit to fetch delay, in ticks. */
493 unsigned commitToFetchDelay;
494
495 /** The width of fetch in instructions. */
496 unsigned fetchWidth;
497
498 /** Is the cache blocked? If so no threads can access it. */
499 bool cacheBlocked;
500
501 /** The packet that is waiting to be retried. */
502 PacketPtr retryPkt;
503
504 /** The thread that is waiting on the cache to tell fetch to retry. */
505 ThreadID retryTid;
506
507 /** Cache block size. */
508 int cacheBlkSize;
509
510 /** Mask to get a cache block's address. */
511 Addr cacheBlkMask;
512
513 /** The cache line being fetched. */
514 uint8_t *cacheData[Impl::MaxThreads];
515
516 /** The PC of the cacheline that has been loaded. */
517 Addr cacheDataPC[Impl::MaxThreads];
518
519 /** Whether or not the cache data is valid. */
520 bool cacheDataValid[Impl::MaxThreads];
521
522 /** Size of instructions. */
523 int instSize;
524
525 /** Icache stall statistics. */
526 Counter lastIcacheStall[Impl::MaxThreads];
527
528 /** List of Active Threads */
529 std::list<ThreadID> *activeThreads;
530
531 /** Number of threads. */
532 ThreadID numThreads;
533
534 /** Number of threads that are actively fetching. */
535 ThreadID numFetchingThreads;
536
537 /** Thread ID being fetched. */
538 ThreadID threadFetched;
539
540 /** Checks if there is an interrupt pending. If there is, fetch
541 * must stop once it is not fetching PAL instructions.
542 */
543 bool interruptPending;
544
545 /** Is there a drain pending. */
546 bool drainPending;
547
548 /** Records if fetch is switched out. */
549 bool switchedOut;
550
551 /** Set to true if a pipelined I-cache request should be issued. */
552 bool issuePipelinedIfetch[Impl::MaxThreads];
553
554 /** Event used to delay fault generation of translation faults */
555 FinishTranslationEvent finishTranslationEvent;
556
557 // @todo: Consider making these vectors and tracking on a per thread basis.
558 /** Stat for total number of cycles stalled due to an icache miss. */
559 Stats::Scalar icacheStallCycles;
560 /** Stat for total number of fetched instructions. */
561 Stats::Scalar fetchedInsts;
562 /** Total number of fetched branches. */
563 Stats::Scalar fetchedBranches;
564 /** Stat for total number of predicted branches. */
565 Stats::Scalar predictedBranches;
566 /** Stat for total number of cycles spent fetching. */
567 Stats::Scalar fetchCycles;
568 /** Stat for total number of cycles spent squashing. */
569 Stats::Scalar fetchSquashCycles;
570 /** Stat for total number of cycles spent waiting for translation */
571 Stats::Scalar fetchTlbCycles;
572 /** Stat for total number of cycles spent blocked due to other stages in
573 * the pipeline.
574 */
575 Stats::Scalar fetchIdleCycles;
576 /** Total number of cycles spent blocked. */
577 Stats::Scalar fetchBlockedCycles;
578 /** Total number of cycles spent in any other state. */
579 Stats::Scalar fetchMiscStallCycles;
580 /** Total number of cycles spent in waiting for drains. */
581 Stats::Scalar fetchPendingDrainCycles;
582 /** Total number of stall cycles caused by no active threads to run. */
583 Stats::Scalar fetchNoActiveThreadStallCycles;
584 /** Total number of stall cycles caused by pending traps. */
585 Stats::Scalar fetchPendingTrapStallCycles;
586 /** Total number of stall cycles caused by pending quiesce instructions. */
587 Stats::Scalar fetchPendingQuiesceStallCycles;
588 /** Total number of stall cycles caused by I-cache wait retrys. */
589 Stats::Scalar fetchIcacheWaitRetryStallCycles;
590 /** Stat for total number of fetched cache lines. */
591 Stats::Scalar fetchedCacheLines;
592 /** Total number of outstanding icache accesses that were dropped
593 * due to a squash.
594 */
595 Stats::Scalar fetchIcacheSquashes;
596 /** Total number of outstanding tlb accesses that were dropped
597 * due to a squash.
598 */
599 Stats::Scalar fetchTlbSquashes;
600 /** Distribution of number of instructions fetched each cycle. */
601 Stats::Distribution fetchNisnDist;
602 /** Rate of how often fetch was idle. */
603 Stats::Formula idleRate;
604 /** Number of branch fetches per cycle. */
605 Stats::Formula branchRate;
606 /** Number of instruction fetched per cycle. */
607 Stats::Formula fetchRate;
608};
609
610#endif //__CPU_O3_FETCH_HH__
| 398 /** BPredUnit. */
399 BPredUnit branchPred;
400
401 /** Predecoder. */
402 TheISA::Predecoder predecoder;
403
404 TheISA::PCState pc[Impl::MaxThreads];
405
406 Addr fetchOffset[Impl::MaxThreads];
407
408 StaticInstPtr macroop[Impl::MaxThreads];
409
410 /** Can the fetch stage redirect from an interrupt on this instruction? */
411 bool delayedCommit[Impl::MaxThreads];
412
413 /** Memory request used to access cache. */
414 RequestPtr memReq[Impl::MaxThreads];
415
416 /** Variable that tracks if fetch has written to the time buffer this
417 * cycle. Used to tell CPU if there is activity this cycle.
418 */
419 bool wroteToTimeBuffer;
420
421 /** Tracks how many instructions has been fetched this cycle. */
422 int numInst;
423
424 /** Source of possible stalls. */
425 struct Stalls {
426 bool decode;
427 bool rename;
428 bool iew;
429 bool commit;
430 };
431
432 /** Tracks which stages are telling fetch to stall. */
433 Stalls stalls[Impl::MaxThreads];
434
435 /** Decode to fetch delay, in ticks. */
436 unsigned decodeToFetchDelay;
437
438 /** Rename to fetch delay, in ticks. */
439 unsigned renameToFetchDelay;
440
441 /** IEW to fetch delay, in ticks. */
442 unsigned iewToFetchDelay;
443
444 /** Commit to fetch delay, in ticks. */
445 unsigned commitToFetchDelay;
446
447 /** The width of fetch in instructions. */
448 unsigned fetchWidth;
449
450 /** Is the cache blocked? If so no threads can access it. */
451 bool cacheBlocked;
452
453 /** The packet that is waiting to be retried. */
454 PacketPtr retryPkt;
455
456 /** The thread that is waiting on the cache to tell fetch to retry. */
457 ThreadID retryTid;
458
459 /** Cache block size. */
460 int cacheBlkSize;
461
462 /** Mask to get a cache block's address. */
463 Addr cacheBlkMask;
464
465 /** The cache line being fetched. */
466 uint8_t *cacheData[Impl::MaxThreads];
467
468 /** The PC of the cacheline that has been loaded. */
469 Addr cacheDataPC[Impl::MaxThreads];
470
471 /** Whether or not the cache data is valid. */
472 bool cacheDataValid[Impl::MaxThreads];
473
474 /** Size of instructions. */
475 int instSize;
476
477 /** Icache stall statistics. */
478 Counter lastIcacheStall[Impl::MaxThreads];
479
480 /** List of Active Threads */
481 std::list<ThreadID> *activeThreads;
482
483 /** Number of threads. */
484 ThreadID numThreads;
485
486 /** Number of threads that are actively fetching. */
487 ThreadID numFetchingThreads;
488
489 /** Thread ID being fetched. */
490 ThreadID threadFetched;
491
492 /** Checks if there is an interrupt pending. If there is, fetch
493 * must stop once it is not fetching PAL instructions.
494 */
495 bool interruptPending;
496
497 /** Is there a drain pending. */
498 bool drainPending;
499
500 /** Records if fetch is switched out. */
501 bool switchedOut;
502
503 /** Set to true if a pipelined I-cache request should be issued. */
504 bool issuePipelinedIfetch[Impl::MaxThreads];
505
506 /** Event used to delay fault generation of translation faults */
507 FinishTranslationEvent finishTranslationEvent;
508
509 // @todo: Consider making these vectors and tracking on a per thread basis.
510 /** Stat for total number of cycles stalled due to an icache miss. */
511 Stats::Scalar icacheStallCycles;
512 /** Stat for total number of fetched instructions. */
513 Stats::Scalar fetchedInsts;
514 /** Total number of fetched branches. */
515 Stats::Scalar fetchedBranches;
516 /** Stat for total number of predicted branches. */
517 Stats::Scalar predictedBranches;
518 /** Stat for total number of cycles spent fetching. */
519 Stats::Scalar fetchCycles;
520 /** Stat for total number of cycles spent squashing. */
521 Stats::Scalar fetchSquashCycles;
522 /** Stat for total number of cycles spent waiting for translation */
523 Stats::Scalar fetchTlbCycles;
524 /** Stat for total number of cycles spent blocked due to other stages in
525 * the pipeline.
526 */
527 Stats::Scalar fetchIdleCycles;
528 /** Total number of cycles spent blocked. */
529 Stats::Scalar fetchBlockedCycles;
530 /** Total number of cycles spent in any other state. */
531 Stats::Scalar fetchMiscStallCycles;
532 /** Total number of cycles spent in waiting for drains. */
533 Stats::Scalar fetchPendingDrainCycles;
534 /** Total number of stall cycles caused by no active threads to run. */
535 Stats::Scalar fetchNoActiveThreadStallCycles;
536 /** Total number of stall cycles caused by pending traps. */
537 Stats::Scalar fetchPendingTrapStallCycles;
538 /** Total number of stall cycles caused by pending quiesce instructions. */
539 Stats::Scalar fetchPendingQuiesceStallCycles;
540 /** Total number of stall cycles caused by I-cache wait retrys. */
541 Stats::Scalar fetchIcacheWaitRetryStallCycles;
542 /** Stat for total number of fetched cache lines. */
543 Stats::Scalar fetchedCacheLines;
544 /** Total number of outstanding icache accesses that were dropped
545 * due to a squash.
546 */
547 Stats::Scalar fetchIcacheSquashes;
548 /** Total number of outstanding tlb accesses that were dropped
549 * due to a squash.
550 */
551 Stats::Scalar fetchTlbSquashes;
552 /** Distribution of number of instructions fetched each cycle. */
553 Stats::Distribution fetchNisnDist;
554 /** Rate of how often fetch was idle. */
555 Stats::Formula idleRate;
556 /** Number of branch fetches per cycle. */
557 Stats::Formula branchRate;
558 /** Number of instruction fetched per cycle. */
559 Stats::Formula fetchRate;
560};
561
562#endif //__CPU_O3_FETCH_HH__
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