1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
|
39#include "config/the_isa.hh"
40#include "cpu/pc_event.hh"
41#include "mem/packet.hh"
42#include "mem/port.hh"
43#include "sim/eventq.hh"
44
45class DerivO3CPUParams;
46
47/**
48 * DefaultFetch class handles both single threaded and SMT fetch. Its
49 * width is specified by the parameters; each cycle it tries to fetch
50 * that many instructions. It supports using a branch predictor to
51 * predict direction and targets.
52 * It supports the idling functionality of the CPU by indicating to
53 * the CPU when it is active and inactive.
54 */
55template <class Impl>
56class DefaultFetch
57{
58 public:
59 /** Typedefs from Impl. */
60 typedef typename Impl::CPUPol CPUPol;
61 typedef typename Impl::DynInst DynInst;
62 typedef typename Impl::DynInstPtr DynInstPtr;
63 typedef typename Impl::O3CPU O3CPU;
64
65 /** Typedefs from the CPU policy. */
66 typedef typename CPUPol::BPredUnit BPredUnit;
67 typedef typename CPUPol::FetchStruct FetchStruct;
68 typedef typename CPUPol::TimeStruct TimeStruct;
69
70 /** Typedefs from ISA. */
71 typedef TheISA::MachInst MachInst;
72 typedef TheISA::ExtMachInst ExtMachInst;
73
74 /** IcachePort class for DefaultFetch. Handles doing the
75 * communication with the cache/memory.
76 */
77 class IcachePort : public Port
78 {
79 protected:
80 /** Pointer to fetch. */
81 DefaultFetch<Impl> *fetch;
82
83 public:
84 /** Default constructor. */
85 IcachePort(DefaultFetch<Impl> *_fetch)
86 : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch)
87 { }
88
89 bool snoopRangeSent;
90
91 virtual void setPeer(Port *port);
92
93 protected:
94 /** Atomic version of receive. Panics. */
95 virtual Tick recvAtomic(PacketPtr pkt);
96
97 /** Functional version of receive. Panics. */
98 virtual void recvFunctional(PacketPtr pkt);
99
100 /** Receives status change. Other than range changing, panics. */
101 virtual void recvStatusChange(Status status);
102
103 /** Returns the address ranges of this device. */
104 virtual void getDeviceAddressRanges(AddrRangeList &resp,
105 bool &snoop)
106 { resp.clear(); snoop = true; }
107
108 /** Timing version of receive. Handles setting fetch to the
109 * proper status to start fetching. */
110 virtual bool recvTiming(PacketPtr pkt);
111
112 /** Handles doing a retry of a failed fetch. */
113 virtual void recvRetry();
114 };
115
116
117 public:
118 /** Overall fetch status. Used to determine if the CPU can
119 * deschedule itsef due to a lack of activity.
120 */
121 enum FetchStatus {
122 Active,
123 Inactive
124 };
125
126 /** Individual thread status. */
127 enum ThreadStatus {
128 Running,
129 Idle,
130 Squashing,
131 Blocked,
132 Fetching,
133 TrapPending,
134 QuiescePending,
135 SwitchOut,
136 IcacheWaitResponse,
137 IcacheWaitRetry,
138 IcacheAccessComplete
139 };
140
141 /** Fetching Policy, Add new policies here.*/
142 enum FetchPriority {
143 SingleThread,
144 RoundRobin,
145 Branch,
146 IQ,
147 LSQ
148 };
149
150 private:
151 /** Fetch status. */
152 FetchStatus _status;
153
154 /** Per-thread status. */
155 ThreadStatus fetchStatus[Impl::MaxThreads];
156
157 /** Fetch policy. */
158 FetchPriority fetchPolicy;
159
160 /** List that has the threads organized by priority. */
161 std::list<ThreadID> priorityList;
162
163 public:
164 /** DefaultFetch constructor. */
165 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
166
167 /** Returns the name of fetch. */
168 std::string name() const;
169
170 /** Registers statistics. */
171 void regStats();
172
173 /** Returns the icache port. */
174 Port *getIcachePort() { return icachePort; }
175
176 /** Sets the main backwards communication time buffer pointer. */
177 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
178
179 /** Sets pointer to list of active threads. */
180 void setActiveThreads(std::list<ThreadID> *at_ptr);
181
182 /** Sets pointer to time buffer used to communicate to the next stage. */
183 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
184
185 /** Initialize stage. */
186 void initStage();
187
188 /** Tells the fetch stage that the Icache is set. */
189 void setIcache();
190
191 /** Processes cache completion event. */
192 void processCacheCompletion(PacketPtr pkt);
193
194 /** Begins the drain of the fetch stage. */
195 bool drain();
196
197 /** Resumes execution after a drain. */
198 void resume();
199
200 /** Tells fetch stage to prepare to be switched out. */
201 void switchOut();
202
203 /** Takes over from another CPU's thread. */
204 void takeOverFrom();
205
206 /** Checks if the fetch stage is switched out. */
207 bool isSwitchedOut() { return switchedOut; }
208
209 /** Tells fetch to wake up from a quiesce instruction. */
210 void wakeFromQuiesce();
211
212 private:
213 /** Changes the status of this stage to active, and indicates this
214 * to the CPU.
215 */
216 inline void switchToActive();
217
218 /** Changes the status of this stage to inactive, and indicates
219 * this to the CPU.
220 */
221 inline void switchToInactive();
222
223 /**
224 * Looks up in the branch predictor to see if the next PC should be
225 * either next PC+=MachInst or a branch target.
226 * @param next_PC Next PC variable passed in by reference. It is
227 * expected to be set to the current PC; it will be updated with what
228 * the next PC will be.
229 * @param next_NPC Used for ISAs which use delay slots.
230 * @return Whether or not a branch was predicted as taken.
231 */
232 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
233
234 /**
235 * Fetches the cache line that contains fetch_PC. Returns any
236 * fault that happened. Puts the data into the class variable
237 * cacheData.
238 * @param vaddr The memory address that is being fetched from.
239 * @param ret_fault The fault reference that will be set to the result of
240 * the icache access.
241 * @param tid Thread id.
242 * @param pc The actual PC of the current instruction.
243 * @return Any fault that occured.
244 */
245 bool fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid, Addr pc);
246
247 /** Squashes a specific thread and resets the PC. */
248 inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
249
250 /** Squashes a specific thread and resets the PC. Also tells the CPU to
251 * remove any instructions between fetch and decode that should be sqaushed.
252 */
253 void squashFromDecode(const TheISA::PCState &newPC,
254 const InstSeqNum &seq_num, ThreadID tid);
255
256 /** Checks if a thread is stalled. */
257 bool checkStall(ThreadID tid) const;
258
259 /** Updates overall fetch stage status; to be called at the end of each
260 * cycle. */
261 FetchStatus updateFetchStatus();
262
263 public:
264 /** Squashes a specific thread and resets the PC. Also tells the CPU to
265 * remove any instructions that are not in the ROB. The source of this
266 * squash should be the commit stage.
267 */
268 void squash(const TheISA::PCState &newPC,
269 const InstSeqNum &seq_num, ThreadID tid);
270
271 /** Ticks the fetch stage, processing all inputs signals and fetching
272 * as many instructions as possible.
273 */
274 void tick();
275
276 /** Checks all input signals and updates the status as necessary.
277 * @return: Returns if the status has changed due to input signals.
278 */
279 bool checkSignalsAndUpdate(ThreadID tid);
280
281 /** Does the actual fetching of instructions and passing them on to the
282 * next stage.
283 * @param status_change fetch() sets this variable if there was a status
284 * change (ie switching to IcacheMissStall).
285 */
286 void fetch(bool &status_change);
287
288 /** Align a PC to the start of an I-cache block. */
289 Addr icacheBlockAlignPC(Addr addr)
290 {
291 return (addr & ~(cacheBlkMask));
292 }
293
294 private:
295 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
296 StaticInstPtr curMacroop, TheISA::PCState thisPC,
297 TheISA::PCState nextPC, bool trace);
298
299 /** Handles retrying the fetch access. */
300 void recvRetry();
301
302 /** Returns the appropriate thread to fetch, given the fetch policy. */
303 ThreadID getFetchingThread(FetchPriority &fetch_priority);
304
305 /** Returns the appropriate thread to fetch using a round robin policy. */
306 ThreadID roundRobin();
307
308 /** Returns the appropriate thread to fetch using the IQ count policy. */
309 ThreadID iqCount();
310
311 /** Returns the appropriate thread to fetch using the LSQ count policy. */
312 ThreadID lsqCount();
313
314 /** Returns the appropriate thread to fetch using the branch count
315 * policy. */
316 ThreadID branchCount();
317
318 private:
319 /** Pointer to the O3CPU. */
320 O3CPU *cpu;
321
322 /** Time buffer interface. */
323 TimeBuffer<TimeStruct> *timeBuffer;
324
325 /** Wire to get decode's information from backwards time buffer. */
326 typename TimeBuffer<TimeStruct>::wire fromDecode;
327
328 /** Wire to get rename's information from backwards time buffer. */
329 typename TimeBuffer<TimeStruct>::wire fromRename;
330
331 /** Wire to get iew's information from backwards time buffer. */
332 typename TimeBuffer<TimeStruct>::wire fromIEW;
333
334 /** Wire to get commit's information from backwards time buffer. */
335 typename TimeBuffer<TimeStruct>::wire fromCommit;
336
337 /** Internal fetch instruction queue. */
338 TimeBuffer<FetchStruct> *fetchQueue;
339
340 //Might be annoying how this name is different than the queue.
341 /** Wire used to write any information heading to decode. */
342 typename TimeBuffer<FetchStruct>::wire toDecode;
343
344 /** Icache interface. */
345 IcachePort *icachePort;
346
347 /** BPredUnit. */
348 BPredUnit branchPred;
349
350 /** Predecoder. */
351 TheISA::Predecoder predecoder;
352
353 TheISA::PCState pc[Impl::MaxThreads];
354
355 Addr fetchOffset[Impl::MaxThreads];
356
357 StaticInstPtr macroop[Impl::MaxThreads];
358
359 /** Memory request used to access cache. */
360 RequestPtr memReq[Impl::MaxThreads];
361
362 /** Variable that tracks if fetch has written to the time buffer this
363 * cycle. Used to tell CPU if there is activity this cycle.
364 */
365 bool wroteToTimeBuffer;
366
367 /** Tracks how many instructions has been fetched this cycle. */
368 int numInst;
369
370 /** Source of possible stalls. */
371 struct Stalls {
372 bool decode;
373 bool rename;
374 bool iew;
375 bool commit;
376 };
377
378 /** Tracks which stages are telling fetch to stall. */
379 Stalls stalls[Impl::MaxThreads];
380
381 /** Decode to fetch delay, in ticks. */
382 unsigned decodeToFetchDelay;
383
384 /** Rename to fetch delay, in ticks. */
385 unsigned renameToFetchDelay;
386
387 /** IEW to fetch delay, in ticks. */
388 unsigned iewToFetchDelay;
389
390 /** Commit to fetch delay, in ticks. */
391 unsigned commitToFetchDelay;
392
393 /** The width of fetch in instructions. */
394 unsigned fetchWidth;
395
396 /** Is the cache blocked? If so no threads can access it. */
397 bool cacheBlocked;
398
399 /** The packet that is waiting to be retried. */
400 PacketPtr retryPkt;
401
402 /** The thread that is waiting on the cache to tell fetch to retry. */
403 ThreadID retryTid;
404
405 /** Cache block size. */
406 int cacheBlkSize;
407
408 /** Mask to get a cache block's address. */
409 Addr cacheBlkMask;
410
411 /** The cache line being fetched. */
412 uint8_t *cacheData[Impl::MaxThreads];
413
414 /** The PC of the cacheline that has been loaded. */
415 Addr cacheDataPC[Impl::MaxThreads];
416
417 /** Whether or not the cache data is valid. */
418 bool cacheDataValid[Impl::MaxThreads];
419
420 /** Size of instructions. */
421 int instSize;
422
423 /** Icache stall statistics. */
424 Counter lastIcacheStall[Impl::MaxThreads];
425
426 /** List of Active Threads */
427 std::list<ThreadID> *activeThreads;
428
429 /** Number of threads. */
430 ThreadID numThreads;
431
432 /** Number of threads that are actively fetching. */
433 ThreadID numFetchingThreads;
434
435 /** Thread ID being fetched. */
436 ThreadID threadFetched;
437
438 /** Checks if there is an interrupt pending. If there is, fetch
439 * must stop once it is not fetching PAL instructions.
440 */
441 bool interruptPending;
442
443 /** Is there a drain pending. */
444 bool drainPending;
445
446 /** Records if fetch is switched out. */
447 bool switchedOut;
448
449 // @todo: Consider making these vectors and tracking on a per thread basis.
450 /** Stat for total number of cycles stalled due to an icache miss. */
451 Stats::Scalar icacheStallCycles;
452 /** Stat for total number of fetched instructions. */
453 Stats::Scalar fetchedInsts;
454 /** Total number of fetched branches. */
455 Stats::Scalar fetchedBranches;
456 /** Stat for total number of predicted branches. */
457 Stats::Scalar predictedBranches;
458 /** Stat for total number of cycles spent fetching. */
459 Stats::Scalar fetchCycles;
460 /** Stat for total number of cycles spent squashing. */
461 Stats::Scalar fetchSquashCycles;
462 /** Stat for total number of cycles spent blocked due to other stages in
463 * the pipeline.
464 */
465 Stats::Scalar fetchIdleCycles;
466 /** Total number of cycles spent blocked. */
467 Stats::Scalar fetchBlockedCycles;
468 /** Total number of cycles spent in any other state. */
469 Stats::Scalar fetchMiscStallCycles;
470 /** Stat for total number of fetched cache lines. */
471 Stats::Scalar fetchedCacheLines;
472 /** Total number of outstanding icache accesses that were dropped
473 * due to a squash.
474 */
475 Stats::Scalar fetchIcacheSquashes;
476 /** Distribution of number of instructions fetched each cycle. */
477 Stats::Distribution fetchNisnDist;
478 /** Rate of how often fetch was idle. */
479 Stats::Formula idleRate;
480 /** Number of branch fetches per cycle. */
481 Stats::Formula branchRate;
482 /** Number of instruction fetched per cycle. */
483 Stats::Formula fetchRate;
484};
485
486#endif //__CPU_O3_FETCH_HH__
| 39#include "config/the_isa.hh"
40#include "cpu/pc_event.hh"
41#include "mem/packet.hh"
42#include "mem/port.hh"
43#include "sim/eventq.hh"
44
45class DerivO3CPUParams;
46
47/**
48 * DefaultFetch class handles both single threaded and SMT fetch. Its
49 * width is specified by the parameters; each cycle it tries to fetch
50 * that many instructions. It supports using a branch predictor to
51 * predict direction and targets.
52 * It supports the idling functionality of the CPU by indicating to
53 * the CPU when it is active and inactive.
54 */
55template <class Impl>
56class DefaultFetch
57{
58 public:
59 /** Typedefs from Impl. */
60 typedef typename Impl::CPUPol CPUPol;
61 typedef typename Impl::DynInst DynInst;
62 typedef typename Impl::DynInstPtr DynInstPtr;
63 typedef typename Impl::O3CPU O3CPU;
64
65 /** Typedefs from the CPU policy. */
66 typedef typename CPUPol::BPredUnit BPredUnit;
67 typedef typename CPUPol::FetchStruct FetchStruct;
68 typedef typename CPUPol::TimeStruct TimeStruct;
69
70 /** Typedefs from ISA. */
71 typedef TheISA::MachInst MachInst;
72 typedef TheISA::ExtMachInst ExtMachInst;
73
74 /** IcachePort class for DefaultFetch. Handles doing the
75 * communication with the cache/memory.
76 */
77 class IcachePort : public Port
78 {
79 protected:
80 /** Pointer to fetch. */
81 DefaultFetch<Impl> *fetch;
82
83 public:
84 /** Default constructor. */
85 IcachePort(DefaultFetch<Impl> *_fetch)
86 : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch)
87 { }
88
89 bool snoopRangeSent;
90
91 virtual void setPeer(Port *port);
92
93 protected:
94 /** Atomic version of receive. Panics. */
95 virtual Tick recvAtomic(PacketPtr pkt);
96
97 /** Functional version of receive. Panics. */
98 virtual void recvFunctional(PacketPtr pkt);
99
100 /** Receives status change. Other than range changing, panics. */
101 virtual void recvStatusChange(Status status);
102
103 /** Returns the address ranges of this device. */
104 virtual void getDeviceAddressRanges(AddrRangeList &resp,
105 bool &snoop)
106 { resp.clear(); snoop = true; }
107
108 /** Timing version of receive. Handles setting fetch to the
109 * proper status to start fetching. */
110 virtual bool recvTiming(PacketPtr pkt);
111
112 /** Handles doing a retry of a failed fetch. */
113 virtual void recvRetry();
114 };
115
116
117 public:
118 /** Overall fetch status. Used to determine if the CPU can
119 * deschedule itsef due to a lack of activity.
120 */
121 enum FetchStatus {
122 Active,
123 Inactive
124 };
125
126 /** Individual thread status. */
127 enum ThreadStatus {
128 Running,
129 Idle,
130 Squashing,
131 Blocked,
132 Fetching,
133 TrapPending,
134 QuiescePending,
135 SwitchOut,
136 IcacheWaitResponse,
137 IcacheWaitRetry,
138 IcacheAccessComplete
139 };
140
141 /** Fetching Policy, Add new policies here.*/
142 enum FetchPriority {
143 SingleThread,
144 RoundRobin,
145 Branch,
146 IQ,
147 LSQ
148 };
149
150 private:
151 /** Fetch status. */
152 FetchStatus _status;
153
154 /** Per-thread status. */
155 ThreadStatus fetchStatus[Impl::MaxThreads];
156
157 /** Fetch policy. */
158 FetchPriority fetchPolicy;
159
160 /** List that has the threads organized by priority. */
161 std::list<ThreadID> priorityList;
162
163 public:
164 /** DefaultFetch constructor. */
165 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
166
167 /** Returns the name of fetch. */
168 std::string name() const;
169
170 /** Registers statistics. */
171 void regStats();
172
173 /** Returns the icache port. */
174 Port *getIcachePort() { return icachePort; }
175
176 /** Sets the main backwards communication time buffer pointer. */
177 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
178
179 /** Sets pointer to list of active threads. */
180 void setActiveThreads(std::list<ThreadID> *at_ptr);
181
182 /** Sets pointer to time buffer used to communicate to the next stage. */
183 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
184
185 /** Initialize stage. */
186 void initStage();
187
188 /** Tells the fetch stage that the Icache is set. */
189 void setIcache();
190
191 /** Processes cache completion event. */
192 void processCacheCompletion(PacketPtr pkt);
193
194 /** Begins the drain of the fetch stage. */
195 bool drain();
196
197 /** Resumes execution after a drain. */
198 void resume();
199
200 /** Tells fetch stage to prepare to be switched out. */
201 void switchOut();
202
203 /** Takes over from another CPU's thread. */
204 void takeOverFrom();
205
206 /** Checks if the fetch stage is switched out. */
207 bool isSwitchedOut() { return switchedOut; }
208
209 /** Tells fetch to wake up from a quiesce instruction. */
210 void wakeFromQuiesce();
211
212 private:
213 /** Changes the status of this stage to active, and indicates this
214 * to the CPU.
215 */
216 inline void switchToActive();
217
218 /** Changes the status of this stage to inactive, and indicates
219 * this to the CPU.
220 */
221 inline void switchToInactive();
222
223 /**
224 * Looks up in the branch predictor to see if the next PC should be
225 * either next PC+=MachInst or a branch target.
226 * @param next_PC Next PC variable passed in by reference. It is
227 * expected to be set to the current PC; it will be updated with what
228 * the next PC will be.
229 * @param next_NPC Used for ISAs which use delay slots.
230 * @return Whether or not a branch was predicted as taken.
231 */
232 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
233
234 /**
235 * Fetches the cache line that contains fetch_PC. Returns any
236 * fault that happened. Puts the data into the class variable
237 * cacheData.
238 * @param vaddr The memory address that is being fetched from.
239 * @param ret_fault The fault reference that will be set to the result of
240 * the icache access.
241 * @param tid Thread id.
242 * @param pc The actual PC of the current instruction.
243 * @return Any fault that occured.
244 */
245 bool fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid, Addr pc);
246
247 /** Squashes a specific thread and resets the PC. */
248 inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
249
250 /** Squashes a specific thread and resets the PC. Also tells the CPU to
251 * remove any instructions between fetch and decode that should be sqaushed.
252 */
253 void squashFromDecode(const TheISA::PCState &newPC,
254 const InstSeqNum &seq_num, ThreadID tid);
255
256 /** Checks if a thread is stalled. */
257 bool checkStall(ThreadID tid) const;
258
259 /** Updates overall fetch stage status; to be called at the end of each
260 * cycle. */
261 FetchStatus updateFetchStatus();
262
263 public:
264 /** Squashes a specific thread and resets the PC. Also tells the CPU to
265 * remove any instructions that are not in the ROB. The source of this
266 * squash should be the commit stage.
267 */
268 void squash(const TheISA::PCState &newPC,
269 const InstSeqNum &seq_num, ThreadID tid);
270
271 /** Ticks the fetch stage, processing all inputs signals and fetching
272 * as many instructions as possible.
273 */
274 void tick();
275
276 /** Checks all input signals and updates the status as necessary.
277 * @return: Returns if the status has changed due to input signals.
278 */
279 bool checkSignalsAndUpdate(ThreadID tid);
280
281 /** Does the actual fetching of instructions and passing them on to the
282 * next stage.
283 * @param status_change fetch() sets this variable if there was a status
284 * change (ie switching to IcacheMissStall).
285 */
286 void fetch(bool &status_change);
287
288 /** Align a PC to the start of an I-cache block. */
289 Addr icacheBlockAlignPC(Addr addr)
290 {
291 return (addr & ~(cacheBlkMask));
292 }
293
294 private:
295 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
296 StaticInstPtr curMacroop, TheISA::PCState thisPC,
297 TheISA::PCState nextPC, bool trace);
298
299 /** Handles retrying the fetch access. */
300 void recvRetry();
301
302 /** Returns the appropriate thread to fetch, given the fetch policy. */
303 ThreadID getFetchingThread(FetchPriority &fetch_priority);
304
305 /** Returns the appropriate thread to fetch using a round robin policy. */
306 ThreadID roundRobin();
307
308 /** Returns the appropriate thread to fetch using the IQ count policy. */
309 ThreadID iqCount();
310
311 /** Returns the appropriate thread to fetch using the LSQ count policy. */
312 ThreadID lsqCount();
313
314 /** Returns the appropriate thread to fetch using the branch count
315 * policy. */
316 ThreadID branchCount();
317
318 private:
319 /** Pointer to the O3CPU. */
320 O3CPU *cpu;
321
322 /** Time buffer interface. */
323 TimeBuffer<TimeStruct> *timeBuffer;
324
325 /** Wire to get decode's information from backwards time buffer. */
326 typename TimeBuffer<TimeStruct>::wire fromDecode;
327
328 /** Wire to get rename's information from backwards time buffer. */
329 typename TimeBuffer<TimeStruct>::wire fromRename;
330
331 /** Wire to get iew's information from backwards time buffer. */
332 typename TimeBuffer<TimeStruct>::wire fromIEW;
333
334 /** Wire to get commit's information from backwards time buffer. */
335 typename TimeBuffer<TimeStruct>::wire fromCommit;
336
337 /** Internal fetch instruction queue. */
338 TimeBuffer<FetchStruct> *fetchQueue;
339
340 //Might be annoying how this name is different than the queue.
341 /** Wire used to write any information heading to decode. */
342 typename TimeBuffer<FetchStruct>::wire toDecode;
343
344 /** Icache interface. */
345 IcachePort *icachePort;
346
347 /** BPredUnit. */
348 BPredUnit branchPred;
349
350 /** Predecoder. */
351 TheISA::Predecoder predecoder;
352
353 TheISA::PCState pc[Impl::MaxThreads];
354
355 Addr fetchOffset[Impl::MaxThreads];
356
357 StaticInstPtr macroop[Impl::MaxThreads];
358
359 /** Memory request used to access cache. */
360 RequestPtr memReq[Impl::MaxThreads];
361
362 /** Variable that tracks if fetch has written to the time buffer this
363 * cycle. Used to tell CPU if there is activity this cycle.
364 */
365 bool wroteToTimeBuffer;
366
367 /** Tracks how many instructions has been fetched this cycle. */
368 int numInst;
369
370 /** Source of possible stalls. */
371 struct Stalls {
372 bool decode;
373 bool rename;
374 bool iew;
375 bool commit;
376 };
377
378 /** Tracks which stages are telling fetch to stall. */
379 Stalls stalls[Impl::MaxThreads];
380
381 /** Decode to fetch delay, in ticks. */
382 unsigned decodeToFetchDelay;
383
384 /** Rename to fetch delay, in ticks. */
385 unsigned renameToFetchDelay;
386
387 /** IEW to fetch delay, in ticks. */
388 unsigned iewToFetchDelay;
389
390 /** Commit to fetch delay, in ticks. */
391 unsigned commitToFetchDelay;
392
393 /** The width of fetch in instructions. */
394 unsigned fetchWidth;
395
396 /** Is the cache blocked? If so no threads can access it. */
397 bool cacheBlocked;
398
399 /** The packet that is waiting to be retried. */
400 PacketPtr retryPkt;
401
402 /** The thread that is waiting on the cache to tell fetch to retry. */
403 ThreadID retryTid;
404
405 /** Cache block size. */
406 int cacheBlkSize;
407
408 /** Mask to get a cache block's address. */
409 Addr cacheBlkMask;
410
411 /** The cache line being fetched. */
412 uint8_t *cacheData[Impl::MaxThreads];
413
414 /** The PC of the cacheline that has been loaded. */
415 Addr cacheDataPC[Impl::MaxThreads];
416
417 /** Whether or not the cache data is valid. */
418 bool cacheDataValid[Impl::MaxThreads];
419
420 /** Size of instructions. */
421 int instSize;
422
423 /** Icache stall statistics. */
424 Counter lastIcacheStall[Impl::MaxThreads];
425
426 /** List of Active Threads */
427 std::list<ThreadID> *activeThreads;
428
429 /** Number of threads. */
430 ThreadID numThreads;
431
432 /** Number of threads that are actively fetching. */
433 ThreadID numFetchingThreads;
434
435 /** Thread ID being fetched. */
436 ThreadID threadFetched;
437
438 /** Checks if there is an interrupt pending. If there is, fetch
439 * must stop once it is not fetching PAL instructions.
440 */
441 bool interruptPending;
442
443 /** Is there a drain pending. */
444 bool drainPending;
445
446 /** Records if fetch is switched out. */
447 bool switchedOut;
448
449 // @todo: Consider making these vectors and tracking on a per thread basis.
450 /** Stat for total number of cycles stalled due to an icache miss. */
451 Stats::Scalar icacheStallCycles;
452 /** Stat for total number of fetched instructions. */
453 Stats::Scalar fetchedInsts;
454 /** Total number of fetched branches. */
455 Stats::Scalar fetchedBranches;
456 /** Stat for total number of predicted branches. */
457 Stats::Scalar predictedBranches;
458 /** Stat for total number of cycles spent fetching. */
459 Stats::Scalar fetchCycles;
460 /** Stat for total number of cycles spent squashing. */
461 Stats::Scalar fetchSquashCycles;
462 /** Stat for total number of cycles spent blocked due to other stages in
463 * the pipeline.
464 */
465 Stats::Scalar fetchIdleCycles;
466 /** Total number of cycles spent blocked. */
467 Stats::Scalar fetchBlockedCycles;
468 /** Total number of cycles spent in any other state. */
469 Stats::Scalar fetchMiscStallCycles;
470 /** Stat for total number of fetched cache lines. */
471 Stats::Scalar fetchedCacheLines;
472 /** Total number of outstanding icache accesses that were dropped
473 * due to a squash.
474 */
475 Stats::Scalar fetchIcacheSquashes;
476 /** Distribution of number of instructions fetched each cycle. */
477 Stats::Distribution fetchNisnDist;
478 /** Rate of how often fetch was idle. */
479 Stats::Formula idleRate;
480 /** Number of branch fetches per cycle. */
481 Stats::Formula branchRate;
482 /** Number of instruction fetched per cycle. */
483 Stats::Formula fetchRate;
484};
485
486#endif //__CPU_O3_FETCH_HH__
|