1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "base/timebuf.hh"
39#include "cpu/pc_event.hh"
40#include "mem/packet.hh"
41#include "mem/port.hh"
42#include "sim/eventq.hh"
43
44/**
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
51 */
52template <class Impl>
53class DefaultFetch
54{
55 public:
56 /** Typedefs from Impl. */
57 typedef typename Impl::CPUPol CPUPol;
58 typedef typename Impl::DynInst DynInst;
59 typedef typename Impl::DynInstPtr DynInstPtr;
60 typedef typename Impl::O3CPU O3CPU;
61 typedef typename Impl::Params Params;
62
63 /** Typedefs from the CPU policy. */
64 typedef typename CPUPol::BPredUnit BPredUnit;
65 typedef typename CPUPol::FetchStruct FetchStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67
68 /** Typedefs from ISA. */
69 typedef TheISA::MachInst MachInst;
70 typedef TheISA::ExtMachInst ExtMachInst;
71
72 /** IcachePort class for DefaultFetch. Handles doing the
73 * communication with the cache/memory.
74 */
75 class IcachePort : public Port
76 {
77 protected:
78 /** Pointer to fetch. */
79 DefaultFetch<Impl> *fetch;
80
81 public:
82 /** Default constructor. */
83 IcachePort(DefaultFetch<Impl> *_fetch)
84 : Port(_fetch->name() + "-iport"), fetch(_fetch)
85 { }
86
87 bool snoopRangeSent;
88
89 virtual void setPeer(Port *port);
90
91 protected:
92 /** Atomic version of receive. Panics. */
93 virtual Tick recvAtomic(PacketPtr pkt);
94
95 /** Functional version of receive. Panics. */
96 virtual void recvFunctional(PacketPtr pkt);
97
98 /** Receives status change. Other than range changing, panics. */
99 virtual void recvStatusChange(Status status);
100
101 /** Returns the address ranges of this device. */
102 virtual void getDeviceAddressRanges(AddrRangeList &resp,
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "base/timebuf.hh"
39#include "cpu/pc_event.hh"
40#include "mem/packet.hh"
41#include "mem/port.hh"
42#include "sim/eventq.hh"
43
44/**
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
51 */
52template <class Impl>
53class DefaultFetch
54{
55 public:
56 /** Typedefs from Impl. */
57 typedef typename Impl::CPUPol CPUPol;
58 typedef typename Impl::DynInst DynInst;
59 typedef typename Impl::DynInstPtr DynInstPtr;
60 typedef typename Impl::O3CPU O3CPU;
61 typedef typename Impl::Params Params;
62
63 /** Typedefs from the CPU policy. */
64 typedef typename CPUPol::BPredUnit BPredUnit;
65 typedef typename CPUPol::FetchStruct FetchStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67
68 /** Typedefs from ISA. */
69 typedef TheISA::MachInst MachInst;
70 typedef TheISA::ExtMachInst ExtMachInst;
71
72 /** IcachePort class for DefaultFetch. Handles doing the
73 * communication with the cache/memory.
74 */
75 class IcachePort : public Port
76 {
77 protected:
78 /** Pointer to fetch. */
79 DefaultFetch<Impl> *fetch;
80
81 public:
82 /** Default constructor. */
83 IcachePort(DefaultFetch<Impl> *_fetch)
84 : Port(_fetch->name() + "-iport"), fetch(_fetch)
85 { }
86
87 bool snoopRangeSent;
88
89 virtual void setPeer(Port *port);
90
91 protected:
92 /** Atomic version of receive. Panics. */
93 virtual Tick recvAtomic(PacketPtr pkt);
94
95 /** Functional version of receive. Panics. */
96 virtual void recvFunctional(PacketPtr pkt);
97
98 /** Receives status change. Other than range changing, panics. */
99 virtual void recvStatusChange(Status status);
100
101 /** Returns the address ranges of this device. */
102 virtual void getDeviceAddressRanges(AddrRangeList &resp,
|
103 bool &snoop)
104 { resp.clear(); snoop = true; }
| 103 AddrRangeList &snoop)
104 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
|
105
106 /** Timing version of receive. Handles setting fetch to the
107 * proper status to start fetching. */
108 virtual bool recvTiming(PacketPtr pkt);
109
110 /** Handles doing a retry of a failed fetch. */
111 virtual void recvRetry();
112 };
113
114
115 public:
116 /** Overall fetch status. Used to determine if the CPU can
117 * deschedule itsef due to a lack of activity.
118 */
119 enum FetchStatus {
120 Active,
121 Inactive
122 };
123
124 /** Individual thread status. */
125 enum ThreadStatus {
126 Running,
127 Idle,
128 Squashing,
129 Blocked,
130 Fetching,
131 TrapPending,
132 QuiescePending,
133 SwitchOut,
134 IcacheWaitResponse,
135 IcacheWaitRetry,
136 IcacheAccessComplete
137 };
138
139 /** Fetching Policy, Add new policies here.*/
140 enum FetchPriority {
141 SingleThread,
142 RoundRobin,
143 Branch,
144 IQ,
145 LSQ
146 };
147
148 private:
149 /** Fetch status. */
150 FetchStatus _status;
151
152 /** Per-thread status. */
153 ThreadStatus fetchStatus[Impl::MaxThreads];
154
155 /** Fetch policy. */
156 FetchPriority fetchPolicy;
157
158 /** List that has the threads organized by priority. */
159 std::list<unsigned> priorityList;
160
161 public:
162 /** DefaultFetch constructor. */
163 DefaultFetch(O3CPU *_cpu, Params *params);
164
165 /** Returns the name of fetch. */
166 std::string name() const;
167
168 /** Registers statistics. */
169 void regStats();
170
171 /** Returns the icache port. */
172 Port *getIcachePort() { return icachePort; }
173
174 /** Sets the main backwards communication time buffer pointer. */
175 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
176
177 /** Sets pointer to list of active threads. */
178 void setActiveThreads(std::list<unsigned> *at_ptr);
179
180 /** Sets pointer to time buffer used to communicate to the next stage. */
181 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
182
183 /** Initialize stage. */
184 void initStage();
185
186 /** Tells the fetch stage that the Icache is set. */
187 void setIcache();
188
189 /** Processes cache completion event. */
190 void processCacheCompletion(PacketPtr pkt);
191
192 /** Begins the drain of the fetch stage. */
193 bool drain();
194
195 /** Resumes execution after a drain. */
196 void resume();
197
198 /** Tells fetch stage to prepare to be switched out. */
199 void switchOut();
200
201 /** Takes over from another CPU's thread. */
202 void takeOverFrom();
203
204 /** Checks if the fetch stage is switched out. */
205 bool isSwitchedOut() { return switchedOut; }
206
207 /** Tells fetch to wake up from a quiesce instruction. */
208 void wakeFromQuiesce();
209
210 private:
211 /** Changes the status of this stage to active, and indicates this
212 * to the CPU.
213 */
214 inline void switchToActive();
215
216 /** Changes the status of this stage to inactive, and indicates
217 * this to the CPU.
218 */
219 inline void switchToInactive();
220
221 /**
222 * Looks up in the branch predictor to see if the next PC should be
223 * either next PC+=MachInst or a branch target.
224 * @param next_PC Next PC variable passed in by reference. It is
225 * expected to be set to the current PC; it will be updated with what
226 * the next PC will be.
227 * @param next_NPC Used for ISAs which use delay slots.
228 * @return Whether or not a branch was predicted as taken.
229 */
230 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
231
232 /**
233 * Fetches the cache line that contains fetch_PC. Returns any
234 * fault that happened. Puts the data into the class variable
235 * cacheData.
236 * @param fetch_PC The PC address that is being fetched from.
237 * @param ret_fault The fault reference that will be set to the result of
238 * the icache access.
239 * @param tid Thread id.
240 * @return Any fault that occured.
241 */
242 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
243
244 /** Squashes a specific thread and resets the PC. */
245 inline void doSquash(const Addr &new_PC, const Addr &new_NPC, unsigned tid);
246
247 /** Squashes a specific thread and resets the PC. Also tells the CPU to
248 * remove any instructions between fetch and decode that should be sqaushed.
249 */
250 void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
251 const InstSeqNum &seq_num, unsigned tid);
252
253 /** Checks if a thread is stalled. */
254 bool checkStall(unsigned tid) const;
255
256 /** Updates overall fetch stage status; to be called at the end of each
257 * cycle. */
258 FetchStatus updateFetchStatus();
259
260 public:
261 /** Squashes a specific thread and resets the PC. Also tells the CPU to
262 * remove any instructions that are not in the ROB. The source of this
263 * squash should be the commit stage.
264 */
265 void squash(const Addr &new_PC, const Addr &new_NPC,
| 105
106 /** Timing version of receive. Handles setting fetch to the
107 * proper status to start fetching. */
108 virtual bool recvTiming(PacketPtr pkt);
109
110 /** Handles doing a retry of a failed fetch. */
111 virtual void recvRetry();
112 };
113
114
115 public:
116 /** Overall fetch status. Used to determine if the CPU can
117 * deschedule itsef due to a lack of activity.
118 */
119 enum FetchStatus {
120 Active,
121 Inactive
122 };
123
124 /** Individual thread status. */
125 enum ThreadStatus {
126 Running,
127 Idle,
128 Squashing,
129 Blocked,
130 Fetching,
131 TrapPending,
132 QuiescePending,
133 SwitchOut,
134 IcacheWaitResponse,
135 IcacheWaitRetry,
136 IcacheAccessComplete
137 };
138
139 /** Fetching Policy, Add new policies here.*/
140 enum FetchPriority {
141 SingleThread,
142 RoundRobin,
143 Branch,
144 IQ,
145 LSQ
146 };
147
148 private:
149 /** Fetch status. */
150 FetchStatus _status;
151
152 /** Per-thread status. */
153 ThreadStatus fetchStatus[Impl::MaxThreads];
154
155 /** Fetch policy. */
156 FetchPriority fetchPolicy;
157
158 /** List that has the threads organized by priority. */
159 std::list<unsigned> priorityList;
160
161 public:
162 /** DefaultFetch constructor. */
163 DefaultFetch(O3CPU *_cpu, Params *params);
164
165 /** Returns the name of fetch. */
166 std::string name() const;
167
168 /** Registers statistics. */
169 void regStats();
170
171 /** Returns the icache port. */
172 Port *getIcachePort() { return icachePort; }
173
174 /** Sets the main backwards communication time buffer pointer. */
175 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
176
177 /** Sets pointer to list of active threads. */
178 void setActiveThreads(std::list<unsigned> *at_ptr);
179
180 /** Sets pointer to time buffer used to communicate to the next stage. */
181 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
182
183 /** Initialize stage. */
184 void initStage();
185
186 /** Tells the fetch stage that the Icache is set. */
187 void setIcache();
188
189 /** Processes cache completion event. */
190 void processCacheCompletion(PacketPtr pkt);
191
192 /** Begins the drain of the fetch stage. */
193 bool drain();
194
195 /** Resumes execution after a drain. */
196 void resume();
197
198 /** Tells fetch stage to prepare to be switched out. */
199 void switchOut();
200
201 /** Takes over from another CPU's thread. */
202 void takeOverFrom();
203
204 /** Checks if the fetch stage is switched out. */
205 bool isSwitchedOut() { return switchedOut; }
206
207 /** Tells fetch to wake up from a quiesce instruction. */
208 void wakeFromQuiesce();
209
210 private:
211 /** Changes the status of this stage to active, and indicates this
212 * to the CPU.
213 */
214 inline void switchToActive();
215
216 /** Changes the status of this stage to inactive, and indicates
217 * this to the CPU.
218 */
219 inline void switchToInactive();
220
221 /**
222 * Looks up in the branch predictor to see if the next PC should be
223 * either next PC+=MachInst or a branch target.
224 * @param next_PC Next PC variable passed in by reference. It is
225 * expected to be set to the current PC; it will be updated with what
226 * the next PC will be.
227 * @param next_NPC Used for ISAs which use delay slots.
228 * @return Whether or not a branch was predicted as taken.
229 */
230 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
231
232 /**
233 * Fetches the cache line that contains fetch_PC. Returns any
234 * fault that happened. Puts the data into the class variable
235 * cacheData.
236 * @param fetch_PC The PC address that is being fetched from.
237 * @param ret_fault The fault reference that will be set to the result of
238 * the icache access.
239 * @param tid Thread id.
240 * @return Any fault that occured.
241 */
242 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
243
244 /** Squashes a specific thread and resets the PC. */
245 inline void doSquash(const Addr &new_PC, const Addr &new_NPC, unsigned tid);
246
247 /** Squashes a specific thread and resets the PC. Also tells the CPU to
248 * remove any instructions between fetch and decode that should be sqaushed.
249 */
250 void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
251 const InstSeqNum &seq_num, unsigned tid);
252
253 /** Checks if a thread is stalled. */
254 bool checkStall(unsigned tid) const;
255
256 /** Updates overall fetch stage status; to be called at the end of each
257 * cycle. */
258 FetchStatus updateFetchStatus();
259
260 public:
261 /** Squashes a specific thread and resets the PC. Also tells the CPU to
262 * remove any instructions that are not in the ROB. The source of this
263 * squash should be the commit stage.
264 */
265 void squash(const Addr &new_PC, const Addr &new_NPC,
|
266 const InstSeqNum &seq_num,
267 bool squash_delay_slot, unsigned tid);
| 266 const InstSeqNum &seq_num, unsigned tid);
|
268
269 /** Ticks the fetch stage, processing all inputs signals and fetching
270 * as many instructions as possible.
271 */
272 void tick();
273
274 /** Checks all input signals and updates the status as necessary.
275 * @return: Returns if the status has changed due to input signals.
276 */
277 bool checkSignalsAndUpdate(unsigned tid);
278
279 /** Does the actual fetching of instructions and passing them on to the
280 * next stage.
281 * @param status_change fetch() sets this variable if there was a status
282 * change (ie switching to IcacheMissStall).
283 */
284 void fetch(bool &status_change);
285
286 /** Align a PC to the start of an I-cache block. */
287 Addr icacheBlockAlignPC(Addr addr)
288 {
289 addr = TheISA::realPCToFetchPC(addr);
290 return (addr & ~(cacheBlkMask));
291 }
292
293 private:
294 /** Handles retrying the fetch access. */
295 void recvRetry();
296
297 /** Returns the appropriate thread to fetch, given the fetch policy. */
298 int getFetchingThread(FetchPriority &fetch_priority);
299
300 /** Returns the appropriate thread to fetch using a round robin policy. */
301 int roundRobin();
302
303 /** Returns the appropriate thread to fetch using the IQ count policy. */
304 int iqCount();
305
306 /** Returns the appropriate thread to fetch using the LSQ count policy. */
307 int lsqCount();
308
309 /** Returns the appropriate thread to fetch using the branch count policy. */
310 int branchCount();
311
312 private:
313 /** Pointer to the O3CPU. */
314 O3CPU *cpu;
315
316 /** Time buffer interface. */
317 TimeBuffer<TimeStruct> *timeBuffer;
318
319 /** Wire to get decode's information from backwards time buffer. */
320 typename TimeBuffer<TimeStruct>::wire fromDecode;
321
322 /** Wire to get rename's information from backwards time buffer. */
323 typename TimeBuffer<TimeStruct>::wire fromRename;
324
325 /** Wire to get iew's information from backwards time buffer. */
326 typename TimeBuffer<TimeStruct>::wire fromIEW;
327
328 /** Wire to get commit's information from backwards time buffer. */
329 typename TimeBuffer<TimeStruct>::wire fromCommit;
330
331 /** Internal fetch instruction queue. */
332 TimeBuffer<FetchStruct> *fetchQueue;
333
334 //Might be annoying how this name is different than the queue.
335 /** Wire used to write any information heading to decode. */
336 typename TimeBuffer<FetchStruct>::wire toDecode;
337
338 /** Icache interface. */
339 IcachePort *icachePort;
340
341 /** BPredUnit. */
342 BPredUnit branchPred;
343
344 /** Predecoder. */
345 TheISA::Predecoder predecoder;
346
347 /** Per-thread fetch PC. */
348 Addr PC[Impl::MaxThreads];
349
350 /** Per-thread next PC. */
351 Addr nextPC[Impl::MaxThreads];
352
353 /** Per-thread next Next PC.
354 * This is not a real register but is used for
355 * architectures that use a branch-delay slot.
356 * (such as MIPS or Sparc)
357 */
358 Addr nextNPC[Impl::MaxThreads];
359
360 /** Memory request used to access cache. */
361 RequestPtr memReq[Impl::MaxThreads];
362
363 /** Variable that tracks if fetch has written to the time buffer this
364 * cycle. Used to tell CPU if there is activity this cycle.
365 */
366 bool wroteToTimeBuffer;
367
368 /** Tracks how many instructions has been fetched this cycle. */
369 int numInst;
370
371 /** Source of possible stalls. */
372 struct Stalls {
373 bool decode;
374 bool rename;
375 bool iew;
376 bool commit;
377 };
378
379 /** Tracks which stages are telling fetch to stall. */
380 Stalls stalls[Impl::MaxThreads];
381
382 /** Decode to fetch delay, in ticks. */
383 unsigned decodeToFetchDelay;
384
385 /** Rename to fetch delay, in ticks. */
386 unsigned renameToFetchDelay;
387
388 /** IEW to fetch delay, in ticks. */
389 unsigned iewToFetchDelay;
390
391 /** Commit to fetch delay, in ticks. */
392 unsigned commitToFetchDelay;
393
394 /** The width of fetch in instructions. */
395 unsigned fetchWidth;
396
397 /** Is the cache blocked? If so no threads can access it. */
398 bool cacheBlocked;
399
400 /** The packet that is waiting to be retried. */
401 PacketPtr retryPkt;
402
403 /** The thread that is waiting on the cache to tell fetch to retry. */
404 int retryTid;
405
406 /** Cache block size. */
407 int cacheBlkSize;
408
409 /** Mask to get a cache block's address. */
410 Addr cacheBlkMask;
411
412 /** The cache line being fetched. */
413 uint8_t *cacheData[Impl::MaxThreads];
414
415 /** The PC of the cacheline that has been loaded. */
416 Addr cacheDataPC[Impl::MaxThreads];
417
418 /** Whether or not the cache data is valid. */
419 bool cacheDataValid[Impl::MaxThreads];
420
421 /** Size of instructions. */
422 int instSize;
423
424 /** Icache stall statistics. */
425 Counter lastIcacheStall[Impl::MaxThreads];
426
427 /** List of Active Threads */
428 std::list<unsigned> *activeThreads;
429
430 /** Number of threads. */
431 unsigned numThreads;
432
433 /** Number of threads that are actively fetching. */
434 unsigned numFetchingThreads;
435
436 /** Thread ID being fetched. */
437 int threadFetched;
438
439 /** Checks if there is an interrupt pending. If there is, fetch
440 * must stop once it is not fetching PAL instructions.
441 */
442 bool interruptPending;
443
444 /** Is there a drain pending. */
445 bool drainPending;
446
447 /** Records if fetch is switched out. */
448 bool switchedOut;
449
450 // @todo: Consider making these vectors and tracking on a per thread basis.
451 /** Stat for total number of cycles stalled due to an icache miss. */
452 Stats::Scalar<> icacheStallCycles;
453 /** Stat for total number of fetched instructions. */
454 Stats::Scalar<> fetchedInsts;
455 /** Total number of fetched branches. */
456 Stats::Scalar<> fetchedBranches;
457 /** Stat for total number of predicted branches. */
458 Stats::Scalar<> predictedBranches;
459 /** Stat for total number of cycles spent fetching. */
460 Stats::Scalar<> fetchCycles;
461 /** Stat for total number of cycles spent squashing. */
462 Stats::Scalar<> fetchSquashCycles;
463 /** Stat for total number of cycles spent blocked due to other stages in
464 * the pipeline.
465 */
466 Stats::Scalar<> fetchIdleCycles;
467 /** Total number of cycles spent blocked. */
468 Stats::Scalar<> fetchBlockedCycles;
469 /** Total number of cycles spent in any other state. */
470 Stats::Scalar<> fetchMiscStallCycles;
471 /** Stat for total number of fetched cache lines. */
472 Stats::Scalar<> fetchedCacheLines;
473 /** Total number of outstanding icache accesses that were dropped
474 * due to a squash.
475 */
476 Stats::Scalar<> fetchIcacheSquashes;
477 /** Distribution of number of instructions fetched each cycle. */
478 Stats::Distribution<> fetchNisnDist;
479 /** Rate of how often fetch was idle. */
480 Stats::Formula idleRate;
481 /** Number of branch fetches per cycle. */
482 Stats::Formula branchRate;
483 /** Number of instruction fetched per cycle. */
484 Stats::Formula fetchRate;
485};
486
487#endif //__CPU_O3_FETCH_HH__
| 267
268 /** Ticks the fetch stage, processing all inputs signals and fetching
269 * as many instructions as possible.
270 */
271 void tick();
272
273 /** Checks all input signals and updates the status as necessary.
274 * @return: Returns if the status has changed due to input signals.
275 */
276 bool checkSignalsAndUpdate(unsigned tid);
277
278 /** Does the actual fetching of instructions and passing them on to the
279 * next stage.
280 * @param status_change fetch() sets this variable if there was a status
281 * change (ie switching to IcacheMissStall).
282 */
283 void fetch(bool &status_change);
284
285 /** Align a PC to the start of an I-cache block. */
286 Addr icacheBlockAlignPC(Addr addr)
287 {
288 addr = TheISA::realPCToFetchPC(addr);
289 return (addr & ~(cacheBlkMask));
290 }
291
292 private:
293 /** Handles retrying the fetch access. */
294 void recvRetry();
295
296 /** Returns the appropriate thread to fetch, given the fetch policy. */
297 int getFetchingThread(FetchPriority &fetch_priority);
298
299 /** Returns the appropriate thread to fetch using a round robin policy. */
300 int roundRobin();
301
302 /** Returns the appropriate thread to fetch using the IQ count policy. */
303 int iqCount();
304
305 /** Returns the appropriate thread to fetch using the LSQ count policy. */
306 int lsqCount();
307
308 /** Returns the appropriate thread to fetch using the branch count policy. */
309 int branchCount();
310
311 private:
312 /** Pointer to the O3CPU. */
313 O3CPU *cpu;
314
315 /** Time buffer interface. */
316 TimeBuffer<TimeStruct> *timeBuffer;
317
318 /** Wire to get decode's information from backwards time buffer. */
319 typename TimeBuffer<TimeStruct>::wire fromDecode;
320
321 /** Wire to get rename's information from backwards time buffer. */
322 typename TimeBuffer<TimeStruct>::wire fromRename;
323
324 /** Wire to get iew's information from backwards time buffer. */
325 typename TimeBuffer<TimeStruct>::wire fromIEW;
326
327 /** Wire to get commit's information from backwards time buffer. */
328 typename TimeBuffer<TimeStruct>::wire fromCommit;
329
330 /** Internal fetch instruction queue. */
331 TimeBuffer<FetchStruct> *fetchQueue;
332
333 //Might be annoying how this name is different than the queue.
334 /** Wire used to write any information heading to decode. */
335 typename TimeBuffer<FetchStruct>::wire toDecode;
336
337 /** Icache interface. */
338 IcachePort *icachePort;
339
340 /** BPredUnit. */
341 BPredUnit branchPred;
342
343 /** Predecoder. */
344 TheISA::Predecoder predecoder;
345
346 /** Per-thread fetch PC. */
347 Addr PC[Impl::MaxThreads];
348
349 /** Per-thread next PC. */
350 Addr nextPC[Impl::MaxThreads];
351
352 /** Per-thread next Next PC.
353 * This is not a real register but is used for
354 * architectures that use a branch-delay slot.
355 * (such as MIPS or Sparc)
356 */
357 Addr nextNPC[Impl::MaxThreads];
358
359 /** Memory request used to access cache. */
360 RequestPtr memReq[Impl::MaxThreads];
361
362 /** Variable that tracks if fetch has written to the time buffer this
363 * cycle. Used to tell CPU if there is activity this cycle.
364 */
365 bool wroteToTimeBuffer;
366
367 /** Tracks how many instructions has been fetched this cycle. */
368 int numInst;
369
370 /** Source of possible stalls. */
371 struct Stalls {
372 bool decode;
373 bool rename;
374 bool iew;
375 bool commit;
376 };
377
378 /** Tracks which stages are telling fetch to stall. */
379 Stalls stalls[Impl::MaxThreads];
380
381 /** Decode to fetch delay, in ticks. */
382 unsigned decodeToFetchDelay;
383
384 /** Rename to fetch delay, in ticks. */
385 unsigned renameToFetchDelay;
386
387 /** IEW to fetch delay, in ticks. */
388 unsigned iewToFetchDelay;
389
390 /** Commit to fetch delay, in ticks. */
391 unsigned commitToFetchDelay;
392
393 /** The width of fetch in instructions. */
394 unsigned fetchWidth;
395
396 /** Is the cache blocked? If so no threads can access it. */
397 bool cacheBlocked;
398
399 /** The packet that is waiting to be retried. */
400 PacketPtr retryPkt;
401
402 /** The thread that is waiting on the cache to tell fetch to retry. */
403 int retryTid;
404
405 /** Cache block size. */
406 int cacheBlkSize;
407
408 /** Mask to get a cache block's address. */
409 Addr cacheBlkMask;
410
411 /** The cache line being fetched. */
412 uint8_t *cacheData[Impl::MaxThreads];
413
414 /** The PC of the cacheline that has been loaded. */
415 Addr cacheDataPC[Impl::MaxThreads];
416
417 /** Whether or not the cache data is valid. */
418 bool cacheDataValid[Impl::MaxThreads];
419
420 /** Size of instructions. */
421 int instSize;
422
423 /** Icache stall statistics. */
424 Counter lastIcacheStall[Impl::MaxThreads];
425
426 /** List of Active Threads */
427 std::list<unsigned> *activeThreads;
428
429 /** Number of threads. */
430 unsigned numThreads;
431
432 /** Number of threads that are actively fetching. */
433 unsigned numFetchingThreads;
434
435 /** Thread ID being fetched. */
436 int threadFetched;
437
438 /** Checks if there is an interrupt pending. If there is, fetch
439 * must stop once it is not fetching PAL instructions.
440 */
441 bool interruptPending;
442
443 /** Is there a drain pending. */
444 bool drainPending;
445
446 /** Records if fetch is switched out. */
447 bool switchedOut;
448
449 // @todo: Consider making these vectors and tracking on a per thread basis.
450 /** Stat for total number of cycles stalled due to an icache miss. */
451 Stats::Scalar<> icacheStallCycles;
452 /** Stat for total number of fetched instructions. */
453 Stats::Scalar<> fetchedInsts;
454 /** Total number of fetched branches. */
455 Stats::Scalar<> fetchedBranches;
456 /** Stat for total number of predicted branches. */
457 Stats::Scalar<> predictedBranches;
458 /** Stat for total number of cycles spent fetching. */
459 Stats::Scalar<> fetchCycles;
460 /** Stat for total number of cycles spent squashing. */
461 Stats::Scalar<> fetchSquashCycles;
462 /** Stat for total number of cycles spent blocked due to other stages in
463 * the pipeline.
464 */
465 Stats::Scalar<> fetchIdleCycles;
466 /** Total number of cycles spent blocked. */
467 Stats::Scalar<> fetchBlockedCycles;
468 /** Total number of cycles spent in any other state. */
469 Stats::Scalar<> fetchMiscStallCycles;
470 /** Stat for total number of fetched cache lines. */
471 Stats::Scalar<> fetchedCacheLines;
472 /** Total number of outstanding icache accesses that were dropped
473 * due to a squash.
474 */
475 Stats::Scalar<> fetchIcacheSquashes;
476 /** Distribution of number of instructions fetched each cycle. */
477 Stats::Distribution<> fetchNisnDist;
478 /** Rate of how often fetch was idle. */
479 Stats::Formula idleRate;
480 /** Number of branch fetches per cycle. */
481 Stats::Formula branchRate;
482 /** Number of instruction fetched per cycle. */
483 Stats::Formula fetchRate;
484};
485
486#endif //__CPU_O3_FETCH_HH__
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