1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
|
40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
43/**
44 * DefaultFetch class handles both single threaded and SMT fetch. Its
45 * width is specified by the parameters; each cycle it tries to fetch
46 * that many instructions. It supports using a branch predictor to
47 * predict direction and targets.
48 * It supports the idling functionality of the CPU by indicating to
49 * the CPU when it is active and inactive.
50 */
51template <class Impl>
52class DefaultFetch
53{
54 public:
55 /** Typedefs from Impl. */
56 typedef typename Impl::CPUPol CPUPol;
57 typedef typename Impl::DynInst DynInst;
58 typedef typename Impl::DynInstPtr DynInstPtr;
59 typedef typename Impl::O3CPU O3CPU;
60 typedef typename Impl::Params Params;
61
62 /** Typedefs from the CPU policy. */
63 typedef typename CPUPol::BPredUnit BPredUnit;
64 typedef typename CPUPol::FetchStruct FetchStruct;
65 typedef typename CPUPol::TimeStruct TimeStruct;
66
67 /** Typedefs from ISA. */
68 typedef TheISA::MachInst MachInst;
69 typedef TheISA::ExtMachInst ExtMachInst;
70
71 /** IcachePort class for DefaultFetch. Handles doing the
72 * communication with the cache/memory.
73 */
74 class IcachePort : public Port
75 {
76 protected:
77 /** Pointer to fetch. */
78 DefaultFetch<Impl> *fetch;
79
80 public:
81 /** Default constructor. */
82 IcachePort(DefaultFetch<Impl> *_fetch)
83 : Port(_fetch->name() + "-iport"), fetch(_fetch)
84 { }
85
86 protected:
87 /** Atomic version of receive. Panics. */
88 virtual Tick recvAtomic(PacketPtr pkt);
89
90 /** Functional version of receive. Panics. */
91 virtual void recvFunctional(PacketPtr pkt);
92
93 /** Receives status change. Other than range changing, panics. */
94 virtual void recvStatusChange(Status status);
95
96 /** Returns the address ranges of this device. */
97 virtual void getDeviceAddressRanges(AddrRangeList &resp,
98 AddrRangeList &snoop)
99 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
100
101 /** Timing version of receive. Handles setting fetch to the
102 * proper status to start fetching. */
103 virtual bool recvTiming(PacketPtr pkt);
104
105 /** Handles doing a retry of a failed fetch. */
106 virtual void recvRetry();
107 };
108
109
110 public:
111 /** Overall fetch status. Used to determine if the CPU can
112 * deschedule itsef due to a lack of activity.
113 */
114 enum FetchStatus {
115 Active,
116 Inactive
117 };
118
119 /** Individual thread status. */
120 enum ThreadStatus {
121 Running,
122 Idle,
123 Squashing,
124 Blocked,
125 Fetching,
126 TrapPending,
127 QuiescePending,
128 SwitchOut,
129 IcacheWaitResponse,
130 IcacheWaitRetry,
131 IcacheAccessComplete
132 };
133
134 /** Fetching Policy, Add new policies here.*/
135 enum FetchPriority {
136 SingleThread,
137 RoundRobin,
138 Branch,
139 IQ,
140 LSQ
141 };
142
143 private:
144 /** Fetch status. */
145 FetchStatus _status;
146
147 /** Per-thread status. */
148 ThreadStatus fetchStatus[Impl::MaxThreads];
149
150 /** Fetch policy. */
151 FetchPriority fetchPolicy;
152
153 /** List that has the threads organized by priority. */
154 std::list<unsigned> priorityList;
155
156 public:
157 /** DefaultFetch constructor. */
158 DefaultFetch(Params *params);
159
160 /** Returns the name of fetch. */
161 std::string name() const;
162
163 /** Registers statistics. */
164 void regStats();
165
166 /** Returns the icache port. */
167 Port *getIcachePort() { return icachePort; }
168
169 /** Sets CPU pointer. */
170 void setCPU(O3CPU *cpu_ptr);
171
172 /** Sets the main backwards communication time buffer pointer. */
173 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
174
175 /** Sets pointer to list of active threads. */
176 void setActiveThreads(std::list<unsigned> *at_ptr);
177
178 /** Sets pointer to time buffer used to communicate to the next stage. */
179 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
180
181 /** Initialize stage. */
182 void initStage();
183
184 /** Processes cache completion event. */
185 void processCacheCompletion(PacketPtr pkt);
186
187 /** Begins the drain of the fetch stage. */
188 bool drain();
189
190 /** Resumes execution after a drain. */
191 void resume();
192
193 /** Tells fetch stage to prepare to be switched out. */
194 void switchOut();
195
196 /** Takes over from another CPU's thread. */
197 void takeOverFrom();
198
199 /** Checks if the fetch stage is switched out. */
200 bool isSwitchedOut() { return switchedOut; }
201
202 /** Tells fetch to wake up from a quiesce instruction. */
203 void wakeFromQuiesce();
204
205 private:
206 /** Changes the status of this stage to active, and indicates this
207 * to the CPU.
208 */
209 inline void switchToActive();
210
211 /** Changes the status of this stage to inactive, and indicates
212 * this to the CPU.
213 */
214 inline void switchToInactive();
215
216 /**
217 * Looks up in the branch predictor to see if the next PC should be
218 * either next PC+=MachInst or a branch target.
219 * @param next_PC Next PC variable passed in by reference. It is
220 * expected to be set to the current PC; it will be updated with what
221 * the next PC will be.
222 * @param next_NPC Used for ISAs which use delay slots.
223 * @return Whether or not a branch was predicted as taken.
224 */
225 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
226
227 /**
228 * Fetches the cache line that contains fetch_PC. Returns any
229 * fault that happened. Puts the data into the class variable
230 * cacheData.
231 * @param fetch_PC The PC address that is being fetched from.
232 * @param ret_fault The fault reference that will be set to the result of
233 * the icache access.
234 * @param tid Thread id.
235 * @return Any fault that occured.
236 */
237 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
238
239 /** Squashes a specific thread and resets the PC. */
240 inline void doSquash(const Addr &new_PC, unsigned tid);
241
242 /** Squashes a specific thread and resets the PC. Also tells the CPU to
243 * remove any instructions between fetch and decode that should be sqaushed.
244 */
245 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
246 unsigned tid);
247
248 /** Checks if a thread is stalled. */
249 bool checkStall(unsigned tid) const;
250
251 /** Updates overall fetch stage status; to be called at the end of each
252 * cycle. */
253 FetchStatus updateFetchStatus();
254
255 public:
256 /** Squashes a specific thread and resets the PC. Also tells the CPU to
257 * remove any instructions that are not in the ROB. The source of this
258 * squash should be the commit stage.
259 */
260 void squash(const Addr &new_PC, const InstSeqNum &seq_num,
261 bool squash_delay_slot, unsigned tid);
262
263 /** Ticks the fetch stage, processing all inputs signals and fetching
264 * as many instructions as possible.
265 */
266 void tick();
267
268 /** Checks all input signals and updates the status as necessary.
269 * @return: Returns if the status has changed due to input signals.
270 */
271 bool checkSignalsAndUpdate(unsigned tid);
272
273 /** Does the actual fetching of instructions and passing them on to the
274 * next stage.
275 * @param status_change fetch() sets this variable if there was a status
276 * change (ie switching to IcacheMissStall).
277 */
278 void fetch(bool &status_change);
279
280 /** Align a PC to the start of an I-cache block. */
281 Addr icacheBlockAlignPC(Addr addr)
282 {
283 addr = TheISA::realPCToFetchPC(addr);
284 return (addr & ~(cacheBlkMask));
285 }
286
287 private:
288 /** Handles retrying the fetch access. */
289 void recvRetry();
290
291 /** Returns the appropriate thread to fetch, given the fetch policy. */
292 int getFetchingThread(FetchPriority &fetch_priority);
293
294 /** Returns the appropriate thread to fetch using a round robin policy. */
295 int roundRobin();
296
297 /** Returns the appropriate thread to fetch using the IQ count policy. */
298 int iqCount();
299
300 /** Returns the appropriate thread to fetch using the LSQ count policy. */
301 int lsqCount();
302
303 /** Returns the appropriate thread to fetch using the branch count policy. */
304 int branchCount();
305
306 private:
307 /** Pointer to the O3CPU. */
308 O3CPU *cpu;
309
310 /** Time buffer interface. */
311 TimeBuffer<TimeStruct> *timeBuffer;
312
313 /** Wire to get decode's information from backwards time buffer. */
314 typename TimeBuffer<TimeStruct>::wire fromDecode;
315
316 /** Wire to get rename's information from backwards time buffer. */
317 typename TimeBuffer<TimeStruct>::wire fromRename;
318
319 /** Wire to get iew's information from backwards time buffer. */
320 typename TimeBuffer<TimeStruct>::wire fromIEW;
321
322 /** Wire to get commit's information from backwards time buffer. */
323 typename TimeBuffer<TimeStruct>::wire fromCommit;
324
325 /** Internal fetch instruction queue. */
326 TimeBuffer<FetchStruct> *fetchQueue;
327
328 //Might be annoying how this name is different than the queue.
329 /** Wire used to write any information heading to decode. */
330 typename TimeBuffer<FetchStruct>::wire toDecode;
331
332 MemObject *mem;
333
334 /** Icache interface. */
335 IcachePort *icachePort;
336
337 /** BPredUnit. */
338 BPredUnit branchPred;
339
340 /** Per-thread fetch PC. */
341 Addr PC[Impl::MaxThreads];
342
343 /** Per-thread next PC. */
344 Addr nextPC[Impl::MaxThreads];
345
346 /** Per-thread next Next PC.
347 * This is not a real register but is used for
348 * architectures that use a branch-delay slot.
349 * (such as MIPS or Sparc)
350 */
351 Addr nextNPC[Impl::MaxThreads];
352
353 /** Memory request used to access cache. */
354 RequestPtr memReq[Impl::MaxThreads];
355
356 /** Variable that tracks if fetch has written to the time buffer this
357 * cycle. Used to tell CPU if there is activity this cycle.
358 */
359 bool wroteToTimeBuffer;
360
361 /** Tracks how many instructions has been fetched this cycle. */
362 int numInst;
363
364 /** Tracks delay slot information for threads in ISAs which use
365 * delay slots;
366 */
367 struct DelaySlotInfo {
368 InstSeqNum delaySlotSeqNum;
369 InstSeqNum branchSeqNum;
370 int numInsts;
371 Addr targetAddr;
372 bool targetReady;
373 };
374
375 DelaySlotInfo delaySlotInfo[Impl::MaxThreads];
376
377 /** Source of possible stalls. */
378 struct Stalls {
379 bool decode;
380 bool rename;
381 bool iew;
382 bool commit;
383 };
384
385 /** Tracks which stages are telling fetch to stall. */
386 Stalls stalls[Impl::MaxThreads];
387
388 /** Decode to fetch delay, in ticks. */
389 unsigned decodeToFetchDelay;
390
391 /** Rename to fetch delay, in ticks. */
392 unsigned renameToFetchDelay;
393
394 /** IEW to fetch delay, in ticks. */
395 unsigned iewToFetchDelay;
396
397 /** Commit to fetch delay, in ticks. */
398 unsigned commitToFetchDelay;
399
400 /** The width of fetch in instructions. */
401 unsigned fetchWidth;
402
403 /** Is the cache blocked? If so no threads can access it. */
404 bool cacheBlocked;
405
406 /** The packet that is waiting to be retried. */
407 PacketPtr retryPkt;
408
409 /** The thread that is waiting on the cache to tell fetch to retry. */
410 int retryTid;
411
412 /** Cache block size. */
413 int cacheBlkSize;
414
415 /** Mask to get a cache block's address. */
416 Addr cacheBlkMask;
417
418 /** The cache line being fetched. */
419 uint8_t *cacheData[Impl::MaxThreads];
420
421 /** The PC of the cacheline that has been loaded. */
422 Addr cacheDataPC[Impl::MaxThreads];
423
424 /** Whether or not the cache data is valid. */
425 bool cacheDataValid[Impl::MaxThreads];
426
427 /** Size of instructions. */
428 int instSize;
429
430 /** Icache stall statistics. */
431 Counter lastIcacheStall[Impl::MaxThreads];
432
433 /** List of Active Threads */
434 std::list<unsigned> *activeThreads;
435
436 /** Number of threads. */
437 unsigned numThreads;
438
439 /** Number of threads that are actively fetching. */
440 unsigned numFetchingThreads;
441
442 /** Thread ID being fetched. */
443 int threadFetched;
444
445 /** Checks if there is an interrupt pending. If there is, fetch
446 * must stop once it is not fetching PAL instructions.
447 */
448 bool interruptPending;
449
450 /** Is there a drain pending. */
451 bool drainPending;
452
453 /** Records if fetch is switched out. */
454 bool switchedOut;
455
456 // @todo: Consider making these vectors and tracking on a per thread basis.
457 /** Stat for total number of cycles stalled due to an icache miss. */
458 Stats::Scalar<> icacheStallCycles;
459 /** Stat for total number of fetched instructions. */
460 Stats::Scalar<> fetchedInsts;
461 /** Total number of fetched branches. */
462 Stats::Scalar<> fetchedBranches;
463 /** Stat for total number of predicted branches. */
464 Stats::Scalar<> predictedBranches;
465 /** Stat for total number of cycles spent fetching. */
466 Stats::Scalar<> fetchCycles;
467 /** Stat for total number of cycles spent squashing. */
468 Stats::Scalar<> fetchSquashCycles;
469 /** Stat for total number of cycles spent blocked due to other stages in
470 * the pipeline.
471 */
472 Stats::Scalar<> fetchIdleCycles;
473 /** Total number of cycles spent blocked. */
474 Stats::Scalar<> fetchBlockedCycles;
475 /** Total number of cycles spent in any other state. */
476 Stats::Scalar<> fetchMiscStallCycles;
477 /** Stat for total number of fetched cache lines. */
478 Stats::Scalar<> fetchedCacheLines;
479 /** Total number of outstanding icache accesses that were dropped
480 * due to a squash.
481 */
482 Stats::Scalar<> fetchIcacheSquashes;
483 /** Distribution of number of instructions fetched each cycle. */
484 Stats::Distribution<> fetchNisnDist;
485 /** Rate of how often fetch was idle. */
486 Stats::Formula idleRate;
487 /** Number of branch fetches per cycle. */
488 Stats::Formula branchRate;
489 /** Number of instruction fetched per cycle. */
490 Stats::Formula fetchRate;
491};
492
493#endif //__CPU_O3_FETCH_HH__
| 40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
43/**
44 * DefaultFetch class handles both single threaded and SMT fetch. Its
45 * width is specified by the parameters; each cycle it tries to fetch
46 * that many instructions. It supports using a branch predictor to
47 * predict direction and targets.
48 * It supports the idling functionality of the CPU by indicating to
49 * the CPU when it is active and inactive.
50 */
51template <class Impl>
52class DefaultFetch
53{
54 public:
55 /** Typedefs from Impl. */
56 typedef typename Impl::CPUPol CPUPol;
57 typedef typename Impl::DynInst DynInst;
58 typedef typename Impl::DynInstPtr DynInstPtr;
59 typedef typename Impl::O3CPU O3CPU;
60 typedef typename Impl::Params Params;
61
62 /** Typedefs from the CPU policy. */
63 typedef typename CPUPol::BPredUnit BPredUnit;
64 typedef typename CPUPol::FetchStruct FetchStruct;
65 typedef typename CPUPol::TimeStruct TimeStruct;
66
67 /** Typedefs from ISA. */
68 typedef TheISA::MachInst MachInst;
69 typedef TheISA::ExtMachInst ExtMachInst;
70
71 /** IcachePort class for DefaultFetch. Handles doing the
72 * communication with the cache/memory.
73 */
74 class IcachePort : public Port
75 {
76 protected:
77 /** Pointer to fetch. */
78 DefaultFetch<Impl> *fetch;
79
80 public:
81 /** Default constructor. */
82 IcachePort(DefaultFetch<Impl> *_fetch)
83 : Port(_fetch->name() + "-iport"), fetch(_fetch)
84 { }
85
86 protected:
87 /** Atomic version of receive. Panics. */
88 virtual Tick recvAtomic(PacketPtr pkt);
89
90 /** Functional version of receive. Panics. */
91 virtual void recvFunctional(PacketPtr pkt);
92
93 /** Receives status change. Other than range changing, panics. */
94 virtual void recvStatusChange(Status status);
95
96 /** Returns the address ranges of this device. */
97 virtual void getDeviceAddressRanges(AddrRangeList &resp,
98 AddrRangeList &snoop)
99 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
100
101 /** Timing version of receive. Handles setting fetch to the
102 * proper status to start fetching. */
103 virtual bool recvTiming(PacketPtr pkt);
104
105 /** Handles doing a retry of a failed fetch. */
106 virtual void recvRetry();
107 };
108
109
110 public:
111 /** Overall fetch status. Used to determine if the CPU can
112 * deschedule itsef due to a lack of activity.
113 */
114 enum FetchStatus {
115 Active,
116 Inactive
117 };
118
119 /** Individual thread status. */
120 enum ThreadStatus {
121 Running,
122 Idle,
123 Squashing,
124 Blocked,
125 Fetching,
126 TrapPending,
127 QuiescePending,
128 SwitchOut,
129 IcacheWaitResponse,
130 IcacheWaitRetry,
131 IcacheAccessComplete
132 };
133
134 /** Fetching Policy, Add new policies here.*/
135 enum FetchPriority {
136 SingleThread,
137 RoundRobin,
138 Branch,
139 IQ,
140 LSQ
141 };
142
143 private:
144 /** Fetch status. */
145 FetchStatus _status;
146
147 /** Per-thread status. */
148 ThreadStatus fetchStatus[Impl::MaxThreads];
149
150 /** Fetch policy. */
151 FetchPriority fetchPolicy;
152
153 /** List that has the threads organized by priority. */
154 std::list<unsigned> priorityList;
155
156 public:
157 /** DefaultFetch constructor. */
158 DefaultFetch(Params *params);
159
160 /** Returns the name of fetch. */
161 std::string name() const;
162
163 /** Registers statistics. */
164 void regStats();
165
166 /** Returns the icache port. */
167 Port *getIcachePort() { return icachePort; }
168
169 /** Sets CPU pointer. */
170 void setCPU(O3CPU *cpu_ptr);
171
172 /** Sets the main backwards communication time buffer pointer. */
173 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
174
175 /** Sets pointer to list of active threads. */
176 void setActiveThreads(std::list<unsigned> *at_ptr);
177
178 /** Sets pointer to time buffer used to communicate to the next stage. */
179 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
180
181 /** Initialize stage. */
182 void initStage();
183
184 /** Processes cache completion event. */
185 void processCacheCompletion(PacketPtr pkt);
186
187 /** Begins the drain of the fetch stage. */
188 bool drain();
189
190 /** Resumes execution after a drain. */
191 void resume();
192
193 /** Tells fetch stage to prepare to be switched out. */
194 void switchOut();
195
196 /** Takes over from another CPU's thread. */
197 void takeOverFrom();
198
199 /** Checks if the fetch stage is switched out. */
200 bool isSwitchedOut() { return switchedOut; }
201
202 /** Tells fetch to wake up from a quiesce instruction. */
203 void wakeFromQuiesce();
204
205 private:
206 /** Changes the status of this stage to active, and indicates this
207 * to the CPU.
208 */
209 inline void switchToActive();
210
211 /** Changes the status of this stage to inactive, and indicates
212 * this to the CPU.
213 */
214 inline void switchToInactive();
215
216 /**
217 * Looks up in the branch predictor to see if the next PC should be
218 * either next PC+=MachInst or a branch target.
219 * @param next_PC Next PC variable passed in by reference. It is
220 * expected to be set to the current PC; it will be updated with what
221 * the next PC will be.
222 * @param next_NPC Used for ISAs which use delay slots.
223 * @return Whether or not a branch was predicted as taken.
224 */
225 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
226
227 /**
228 * Fetches the cache line that contains fetch_PC. Returns any
229 * fault that happened. Puts the data into the class variable
230 * cacheData.
231 * @param fetch_PC The PC address that is being fetched from.
232 * @param ret_fault The fault reference that will be set to the result of
233 * the icache access.
234 * @param tid Thread id.
235 * @return Any fault that occured.
236 */
237 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
238
239 /** Squashes a specific thread and resets the PC. */
240 inline void doSquash(const Addr &new_PC, unsigned tid);
241
242 /** Squashes a specific thread and resets the PC. Also tells the CPU to
243 * remove any instructions between fetch and decode that should be sqaushed.
244 */
245 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
246 unsigned tid);
247
248 /** Checks if a thread is stalled. */
249 bool checkStall(unsigned tid) const;
250
251 /** Updates overall fetch stage status; to be called at the end of each
252 * cycle. */
253 FetchStatus updateFetchStatus();
254
255 public:
256 /** Squashes a specific thread and resets the PC. Also tells the CPU to
257 * remove any instructions that are not in the ROB. The source of this
258 * squash should be the commit stage.
259 */
260 void squash(const Addr &new_PC, const InstSeqNum &seq_num,
261 bool squash_delay_slot, unsigned tid);
262
263 /** Ticks the fetch stage, processing all inputs signals and fetching
264 * as many instructions as possible.
265 */
266 void tick();
267
268 /** Checks all input signals and updates the status as necessary.
269 * @return: Returns if the status has changed due to input signals.
270 */
271 bool checkSignalsAndUpdate(unsigned tid);
272
273 /** Does the actual fetching of instructions and passing them on to the
274 * next stage.
275 * @param status_change fetch() sets this variable if there was a status
276 * change (ie switching to IcacheMissStall).
277 */
278 void fetch(bool &status_change);
279
280 /** Align a PC to the start of an I-cache block. */
281 Addr icacheBlockAlignPC(Addr addr)
282 {
283 addr = TheISA::realPCToFetchPC(addr);
284 return (addr & ~(cacheBlkMask));
285 }
286
287 private:
288 /** Handles retrying the fetch access. */
289 void recvRetry();
290
291 /** Returns the appropriate thread to fetch, given the fetch policy. */
292 int getFetchingThread(FetchPriority &fetch_priority);
293
294 /** Returns the appropriate thread to fetch using a round robin policy. */
295 int roundRobin();
296
297 /** Returns the appropriate thread to fetch using the IQ count policy. */
298 int iqCount();
299
300 /** Returns the appropriate thread to fetch using the LSQ count policy. */
301 int lsqCount();
302
303 /** Returns the appropriate thread to fetch using the branch count policy. */
304 int branchCount();
305
306 private:
307 /** Pointer to the O3CPU. */
308 O3CPU *cpu;
309
310 /** Time buffer interface. */
311 TimeBuffer<TimeStruct> *timeBuffer;
312
313 /** Wire to get decode's information from backwards time buffer. */
314 typename TimeBuffer<TimeStruct>::wire fromDecode;
315
316 /** Wire to get rename's information from backwards time buffer. */
317 typename TimeBuffer<TimeStruct>::wire fromRename;
318
319 /** Wire to get iew's information from backwards time buffer. */
320 typename TimeBuffer<TimeStruct>::wire fromIEW;
321
322 /** Wire to get commit's information from backwards time buffer. */
323 typename TimeBuffer<TimeStruct>::wire fromCommit;
324
325 /** Internal fetch instruction queue. */
326 TimeBuffer<FetchStruct> *fetchQueue;
327
328 //Might be annoying how this name is different than the queue.
329 /** Wire used to write any information heading to decode. */
330 typename TimeBuffer<FetchStruct>::wire toDecode;
331
332 MemObject *mem;
333
334 /** Icache interface. */
335 IcachePort *icachePort;
336
337 /** BPredUnit. */
338 BPredUnit branchPred;
339
340 /** Per-thread fetch PC. */
341 Addr PC[Impl::MaxThreads];
342
343 /** Per-thread next PC. */
344 Addr nextPC[Impl::MaxThreads];
345
346 /** Per-thread next Next PC.
347 * This is not a real register but is used for
348 * architectures that use a branch-delay slot.
349 * (such as MIPS or Sparc)
350 */
351 Addr nextNPC[Impl::MaxThreads];
352
353 /** Memory request used to access cache. */
354 RequestPtr memReq[Impl::MaxThreads];
355
356 /** Variable that tracks if fetch has written to the time buffer this
357 * cycle. Used to tell CPU if there is activity this cycle.
358 */
359 bool wroteToTimeBuffer;
360
361 /** Tracks how many instructions has been fetched this cycle. */
362 int numInst;
363
364 /** Tracks delay slot information for threads in ISAs which use
365 * delay slots;
366 */
367 struct DelaySlotInfo {
368 InstSeqNum delaySlotSeqNum;
369 InstSeqNum branchSeqNum;
370 int numInsts;
371 Addr targetAddr;
372 bool targetReady;
373 };
374
375 DelaySlotInfo delaySlotInfo[Impl::MaxThreads];
376
377 /** Source of possible stalls. */
378 struct Stalls {
379 bool decode;
380 bool rename;
381 bool iew;
382 bool commit;
383 };
384
385 /** Tracks which stages are telling fetch to stall. */
386 Stalls stalls[Impl::MaxThreads];
387
388 /** Decode to fetch delay, in ticks. */
389 unsigned decodeToFetchDelay;
390
391 /** Rename to fetch delay, in ticks. */
392 unsigned renameToFetchDelay;
393
394 /** IEW to fetch delay, in ticks. */
395 unsigned iewToFetchDelay;
396
397 /** Commit to fetch delay, in ticks. */
398 unsigned commitToFetchDelay;
399
400 /** The width of fetch in instructions. */
401 unsigned fetchWidth;
402
403 /** Is the cache blocked? If so no threads can access it. */
404 bool cacheBlocked;
405
406 /** The packet that is waiting to be retried. */
407 PacketPtr retryPkt;
408
409 /** The thread that is waiting on the cache to tell fetch to retry. */
410 int retryTid;
411
412 /** Cache block size. */
413 int cacheBlkSize;
414
415 /** Mask to get a cache block's address. */
416 Addr cacheBlkMask;
417
418 /** The cache line being fetched. */
419 uint8_t *cacheData[Impl::MaxThreads];
420
421 /** The PC of the cacheline that has been loaded. */
422 Addr cacheDataPC[Impl::MaxThreads];
423
424 /** Whether or not the cache data is valid. */
425 bool cacheDataValid[Impl::MaxThreads];
426
427 /** Size of instructions. */
428 int instSize;
429
430 /** Icache stall statistics. */
431 Counter lastIcacheStall[Impl::MaxThreads];
432
433 /** List of Active Threads */
434 std::list<unsigned> *activeThreads;
435
436 /** Number of threads. */
437 unsigned numThreads;
438
439 /** Number of threads that are actively fetching. */
440 unsigned numFetchingThreads;
441
442 /** Thread ID being fetched. */
443 int threadFetched;
444
445 /** Checks if there is an interrupt pending. If there is, fetch
446 * must stop once it is not fetching PAL instructions.
447 */
448 bool interruptPending;
449
450 /** Is there a drain pending. */
451 bool drainPending;
452
453 /** Records if fetch is switched out. */
454 bool switchedOut;
455
456 // @todo: Consider making these vectors and tracking on a per thread basis.
457 /** Stat for total number of cycles stalled due to an icache miss. */
458 Stats::Scalar<> icacheStallCycles;
459 /** Stat for total number of fetched instructions. */
460 Stats::Scalar<> fetchedInsts;
461 /** Total number of fetched branches. */
462 Stats::Scalar<> fetchedBranches;
463 /** Stat for total number of predicted branches. */
464 Stats::Scalar<> predictedBranches;
465 /** Stat for total number of cycles spent fetching. */
466 Stats::Scalar<> fetchCycles;
467 /** Stat for total number of cycles spent squashing. */
468 Stats::Scalar<> fetchSquashCycles;
469 /** Stat for total number of cycles spent blocked due to other stages in
470 * the pipeline.
471 */
472 Stats::Scalar<> fetchIdleCycles;
473 /** Total number of cycles spent blocked. */
474 Stats::Scalar<> fetchBlockedCycles;
475 /** Total number of cycles spent in any other state. */
476 Stats::Scalar<> fetchMiscStallCycles;
477 /** Stat for total number of fetched cache lines. */
478 Stats::Scalar<> fetchedCacheLines;
479 /** Total number of outstanding icache accesses that were dropped
480 * due to a squash.
481 */
482 Stats::Scalar<> fetchIcacheSquashes;
483 /** Distribution of number of instructions fetched each cycle. */
484 Stats::Distribution<> fetchNisnDist;
485 /** Rate of how often fetch was idle. */
486 Stats::Formula idleRate;
487 /** Number of branch fetches per cycle. */
488 Stats::Formula branchRate;
489 /** Number of instruction fetched per cycle. */
490 Stats::Formula fetchRate;
491};
492
493#endif //__CPU_O3_FETCH_HH__
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